Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	428806449	44716475	0	0
DepthKnown_A	428806449	428705566	0	0
RvalidKnown_A	428806449	428705566	0	0
WreadyKnown_A	428806449	428705566	0	0
gen_passthru_fifo.paramCheckPass	954	954	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	44716475	0	0
T1	149174	19722	0	0
T2	128270	17135	0	0
T3	86994	8457	0	0
T31	306371	34930	0	0
T32	264387	20171	0	0
T33	288121	37103	0	0
T67	147442	19775	0	0
T68	87045	9747	0	0
T118	135546	13285	0	0
T159	162226	20072	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	428705566	0	0
T1	149174	149116	0	0
T2	128270	128212	0	0
T3	86994	86939	0	0
T31	306371	306258	0	0
T32	264387	264278	0	0
T33	288121	288005	0	0
T67	147442	147387	0	0
T68	87045	86990	0	0
T118	135546	135488	0	0
T159	162226	162168	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	428705566	0	0
T1	149174	149116	0	0
T2	128270	128212	0	0
T3	86994	86939	0	0
T31	306371	306258	0	0
T32	264387	264278	0	0
T33	288121	288005	0	0
T67	147442	147387	0	0
T68	87045	86990	0	0
T118	135546	135488	0	0
T159	162226	162168	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	428705566	0	0
T1	149174	149116	0	0
T2	128270	128212	0	0
T3	86994	86939	0	0
T31	306371	306258	0	0
T32	264387	264278	0	0
T33	288121	288005	0	0
T67	147442	147387	0	0
T68	87045	86990	0	0
T118	135546	135488	0	0
T159	162226	162168	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T118	1	1	0	0
T159	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	428806449	34787231	0	0
DepthKnown_A	428806449	428705566	0	0
RvalidKnown_A	428806449	428705566	0	0
WreadyKnown_A	428806449	428705566	0	0
gen_passthru_fifo.paramCheckPass	954	954	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	34787231	0	0
T1	149174	14672	0	0
T2	128270	12071	0	0
T3	86994	6214	0	0
T31	306371	26110	0	0
T32	264387	16098	0	0
T33	288121	27727	0	0
T67	147442	14743	0	0
T68	87045	7373	0	0
T118	135546	9609	0	0
T159	162226	17682	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	428705566	0	0
T1	149174	149116	0	0
T2	128270	128212	0	0
T3	86994	86939	0	0
T31	306371	306258	0	0
T32	264387	264278	0	0
T33	288121	288005	0	0
T67	147442	147387	0	0
T68	87045	86990	0	0
T118	135546	135488	0	0
T159	162226	162168	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	428705566	0	0
T1	149174	149116	0	0
T2	128270	128212	0	0
T3	86994	86939	0	0
T31	306371	306258	0	0
T32	264387	264278	0	0
T33	288121	288005	0	0
T67	147442	147387	0	0
T68	87045	86990	0	0
T118	135546	135488	0	0
T159	162226	162168	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	428705566	0	0
T1	149174	149116	0	0
T2	128270	128212	0	0
T3	86994	86939	0	0
T31	306371	306258	0	0
T32	264387	264278	0	0
T33	288121	288005	0	0
T67	147442	147387	0	0
T68	87045	86990	0	0
T118	135546	135488	0	0
T159	162226	162168	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T118	1	1	0	0
T159	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	428806449	30066237	0	0
DepthKnown_A	428806449	428705566	0	0
RvalidKnown_A	428806449	428705566	0	0
WreadyKnown_A	428806449	428705566	0	0
gen_passthru_fifo.paramCheckPass	954	954	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	30066237	0	0
T1	149174	8577	0	0
T2	128270	6690	0	0
T3	86994	4317	0	0
T31	306371	21853	0	0
T32	264387	12201	0	0
T33	288121	20139	0	0
T67	147442	8638	0	0
T68	87045	4886	0	0
T118	135546	9186	0	0
T159	162226	7039	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	428705566	0	0
T1	149174	149116	0	0
T2	128270	128212	0	0
T3	86994	86939	0	0
T31	306371	306258	0	0
T32	264387	264278	0	0
T33	288121	288005	0	0
T67	147442	147387	0	0
T68	87045	86990	0	0
T118	135546	135488	0	0
T159	162226	162168	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	428705566	0	0
T1	149174	149116	0	0
T2	128270	128212	0	0
T3	86994	86939	0	0
T31	306371	306258	0	0
T32	264387	264278	0	0
T33	288121	288005	0	0
T67	147442	147387	0	0
T68	87045	86990	0	0
T118	135546	135488	0	0
T159	162226	162168	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	428705566	0	0
T1	149174	149116	0	0
T2	128270	128212	0	0
T3	86994	86939	0	0
T31	306371	306258	0	0
T32	264387	264278	0	0
T33	288121	288005	0	0
T67	147442	147387	0	0
T68	87045	86990	0	0
T118	135546	135488	0	0
T159	162226	162168	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T118	1	1	0	0
T159	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	428806449	26524689	0	0
DepthKnown_A	428806449	428705566	0	0
RvalidKnown_A	428806449	428705566	0	0
WreadyKnown_A	428806449	428705566	0	0
gen_passthru_fifo.paramCheckPass	954	954	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	26524689	0	0
T1	149174	8304	0	0
T2	128270	6413	0	0
T3	86994	4177	0	0
T31	306371	21200	0	0
T32	264387	11948	0	0
T33	288121	19753	0	0
T67	147442	8356	0	0
T68	87045	4743	0	0
T118	135546	9012	0	0
T159	162226	6871	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	428705566	0	0
T1	149174	149116	0	0
T2	128270	128212	0	0
T3	86994	86939	0	0
T31	306371	306258	0	0
T32	264387	264278	0	0
T33	288121	288005	0	0
T67	147442	147387	0	0
T68	87045	86990	0	0
T118	135546	135488	0	0
T159	162226	162168	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	428705566	0	0
T1	149174	149116	0	0
T2	128270	128212	0	0
T3	86994	86939	0	0
T31	306371	306258	0	0
T32	264387	264278	0	0
T33	288121	288005	0	0
T67	147442	147387	0	0
T68	87045	86990	0	0
T118	135546	135488	0	0
T159	162226	162168	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	428705566	0	0
T1	149174	149116	0	0
T2	128270	128212	0	0
T3	86994	86939	0	0
T31	306371	306258	0	0
T32	264387	264278	0	0
T33	288121	288005	0	0
T67	147442	147387	0	0
T68	87045	86990	0	0
T118	135546	135488	0	0
T159	162226	162168	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T118	1	1	0	0
T159	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	428806449	61782	0	0
DepthKnown_A	428806449	428705566	0	0
RvalidKnown_A	428806449	428705566	0	0
WreadyKnown_A	428806449	428705566	0	0
gen_passthru_fifo.paramCheckPass	954	954	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	61782	0	0
T1	149174	26	0	0
T2	128270	26	0	0
T3	86994	19	0	0
T31	306371	284	0	0
T32	264387	29	0	0
T33	288121	151	0	0
T67	147442	26	0	0
T68	87045	13	0	0
T118	135546	15	0	0
T159	162226	47	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	428705566	0	0
T1	149174	149116	0	0
T2	128270	128212	0	0
T3	86994	86939	0	0
T31	306371	306258	0	0
T32	264387	264278	0	0
T33	288121	288005	0	0
T67	147442	147387	0	0
T68	87045	86990	0	0
T118	135546	135488	0	0
T159	162226	162168	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	428705566	0	0
T1	149174	149116	0	0
T2	128270	128212	0	0
T3	86994	86939	0	0
T31	306371	306258	0	0
T32	264387	264278	0	0
T33	288121	288005	0	0
T67	147442	147387	0	0
T68	87045	86990	0	0
T118	135546	135488	0	0
T159	162226	162168	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	428705566	0	0
T1	149174	149116	0	0
T2	128270	128212	0	0
T3	86994	86939	0	0
T31	306371	306258	0	0
T32	264387	264278	0	0
T33	288121	288005	0	0
T67	147442	147387	0	0
T68	87045	86990	0	0
T118	135546	135488	0	0
T159	162226	162168	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T118	1	1	0	0
T159	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	428806449	61782	0	0
DepthKnown_A	428806449	428705566	0	0
RvalidKnown_A	428806449	428705566	0	0
WreadyKnown_A	428806449	428705566	0	0
gen_passthru_fifo.paramCheckPass	954	954	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	61782	0	0
T1	149174	26	0	0
T2	128270	26	0	0
T3	86994	19	0	0
T31	306371	284	0	0
T32	264387	29	0	0
T33	288121	151	0	0
T67	147442	26	0	0
T68	87045	13	0	0
T118	135546	15	0	0
T159	162226	47	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	428705566	0	0
T1	149174	149116	0	0
T2	128270	128212	0	0
T3	86994	86939	0	0
T31	306371	306258	0	0
T32	264387	264278	0	0
T33	288121	288005	0	0
T67	147442	147387	0	0
T68	87045	86990	0	0
T118	135546	135488	0	0
T159	162226	162168	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	428705566	0	0
T1	149174	149116	0	0
T2	128270	128212	0	0
T3	86994	86939	0	0
T31	306371	306258	0	0
T32	264387	264278	0	0
T33	288121	288005	0	0
T67	147442	147387	0	0
T68	87045	86990	0	0
T118	135546	135488	0	0
T159	162226	162168	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	428705566	0	0
T1	149174	149116	0	0
T2	128270	128212	0	0
T3	86994	86939	0	0
T31	306371	306258	0	0
T32	264387	264278	0	0
T33	288121	288005	0	0
T67	147442	147387	0	0
T68	87045	86990	0	0
T118	135546	135488	0	0
T159	162226	162168	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T118	1	1	0	0
T159	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	428806449	49717	0	0
DepthKnown_A	428806449	428705566	0	0
RvalidKnown_A	428806449	428705566	0	0
WreadyKnown_A	428806449	428705566	0	0
gen_passthru_fifo.paramCheckPass	954	954	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	49717	0	0
T1	149174	23	0	0
T2	128270	23	0	0
T3	86994	18	0	0
T31	306371	168	0	0
T32	264387	25	0	0
T33	288121	95	0	0
T67	147442	23	0	0
T68	87045	12	0	0
T118	135546	12	0	0
T159	162226	46	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	428705566	0	0
T1	149174	149116	0	0
T2	128270	128212	0	0
T3	86994	86939	0	0
T31	306371	306258	0	0
T32	264387	264278	0	0
T33	288121	288005	0	0
T67	147442	147387	0	0
T68	87045	86990	0	0
T118	135546	135488	0	0
T159	162226	162168	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	428705566	0	0
T1	149174	149116	0	0
T2	128270	128212	0	0
T3	86994	86939	0	0
T31	306371	306258	0	0
T32	264387	264278	0	0
T33	288121	288005	0	0
T67	147442	147387	0	0
T68	87045	86990	0	0
T118	135546	135488	0	0
T159	162226	162168	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	428705566	0	0
T1	149174	149116	0	0
T2	128270	128212	0	0
T3	86994	86939	0	0
T31	306371	306258	0	0
T32	264387	264278	0	0
T33	288121	288005	0	0
T67	147442	147387	0	0
T68	87045	86990	0	0
T118	135546	135488	0	0
T159	162226	162168	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T118	1	1	0	0
T159	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	428806449	49717	0	0
DepthKnown_A	428806449	428705566	0	0
RvalidKnown_A	428806449	428705566	0	0
WreadyKnown_A	428806449	428705566	0	0
gen_passthru_fifo.paramCheckPass	954	954	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	49717	0	0
T1	149174	23	0	0
T2	128270	23	0	0
T3	86994	18	0	0
T31	306371	168	0	0
T32	264387	25	0	0
T33	288121	95	0	0
T67	147442	23	0	0
T68	87045	12	0	0
T118	135546	12	0	0
T159	162226	46	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	428705566	0	0
T1	149174	149116	0	0
T2	128270	128212	0	0
T3	86994	86939	0	0
T31	306371	306258	0	0
T32	264387	264278	0	0
T33	288121	288005	0	0
T67	147442	147387	0	0
T68	87045	86990	0	0
T118	135546	135488	0	0
T159	162226	162168	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	428705566	0	0
T1	149174	149116	0	0
T2	128270	128212	0	0
T3	86994	86939	0	0
T31	306371	306258	0	0
T32	264387	264278	0	0
T33	288121	288005	0	0
T67	147442	147387	0	0
T68	87045	86990	0	0
T118	135546	135488	0	0
T159	162226	162168	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	428705566	0	0
T1	149174	149116	0	0
T2	128270	128212	0	0
T3	86994	86939	0	0
T31	306371	306258	0	0
T32	264387	264278	0	0
T33	288121	288005	0	0
T67	147442	147387	0	0
T68	87045	86990	0	0
T118	135546	135488	0	0
T159	162226	162168	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T118	1	1	0	0
T159	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	428806449	12065	0	0
DepthKnown_A	428806449	428705566	0	0
RvalidKnown_A	428806449	428705566	0	0
WreadyKnown_A	428806449	428705566	0	0
gen_passthru_fifo.paramCheckPass	954	954	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	12065	0	0
T1	149174	3	0	0
T2	128270	3	0	0
T3	86994	1	0	0
T31	306371	116	0	0
T32	264387	4	0	0
T33	288121	56	0	0
T67	147442	3	0	0
T68	87045	1	0	0
T118	135546	3	0	0
T159	162226	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	428705566	0	0
T1	149174	149116	0	0
T2	128270	128212	0	0
T3	86994	86939	0	0
T31	306371	306258	0	0
T32	264387	264278	0	0
T33	288121	288005	0	0
T67	147442	147387	0	0
T68	87045	86990	0	0
T118	135546	135488	0	0
T159	162226	162168	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	428705566	0	0
T1	149174	149116	0	0
T2	128270	128212	0	0
T3	86994	86939	0	0
T31	306371	306258	0	0
T32	264387	264278	0	0
T33	288121	288005	0	0
T67	147442	147387	0	0
T68	87045	86990	0	0
T118	135546	135488	0	0
T159	162226	162168	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	428705566	0	0
T1	149174	149116	0	0
T2	128270	128212	0	0
T3	86994	86939	0	0
T31	306371	306258	0	0
T32	264387	264278	0	0
T33	288121	288005	0	0
T67	147442	147387	0	0
T68	87045	86990	0	0
T118	135546	135488	0	0
T159	162226	162168	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T118	1	1	0	0
T159	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	428806449	12065	0	0
DepthKnown_A	428806449	428705566	0	0
RvalidKnown_A	428806449	428705566	0	0
WreadyKnown_A	428806449	428705566	0	0
gen_passthru_fifo.paramCheckPass	954	954	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	12065	0	0
T1	149174	3	0	0
T2	128270	3	0	0
T3	86994	1	0	0
T31	306371	116	0	0
T32	264387	4	0	0
T33	288121	56	0	0
T67	147442	3	0	0
T68	87045	1	0	0
T118	135546	3	0	0
T159	162226	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	428705566	0	0
T1	149174	149116	0	0
T2	128270	128212	0	0
T3	86994	86939	0	0
T31	306371	306258	0	0
T32	264387	264278	0	0
T33	288121	288005	0	0
T67	147442	147387	0	0
T68	87045	86990	0	0
T118	135546	135488	0	0
T159	162226	162168	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	428705566	0	0
T1	149174	149116	0	0
T2	128270	128212	0	0
T3	86994	86939	0	0
T31	306371	306258	0	0
T32	264387	264278	0	0
T33	288121	288005	0	0
T67	147442	147387	0	0
T68	87045	86990	0	0
T118	135546	135488	0	0
T159	162226	162168	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	428705566	0	0
T1	149174	149116	0	0
T2	128270	128212	0	0
T3	86994	86939	0	0
T31	306371	306258	0	0
T32	264387	264278	0	0
T33	288121	288005	0	0
T67	147442	147387	0	0
T68	87045	86990	0	0
T118	135546	135488	0	0
T159	162226	162168	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T118	1	1	0	0
T159	1	1	0	0