Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.20			90.20

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	89.40			89.40
tb.dut.top_earlgrey.u_uart1	90.13			90.13
tb.dut.top_earlgrey.u_uart2	90.13			90.13
tb.dut.top_earlgrey.u_uart3	90.20			90.20

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.40			89.40

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.40			89.40

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.57	92.83		90.88			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.13			90.13

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.13			90.13

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.57	92.83		90.88			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.13			90.13

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.13			90.13

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.57	92.83		90.88			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.20			90.20

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.20			90.20

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.57	92.83		90.88			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	39	31	79.49
Total Bits	306	276	90.20
Total Bits 0->1	153	138	90.20
Total Bits 1->0	153	138	90.20

Ports	39	31	79.49
Port Bits	306	276	90.20
Port Bits 0->1	153	138	90.20
Port Bits 1->0	153	138	90.20

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T32,T117,T250	Yes	T32,T117,T250	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T32,T117,T250	Yes	T32,T117,T250	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T4,*T49,*T59	Yes	T4,T49,T59	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T49,*T60,*T52	Yes	T49,T60,T52	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T32,T117,T250	Yes	T32,T117,T250	INPUT
tl_o.a_ready	Yes	Yes	T117,T250,T46	Yes	T117,T250,T46	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T117,T250,T43	Yes	T117,T250,T43	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T117,T250,T43	Yes	T117,T250,T46	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T43,T44,T45	Yes	T117,T250,T46	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T117,T250,T43	Yes	T117,T250,T46	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T99,*T117,*T250	Yes	T99,T117,T250	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T43,T44,T45	Yes	T117,T250,T46	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T117,*T250,*T43	Yes	T117,T250,T43	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T117,T250,T46	Yes	T117,T250,T46	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T330,T308,T331	Yes	T330,T308,T331	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T147,T148,T158	Yes	T147,T148,T158	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T147,T148,T158	Yes	T147,T148,T158	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T330,T308,T331	Yes	T330,T308,T331	OUTPUT
cio_rx_i	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T250,T43,T251	Yes	T250,T43,T251	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T117,T250,T251	Yes	T117,T250,T251	OUTPUT
intr_rx_watermark_o	Yes	Yes	T117,T250,T251	Yes	T117,T250,T251	OUTPUT
intr_tx_empty_o	Yes	Yes	T117,T250,T251	Yes	T117,T250,T251	OUTPUT
intr_rx_overflow_o	Yes	Yes	T117,T250,T251	Yes	T117,T250,T251	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T117,T213,T214	Yes	T117,T213,T214	OUTPUT
intr_rx_break_err_o	Yes	Yes	T117,T213,T214	Yes	T117,T213,T214	OUTPUT
intr_rx_timeout_o	Yes	Yes	T117,T213,T214	Yes	T117,T213,T214	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T117,T213,T214	Yes	T117,T213,T214	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	39	31	79.49
Total Bits	302	270	89.40
Total Bits 0->1	151	135	89.40
Total Bits 1->0	151	135	89.40

Ports	39	31	79.49
Port Bits	302	270	89.40
Port Bits 0->1	151	135	89.40
Port Bits 1->0	151	135	89.40

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T32,T117,T250	Yes	T32,T117,T250	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T32,T117,T250	Yes	T32,T117,T250	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T4,*T49,*T59	Yes	T4,T49,T59	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T49,*T60,*T52	Yes	T49,T60,T52	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T32,T117,T250	Yes	T32,T117,T250	INPUT
tl_o.a_ready	Yes	Yes	T117,T250,T46	Yes	T117,T250,T46	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T117,T250,T43	Yes	T117,T250,T43	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T117,T250,T43	Yes	T117,T250,T46	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T43,T44,T45	Yes	T117,T250,T46	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T117,T250,T43	Yes	T117,T250,T46	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T117,*T250,*T46	Yes	T117,T250,T46	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T43,T44,T45	Yes	T117,T250,T46	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T117,*T250,*T43	Yes	T117,T250,T43	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T117,T250,T46	Yes	T117,T250,T46	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T330,T106,T147	Yes	T330,T106,T147	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T147,T148,T158	Yes	T147,T148,T158	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T147,T148,T158	Yes	T147,T148,T158	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T330,T106,T147	Yes	T330,T106,T147	OUTPUT
cio_rx_i	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T250,T43,T251	Yes	T250,T43,T251	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T117,T250,T251	Yes	T117,T250,T251	OUTPUT
intr_rx_watermark_o	Yes	Yes	T117,T250,T251	Yes	T117,T250,T251	OUTPUT
intr_tx_empty_o	Yes	Yes	T117,T250,T251	Yes	T117,T250,T251	OUTPUT
intr_rx_overflow_o	Yes	Yes	T117,T250,T251	Yes	T117,T250,T251	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T117,T213,T214	Yes	T117,T213,T214	OUTPUT
intr_rx_break_err_o	Yes	Yes	T117,T213,T214	Yes	T117,T213,T214	OUTPUT
intr_rx_timeout_o	Yes	Yes	T117,T213,T214	Yes	T117,T213,T214	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T117,T213,T214	Yes	T117,T213,T214	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	39	31	79.49
Total Bits	304	274	90.13
Total Bits 0->1	152	137	90.13
Total Bits 1->0	152	137	90.13

Ports	39	31	79.49
Port Bits	304	274	90.13
Port Bits 0->1	152	137	90.13
Port Bits 1->0	152	137	90.13

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T117,T213,T263	Yes	T117,T213,T263	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T117,T213,T263	Yes	T117,T213,T263	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T4,*T49,*T59	Yes	T4,T49,T59	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T49,*T60,*T52	Yes	T49,T60,T52	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T117,T106,T213	Yes	T117,T106,T213	INPUT
tl_o.a_ready	Yes	Yes	T117,T106,T213	Yes	T117,T106,T213	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T117,T213,T263	Yes	T117,T213,T263	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T117,T213,T263	Yes	T117,T106,T213	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T217,*T99,*T310	Yes	T117,T106,T213	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T117,T213,T263	Yes	T117,T106,T213	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T99,*T117,*T213	Yes	T99,T117,T213	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T217,T99,T310	Yes	T117,T106,T213	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T117,*T213,*T263	Yes	T117,T213,T263	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T117,T106,T213	Yes	T117,T106,T213	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T106,T147,T148	Yes	T106,T147,T148	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T147,T148,T158	Yes	T147,T148,T158	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T147,T148,T158	Yes	T147,T148,T158	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T106,T147,T148	Yes	T106,T147,T148	OUTPUT
cio_rx_i	Yes	Yes	T263,T264,T265	Yes	T7,T263,T264	INPUT
cio_tx_o	Yes	Yes	T263,T264,T265	Yes	T263,T264,T265	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T117,T213,T263	Yes	T117,T213,T263	OUTPUT
intr_rx_watermark_o	Yes	Yes	T117,T213,T263	Yes	T117,T213,T263	OUTPUT
intr_tx_empty_o	Yes	Yes	T117,T213,T263	Yes	T117,T213,T263	OUTPUT
intr_rx_overflow_o	Yes	Yes	T117,T213,T263	Yes	T117,T213,T263	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T117,T213,T214	Yes	T117,T213,T214	OUTPUT
intr_rx_break_err_o	Yes	Yes	T117,T213,T214	Yes	T117,T213,T214	OUTPUT
intr_rx_timeout_o	Yes	Yes	T117,T213,T214	Yes	T117,T213,T214	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T117,T213,T214	Yes	T117,T213,T214	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	39	31	79.49
Total Bits	304	274	90.13
Total Bits 0->1	152	137	90.13
Total Bits 1->0	152	137	90.13

Ports	39	31	79.49
Port Bits	304	274	90.13
Port Bits 0->1	152	137	90.13
Port Bits 1->0	152	137	90.13

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T117,T213,T311	Yes	T117,T213,T311	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T117,T213,T311	Yes	T117,T213,T311	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T4,*T49,*T59	Yes	T4,T49,T59	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T49,*T60,*T52	Yes	T49,T60,T52	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T117,T106,T213	Yes	T117,T106,T213	INPUT
tl_o.a_ready	Yes	Yes	T117,T106,T213	Yes	T117,T106,T213	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T117,T213,T311	Yes	T117,T213,T311	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T117,T213,T311	Yes	T117,T106,T213	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T217,T99,*T310	Yes	T117,T106,T213	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T117,T213,T311	Yes	T117,T106,T213	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T99,*T117,*T213	Yes	T99,T117,T213	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T217,T99,T310	Yes	T117,T106,T213	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T117,*T213,*T311	Yes	T117,T213,T311	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T117,T106,T213	Yes	T117,T106,T213	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T331,T106,T147	Yes	T331,T106,T147	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T147,T148,T158	Yes	T147,T148,T158	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T147,T148,T158	Yes	T147,T148,T158	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T331,T106,T147	Yes	T331,T106,T147	OUTPUT
cio_rx_i	Yes	Yes	T311,T332,T333	Yes	T311,T332,T333	INPUT
cio_tx_o	Yes	Yes	T311,T332,T333	Yes	T311,T332,T333	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T117,T213,T311	Yes	T117,T213,T311	OUTPUT
intr_rx_watermark_o	Yes	Yes	T117,T213,T311	Yes	T117,T213,T311	OUTPUT
intr_tx_empty_o	Yes	Yes	T117,T213,T311	Yes	T117,T213,T311	OUTPUT
intr_rx_overflow_o	Yes	Yes	T117,T213,T311	Yes	T117,T213,T311	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T117,T213,T214	Yes	T117,T213,T214	OUTPUT
intr_rx_break_err_o	Yes	Yes	T117,T213,T214	Yes	T117,T213,T214	OUTPUT
intr_rx_timeout_o	Yes	Yes	T117,T213,T214	Yes	T117,T213,T214	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T117,T213,T214	Yes	T117,T213,T214	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	39	31	79.49
Total Bits	306	276	90.20
Total Bits 0->1	153	138	90.20
Total Bits 1->0	153	138	90.20

Ports	39	31	79.49
Port Bits	306	276	90.20
Port Bits 0->1	153	138	90.20
Port Bits 1->0	153	138	90.20

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T117,T15,T252	Yes	T117,T15,T252	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T117,T15,T252	Yes	T117,T15,T252	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T4,*T49,*T59	Yes	T4,T49,T59	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T49,*T60,*T52	Yes	T49,T60,T52	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T117,T15,T252	Yes	T117,T15,T252	INPUT
tl_o.a_ready	Yes	Yes	T117,T15,T252	Yes	T117,T15,T252	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T117,T15,T252	Yes	T117,T15,T252	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T117,T15,T252	Yes	T117,T15,T252	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T217,*T99,*T310	Yes	T117,T15,T252	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T117,T15,T252	Yes	T117,T15,T252	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T99,*T117,*T15	Yes	T99,T117,T15	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T217,T99,T310	Yes	T117,T15,T252	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T117,*T15,*T252	Yes	T117,T15,T252	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T117,T15,T252	Yes	T117,T15,T252	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T308,T106,T147	Yes	T308,T106,T147	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T147,T148,T158	Yes	T147,T148,T158	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T147,T148,T158	Yes	T147,T148,T158	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T308,T106,T147	Yes	T308,T106,T147	OUTPUT
cio_rx_i	Yes	Yes	T15,T252,T334	Yes	T15,T252,T334	INPUT
cio_tx_o	Yes	Yes	T15,T252,T334	Yes	T15,T252,T334	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T117,T15,T252	Yes	T117,T15,T252	OUTPUT
intr_rx_watermark_o	Yes	Yes	T117,T15,T252	Yes	T117,T15,T252	OUTPUT
intr_tx_empty_o	Yes	Yes	T117,T15,T252	Yes	T117,T15,T252	OUTPUT
intr_rx_overflow_o	Yes	Yes	T117,T15,T252	Yes	T117,T15,T252	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T117,T213,T214	Yes	T117,T213,T214	OUTPUT
intr_rx_break_err_o	Yes	Yes	T117,T213,T214	Yes	T117,T213,T214	OUTPUT
intr_rx_timeout_o	Yes	Yes	T117,T213,T214	Yes	T117,T213,T214	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T117,T213,T214	Yes	T117,T213,T214	OUTPUT

*Tests covering at least one bit in the range