Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.54			80.54

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	80.54			80.54

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.54			80.54

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.54			80.54

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.57	92.83		90.88			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	300	54.55
Total Bits	6824	5496	80.54
Total Bits 0->1	3412	2748	80.54
Total Bits 1->0	3412	2748	80.54

Ports	550	300	54.55
Port Bits	6824	5496	80.54
Port Bits 0->1	3412	2748	80.54
Port Bits 1->0	3412	2748	80.54

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_source[5:3]	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[5:0]	Yes	Yes	*T31,*T98,*T95	Yes	T31,T98,T95	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	No	No		No		OUTPUT
tl_rv_core_ibex__corei_o.d_source[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:3]	No	No		No		OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[0]	No	No		No		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T49,T60,T52	Yes	T49,T60,T52	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T99,T30,T100	Yes	T99,T30,T100	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T99,T28,T29	Yes	T99,T28,T29	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_opcode[1]	No	No		No		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T31,T33,T101	Yes	T31,T33,T101	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	No	No		No		OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T4,T48,T49	Yes	T4,T48,T49	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.instr_type[0]	Yes	Yes	*T31,*T32,*T33	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_rv_dm__sba_i.a_user.instr_type[3]	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T4,T48,T49	Yes	T4,T48,T49	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	No	No		No		INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[0]	No	No		No		INPUT
tl_rv_dm__sba_i.a_size[1]	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[1:0]	No	No		No		INPUT
tl_rv_dm__sba_i.a_opcode[2]	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T4,T48,T49	Yes	T4,T48,T49	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	No	No		No		OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T4,T48,T49	Yes	T4,T48,T49	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[1:0]	Yes	Yes	T4,T48,T49	Yes	T4,T48,T49	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[2]	No	No		No		OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[5:3]	Yes	Yes	T4,T48,T49	Yes	T4,T48,T49	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T48,T49,T102	Yes	T48,T49,T102	OUTPUT
tl_rv_dm__sba_o.d_sink	No	No		No		OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	No	No		No		OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[0]	No	No		No		OUTPUT
tl_rv_dm__sba_o.d_size[1]	Yes	Yes	T4,T48,T49	Yes	T4,T48,T49	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T4,*T48,*T49	Yes	T4,T48,T49	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T4,T48,T49	Yes	T4,T48,T49	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T49,T52	Yes	T49,T52	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[0]	Yes	Yes	*T49,*T52	Yes	T49,T52	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[1]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:2]	Yes	Yes	T49,T52	Yes	T49,T52	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[0]	Yes	Yes	*T49,*T52	Yes	T49,T52	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3]	Yes	Yes	T49,T52	Yes	T49,T52	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T49,T52	Yes	T49,T52	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T49,T52	Yes	T49,T52	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[0]	Yes	Yes	*T49,*T52	Yes	T49,T52	OUTPUT
tl_rv_dm__regs_o.a_source[5:1]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[0]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_size[1]	Yes	Yes	T49,T52	Yes	T49,T52	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_opcode[2]	Yes	Yes	T49,T52	Yes	T49,T52	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T49,T52	Yes	T49,T52	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T49,T52	Yes	T49,T52	INPUT
tl_rv_dm__regs_i.d_error	No	No		No		INPUT
tl_rv_dm__regs_i.d_user.data_intg[0]	Yes	Yes	*T49,*T52	Yes	T49,T52	INPUT
tl_rv_dm__regs_i.d_user.data_intg[2:1]	No	No		No		INPUT
tl_rv_dm__regs_i.d_user.data_intg[5:3]	Yes	Yes	T49,*T52	Yes	T49,T52	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6]	No	No		No		INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[1:0]	Yes	Yes	T49,T52	Yes	T49,T52	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[5:4]	Yes	Yes	T49,T52	Yes	T49,T52	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T49,T52	Yes	T49,T52	INPUT
tl_rv_dm__regs_i.d_sink	No	No		No		INPUT
tl_rv_dm__regs_i.d_source[0]	Yes	Yes	*T49,*T52	Yes	T49,T52	INPUT
tl_rv_dm__regs_i.d_source[5:1]	No	No		No		INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[0]	No	No		No		INPUT
tl_rv_dm__regs_i.d_size[1]	Yes	Yes	T49,T52	Yes	T49,T52	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T49,*T52	Yes	T49,T52	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T49,T52	Yes	T49,T52	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T49,T103,T52	Yes	T49,T103,T52	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T49,T103,T52	Yes	T49,T103,T52	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T49,T103,T52	Yes	T49,T103,T52	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T49,T103,T52	Yes	T49,T103,T52	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T49,T103,T52	Yes	T49,T103,T52	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[4:0]	Yes	Yes	*T103,*T104,*T105	Yes	T103,T104,T105	OUTPUT
tl_rv_dm__mem_o.a_source[5]	No	No		No		OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[0]	No	No		No		OUTPUT
tl_rv_dm__mem_o.a_size[1]	Yes	Yes	T49,T103,T52	Yes	T49,T103,T52	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_rv_dm__mem_o.a_opcode[2]	Yes	Yes	T49,T103,T52	Yes	T49,T103,T52	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T49,T103,T52	Yes	T49,T103,T52	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T31,T32,T33	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T103,T104,T105	Yes	T103,T104,T105	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[2:0]	Yes	Yes	*T49,*T103,*T52	Yes	T49,T103,T52	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[3]	No	No		No		INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[5:4]	Yes	Yes	*T49,*T103,*T52	Yes	T49,T103,T52	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T31,T32,T33	INPUT
tl_rv_dm__mem_i.d_sink	No	No		No		INPUT
tl_rv_dm__mem_i.d_source[4:0]	Yes	Yes	*T103,*T104,*T105	Yes	T103,T104,T105	INPUT
tl_rv_dm__mem_i.d_source[5]	No	No		No		INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[0]	No	No		No		INPUT
tl_rv_dm__mem_i.d_size[1]	Yes	Yes	T49,T103,T52	Yes	T49,T103,T52	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T31,T32,T33	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T49,T103,T52	Yes	T49,T103,T52	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T46,T43,T47	Yes	T46,T43,T47	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[4:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_source[5]	No	No		No		OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[0]	No	No		No		OUTPUT
tl_rom_ctrl__rom_o.a_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	No	No		No		INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[4]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:5]	No	No		No		INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_sink	No	No		No		INPUT
tl_rom_ctrl__rom_i.d_source[4:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_source[5]	No	No		No		INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[0]	No	No		No		INPUT
tl_rom_ctrl__rom_i.d_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	No	No		No		INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T49,T106,T52	Yes	T49,T106,T52	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T107,T49,T106	Yes	T107,T49,T106	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[0]	Yes	Yes	*T107,*T49,*T106	Yes	T107,T49,T106	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3]	Yes	Yes	T107,T49,T106	Yes	T107,T49,T106	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T49,T106,T52	Yes	T49,T106,T52	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T107,T49,T106	Yes	T107,T49,T106	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[1:0]	Yes	Yes	*T49,*T52,*T107	Yes	T49,T52,T107	OUTPUT
tl_rom_ctrl__regs_o.a_source[5:2]	No	No		No		OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[0]	No	No		No		OUTPUT
tl_rom_ctrl__regs_o.a_size[1]	Yes	Yes	T107,T49,T106	Yes	T107,T49,T106	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2]	Yes	Yes	T107,T49,T108	Yes	T107,T49,T108	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T107,T49,T106	Yes	T107,T49,T106	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T107,T49,T106	Yes	T107,T49,T106	INPUT
tl_rom_ctrl__regs_i.d_error	No	No		No		INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T108,T109,T110	Yes	T108,T109,T110	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[1:0]	Yes	Yes	T49,T52,*T106	Yes	T49,T106,T52	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[5:4]	Yes	Yes	T107,T49,T108	Yes	T107,T49,T106	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T49,T108,T109	Yes	T49,T106,T108	INPUT
tl_rom_ctrl__regs_i.d_sink	No	No		No		INPUT
tl_rom_ctrl__regs_i.d_source[1:0]	Yes	Yes	*T49,*T52,*T107	Yes	T49,T52,T107	INPUT
tl_rom_ctrl__regs_i.d_source[5:2]	No	No		No		INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[0]	No	No		No		INPUT
tl_rom_ctrl__regs_i.d_size[1]	Yes	Yes	T107,T49,T108	Yes	T107,T49,T106	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T107,*T49,*T108	Yes	T107,T49,T108	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T107,T49,T106	Yes	T107,T49,T106	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_peri_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T4,*T49,*T59	Yes	T4,T49,T59	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[0]	Yes	Yes	*T49,*T60,*T52	Yes	T49,T60,T52	OUTPUT
tl_peri_o.a_opcode[1]	No	No		No		OUTPUT
tl_peri_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	Yes	Yes	T101,T111,T107	Yes	T101,T111,T107	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	No	No		No		INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T4,*T49,*T59	Yes	T4,T49,T59	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T10,T106,T112	Yes	T10,T106,T112	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T10,T106,T112	Yes	T10,T106,T112	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[0]	Yes	Yes	*T10,*T106,*T112	Yes	T10,T106,T112	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[1]	No	No		No		OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:2]	Yes	Yes	T10,T106,T112	Yes	T10,T106,T112	OUTPUT
tl_spi_host0_o.a_user.instr_type[0]	Yes	Yes	*T10,*T106,*T112	Yes	T10,T106,T112	OUTPUT
tl_spi_host0_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_spi_host0_o.a_user.instr_type[3]	Yes	Yes	T10,T106,T112	Yes	T10,T106,T112	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T10,T106,T112	Yes	T10,T106,T112	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T10,T106,T112	Yes	T10,T106,T112	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[0]	No	No		No		OUTPUT
tl_spi_host0_o.a_source[1]	Yes	Yes	*T10,*T112,*T113	Yes	T10,T112,T113	OUTPUT
tl_spi_host0_o.a_source[5:2]	No	No		No		OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[0]	No	No		No		OUTPUT
tl_spi_host0_o.a_size[1]	Yes	Yes	T10,T106,T112	Yes	T10,T106,T112	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[0]	Yes	Yes	*T10,*T11,*T12	Yes	T10,T11,T12	OUTPUT
tl_spi_host0_o.a_opcode[1]	No	No		No		OUTPUT
tl_spi_host0_o.a_opcode[2]	Yes	Yes	T10,T112,T113	Yes	T10,T112,T113	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T10,T106,T112	Yes	T10,T106,T112	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T10,T106,T112	Yes	T10,T106,T112	INPUT
tl_spi_host0_i.d_error	No	No		No		INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T10,T112,T114	Yes	T10,T112,T114	INPUT
tl_spi_host0_i.d_user.rsp_intg[1:0]	Yes	Yes	T10,T112,T113	Yes	T10,T106,T112	INPUT
tl_spi_host0_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_spi_host0_i.d_user.rsp_intg[5:4]	Yes	Yes	T10,T112,T113	Yes	T10,T106,T112	INPUT
tl_spi_host0_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T10,T112,T114	Yes	T10,T112,T114	INPUT
tl_spi_host0_i.d_sink	No	No		No		INPUT
tl_spi_host0_i.d_source[0]	No	No		No		INPUT
tl_spi_host0_i.d_source[1]	Yes	Yes	*T10,*T112,*T113	Yes	T10,T112,T113	INPUT
tl_spi_host0_i.d_source[5:2]	No	No		No		INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[0]	No	No		No		INPUT
tl_spi_host0_i.d_size[1]	Yes	Yes	T10,T112,T113	Yes	T10,T106,T112	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T10,*T112,*T113	Yes	T10,T112,T113	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T10,T106,T112	Yes	T10,T106,T112	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T106,T112,T113	Yes	T106,T112,T113	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T106,T112,T114	Yes	T106,T112,T114	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T106,T112,T113	Yes	T106,T112,T113	OUTPUT
tl_spi_host1_o.a_user.instr_type[0]	Yes	Yes	*T106,*T112,*T113	Yes	T106,T112,T113	OUTPUT
tl_spi_host1_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_spi_host1_o.a_user.instr_type[3]	Yes	Yes	T106,T112,T113	Yes	T106,T112,T113	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T106,T112,T114	Yes	T106,T112,T114	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T106,T112,T113	Yes	T106,T112,T113	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[0]	No	No		No		OUTPUT
tl_spi_host1_o.a_source[1]	Yes	Yes	*T112,*T113,*T115	Yes	T112,T113,T115	OUTPUT
tl_spi_host1_o.a_source[5:2]	No	No		No		OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[0]	No	No		No		OUTPUT
tl_spi_host1_o.a_size[1]	Yes	Yes	T106,T112,T113	Yes	T106,T112,T113	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_spi_host1_o.a_opcode[2]	Yes	Yes	T112,T113,T115	Yes	T112,T113,T115	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T106,T112,T113	Yes	T106,T112,T113	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T106,T112,T113	Yes	T106,T112,T113	INPUT
tl_spi_host1_i.d_error	No	No		No		INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T112,T114,T116	Yes	T112,T114,T116	INPUT
tl_spi_host1_i.d_user.rsp_intg[1:0]	Yes	Yes	T112,T113,T115	Yes	T106,T112,T113	INPUT
tl_spi_host1_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_spi_host1_i.d_user.rsp_intg[5:4]	Yes	Yes	T112,T113,T115	Yes	T106,T112,T113	INPUT
tl_spi_host1_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T112,T114,T116	Yes	T112,T114,T116	INPUT
tl_spi_host1_i.d_sink	No	No		No		INPUT
tl_spi_host1_i.d_source[0]	No	No		No		INPUT
tl_spi_host1_i.d_source[1]	Yes	Yes	*T112,*T113,*T115	Yes	T112,T113,T115	INPUT
tl_spi_host1_i.d_source[5:2]	No	No		No		INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[0]	No	No		No		INPUT
tl_spi_host1_i.d_size[1]	Yes	Yes	T112,T113,T115	Yes	T106,T112,T113	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T112,*T113,*T115	Yes	T112,T113,T115	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T106,T112,T113	Yes	T106,T112,T113	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T16,T117,T17	Yes	T16,T117,T17	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T117,T17,T106	Yes	T117,T17,T106	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T16,T117,T17	Yes	T16,T117,T17	OUTPUT
tl_usbdev_o.a_user.instr_type[0]	Yes	Yes	*T16,*T117,*T17	Yes	T16,T117,T17	OUTPUT
tl_usbdev_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_usbdev_o.a_user.instr_type[3]	Yes	Yes	T16,T117,T17	Yes	T16,T117,T17	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T117,T17,T106	Yes	T117,T17,T106	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T16,T117,T17	Yes	T16,T117,T17	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[1:0]	Yes	Yes	*T99,*T117,*T17	Yes	T99,T117,T17	OUTPUT
tl_usbdev_o.a_source[5:2]	No	No		No		OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[0]	No	No		No		OUTPUT
tl_usbdev_o.a_size[1]	Yes	Yes	T16,T117,T17	Yes	T16,T117,T17	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_usbdev_o.a_opcode[2]	Yes	Yes	T16,T117,T17	Yes	T16,T117,T17	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T16,T117,T17	Yes	T16,T117,T17	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T16,T117,T17	Yes	T16,T117,T17	INPUT
tl_usbdev_i.d_error	No	No		No		INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T117,T17,T112	Yes	T16,T117,T17	INPUT
tl_usbdev_i.d_user.rsp_intg[1:0]	Yes	Yes	*T16,T117,T17	Yes	T117,T17,T112	INPUT
tl_usbdev_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_usbdev_i.d_user.rsp_intg[5:4]	Yes	Yes	T17,T112,T18	Yes	T16,T117,T17	INPUT
tl_usbdev_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T16,T117,T17	Yes	T117,T17,T112	INPUT
tl_usbdev_i.d_sink	No	No		No		INPUT
tl_usbdev_i.d_source[1:0]	Yes	Yes	*T99,*T117,*T17	Yes	T99,T117,T17	INPUT
tl_usbdev_i.d_source[5:2]	No	No		No		INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[0]	No	No		No		INPUT
tl_usbdev_i.d_size[1]	Yes	Yes	T17,T112,T18	Yes	T16,T117,T17	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T117,*T17,*T106	Yes	T117,T17,T112	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T16,T117,T17	Yes	T16,T117,T17	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[0]	No	No		No		OUTPUT
tl_flash_ctrl__core_o.a_source[1]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_source[5:2]	No	No		No		OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[0]	No	No		No		OUTPUT
tl_flash_ctrl__core_o.a_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T31,T32,T33	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[3]	No	No		No		INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[5:4]	Yes	Yes	T31,T118,T32	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T31,T118,T32	INPUT
tl_flash_ctrl__core_i.d_sink	No	No		No		INPUT
tl_flash_ctrl__core_i.d_source[0]	No	No		No		INPUT
tl_flash_ctrl__core_i.d_source[1]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_source[5:2]	No	No		No		INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[0]	No	No		No		INPUT
tl_flash_ctrl__core_i.d_size[1]	Yes	Yes	T31,T118,T32	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	No	No		No		OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	No	No		No		OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	No	No		No		OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	No	No		No		OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	No	No		No		OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	No	No		No		OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	No	No		No		OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	No	No		No		OUTPUT
tl_flash_ctrl__prim_o.a_valid	No	No		No		OUTPUT
tl_flash_ctrl__prim_i.a_ready	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_error	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_sink	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	No	No		No		INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_source[1]	No	No		No		OUTPUT
tl_flash_ctrl__mem_o.a_source[4:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_source[5]	No	No		No		OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[0]	No	No		No		OUTPUT
tl_flash_ctrl__mem_o.a_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T31,T32,T33	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[3]	No	No		No		INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[4]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:5]	No	No		No		INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_sink	No	No		No		INPUT
tl_flash_ctrl__mem_i.d_source[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_source[1]	No	No		No		INPUT
tl_flash_ctrl__mem_i.d_source[4:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_source[5]	No	No		No		INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[0]	No	No		No		INPUT
tl_flash_ctrl__mem_i.d_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	No	No		No		INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_hmac_o.d_ready	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T46,T43,T47	Yes	T46,T43,T47	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T46,T43,T47	Yes	T46,T43,T47	OUTPUT
tl_hmac_o.a_user.instr_type[0]	Yes	Yes	*T119,*T46,*T43	Yes	T119,T46,T43	OUTPUT
tl_hmac_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_hmac_o.a_user.instr_type[3]	Yes	Yes	T119,T46,T43	Yes	T119,T46,T43	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T46,T43,T47	Yes	T46,T43,T47	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T119,T46,T43	Yes	T119,T46,T43	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[0]	No	No		No		OUTPUT
tl_hmac_o.a_source[1]	Yes	Yes	*T46,*T43,*T47	Yes	T46,T43,T47	OUTPUT
tl_hmac_o.a_source[5:2]	No	No		No		OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[0]	No	No		No		OUTPUT
tl_hmac_o.a_size[1]	Yes	Yes	T119,T46,T43	Yes	T119,T46,T43	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[0]	Yes	Yes	*T120,*T121,*T122	Yes	T120,T121,T122	OUTPUT
tl_hmac_o.a_opcode[1]	No	No		No		OUTPUT
tl_hmac_o.a_opcode[2]	Yes	Yes	T119,T46,T43	Yes	T119,T46,T43	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T119,T46,T43	Yes	T119,T46,T43	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T119,T46,T43	Yes	T119,T46,T43	INPUT
tl_hmac_i.d_error	No	No		No		INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T119,T46,T43	Yes	T119,T46,T43	INPUT
tl_hmac_i.d_user.rsp_intg[1:0]	Yes	Yes	T119,T46,T43	Yes	T119,T46,T43	INPUT
tl_hmac_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_hmac_i.d_user.rsp_intg[5:4]	Yes	Yes	*T119,T46,T43	Yes	T119,T46,T43	INPUT
tl_hmac_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T46,T43,T47	Yes	T46,T43,T47	INPUT
tl_hmac_i.d_sink	No	No		No		INPUT
tl_hmac_i.d_source[0]	No	No		No		INPUT
tl_hmac_i.d_source[1]	Yes	Yes	*T46,*T43,*T47	Yes	T46,T43,T47	INPUT
tl_hmac_i.d_source[5:2]	No	No		No		INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[0]	No	No		No		INPUT
tl_hmac_i.d_size[1]	Yes	Yes	T119,T46,T43	Yes	T119,T46,T43	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T46,*T43,*T47	Yes	T46,T43,T47	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T119,T46,T43	Yes	T119,T46,T43	INPUT
tl_kmac_o.d_ready	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T123,T124,T125	Yes	T123,T124,T125	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T119,T123,T69	Yes	T119,T123,T69	OUTPUT
tl_kmac_o.a_user.instr_type[0]	Yes	Yes	*T119,*T123,*T69	Yes	T119,T123,T69	OUTPUT
tl_kmac_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_kmac_o.a_user.instr_type[3]	Yes	Yes	T119,T123,T69	Yes	T119,T123,T69	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T123,T124,T125	Yes	T123,T124,T125	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T119,T123,T69	Yes	T119,T123,T69	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[0]	No	No		No		OUTPUT
tl_kmac_o.a_source[1]	Yes	Yes	*T119,*T123,*T69	Yes	T119,T123,T69	OUTPUT
tl_kmac_o.a_source[5:2]	No	No		No		OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[0]	No	No		No		OUTPUT
tl_kmac_o.a_size[1]	Yes	Yes	T119,T123,T69	Yes	T119,T123,T69	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[0]	Yes	Yes	*T123,*T124,*T125	Yes	T123,T124,T125	OUTPUT
tl_kmac_o.a_opcode[1]	No	No		No		OUTPUT
tl_kmac_o.a_opcode[2]	Yes	Yes	T119,T123,T69	Yes	T119,T123,T69	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T119,T123,T69	Yes	T119,T123,T69	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T119,T123,T69	Yes	T119,T123,T69	INPUT
tl_kmac_i.d_error	No	No		No		INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T119,T123,T69	Yes	T119,T123,T69	INPUT
tl_kmac_i.d_user.rsp_intg[1:0]	Yes	Yes	T119,T123,T69	Yes	T119,T123,T69	INPUT
tl_kmac_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_kmac_i.d_user.rsp_intg[5:4]	Yes	Yes	*T119,T123,T124	Yes	T119,T123,T69	INPUT
tl_kmac_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T123,T69,T124	Yes	T123,T124,T125	INPUT
tl_kmac_i.d_sink	No	No		No		INPUT
tl_kmac_i.d_source[0]	No	No		No		INPUT
tl_kmac_i.d_source[1]	Yes	Yes	*T119,*T123,*T69	Yes	T119,T123,T69	INPUT
tl_kmac_i.d_source[5:2]	No	No		No		INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[0]	No	No		No		INPUT
tl_kmac_i.d_size[1]	Yes	Yes	T119,T123,T124	Yes	T119,T123,T69	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T123,*T69,*T124	Yes	T123,T124,T125	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T119,T123,T69	Yes	T119,T123,T69	INPUT
tl_aes_o.d_ready	Yes	Yes	T31,T68,T32	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T68,T126,T127	Yes	T68,T126,T127	OUTPUT
tl_aes_o.a_user.cmd_intg[0]	Yes	Yes	*T68,*T126,*T127	Yes	T68,T126,T127	OUTPUT
tl_aes_o.a_user.cmd_intg[1]	No	No		No		OUTPUT
tl_aes_o.a_user.cmd_intg[6:2]	Yes	Yes	T68,T119,T126	Yes	T68,T119,T126	OUTPUT
tl_aes_o.a_user.instr_type[0]	Yes	Yes	*T68,*T119,*T126	Yes	T68,T119,T126	OUTPUT
tl_aes_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_aes_o.a_user.instr_type[3]	Yes	Yes	T68,T119,T126	Yes	T68,T119,T126	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T68,T126,T127	Yes	T68,T126,T127	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T68,T119,T126	Yes	T68,T119,T126	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[0]	No	No		No		OUTPUT
tl_aes_o.a_source[1]	Yes	Yes	*T68,*T126,*T127	Yes	T68,T126,T127	OUTPUT
tl_aes_o.a_source[5:2]	No	No		No		OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[0]	No	No		No		OUTPUT
tl_aes_o.a_size[1]	Yes	Yes	T68,T119,T126	Yes	T68,T119,T126	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_aes_o.a_opcode[2]	Yes	Yes	T68,T119,T126	Yes	T68,T119,T126	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T68,T119,T126	Yes	T68,T119,T126	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T68,T126,T127	Yes	T68,T126,T127	INPUT
tl_aes_i.d_error	No	No		No		INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T68,T126,T127	Yes	T68,T126,T127	INPUT
tl_aes_i.d_user.rsp_intg[1:0]	Yes	Yes	T68,T126,T127	Yes	T68,T126,T127	INPUT
tl_aes_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_aes_i.d_user.rsp_intg[5:4]	Yes	Yes	T128,*T129,*T130	Yes	T68,T126,T127	INPUT
tl_aes_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T68,T126,T131	Yes	T68,T126,T127	INPUT
tl_aes_i.d_sink	No	No		No		INPUT
tl_aes_i.d_source[0]	No	No		No		INPUT
tl_aes_i.d_source[1]	Yes	Yes	*T68,*T126,*T127	Yes	T68,T126,T127	INPUT
tl_aes_i.d_source[5:2]	No	No		No		INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[0]	No	No		No		INPUT
tl_aes_i.d_size[1]	Yes	Yes	T128,T129,T130	Yes	T68,T126,T127	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T68,*T126,*T127	Yes	T68,T126,T127	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T68,T126,T127	Yes	T68,T126,T127	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_entropy_src_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[0]	No	No		No		OUTPUT
tl_entropy_src_o.a_source[1]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_source[5:2]	No	No		No		OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[0]	No	No		No		OUTPUT
tl_entropy_src_o.a_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_entropy_src_o.a_opcode[2]	Yes	Yes	T76,T74,T66	Yes	T76,T74,T66	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_error	No	No		No		INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T76,T74,T66	Yes	T76,T74,T66	INPUT
tl_entropy_src_i.d_user.rsp_intg[1:0]	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_entropy_src_i.d_user.rsp_intg[5:4]	Yes	Yes	*T31,*T32,*T33	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_sink	No	No		No		INPUT
tl_entropy_src_i.d_source[0]	No	No		No		INPUT
tl_entropy_src_i.d_source[1]	Yes	Yes	*T31,*T32,*T33	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_source[5:2]	No	No		No		INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[0]	No	No		No		INPUT
tl_entropy_src_i.d_size[1]	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T76,*T74,*T66	Yes	T76,T74,T66	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_csrng_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T76,T74,T66	Yes	T76,T74,T66	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[0]	No	No		No		OUTPUT
tl_csrng_o.a_source[1]	Yes	Yes	*T76,*T74,*T66	Yes	T76,T74,T66	OUTPUT
tl_csrng_o.a_source[5:2]	No	No		No		OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[0]	No	No		No		OUTPUT
tl_csrng_o.a_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_csrng_o.a_opcode[2]	Yes	Yes	T76,T74,T66	Yes	T76,T74,T66	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_error	No	No		No		INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T76,T74,T66	Yes	T76,T74,T66	INPUT
tl_csrng_i.d_user.rsp_intg[1:0]	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_csrng_i.d_user.rsp_intg[5:4]	Yes	Yes	*T31,*T32,*T33	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_sink	No	No		No		INPUT
tl_csrng_i.d_source[0]	No	No		No		INPUT
tl_csrng_i.d_source[1]	Yes	Yes	*T76,*T74,*T66	Yes	T76,T74,T66	INPUT
tl_csrng_i.d_source[5:2]	No	No		No		INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[0]	No	No		No		INPUT
tl_csrng_i.d_size[1]	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T76,*T74,*T66	Yes	T76,T74,T66	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T76,T74,T66	Yes	T76,T74,T66	OUTPUT
tl_edn0_o.a_user.cmd_intg[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.cmd_intg[1]	No	No		No		OUTPUT
tl_edn0_o.a_user.cmd_intg[6:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_edn0_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T76,T74,T66	Yes	T76,T74,T66	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[0]	No	No		No		OUTPUT
tl_edn0_o.a_source[1]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_source[5:2]	No	No		No		OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[0]	No	No		No		OUTPUT
tl_edn0_o.a_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_edn0_o.a_opcode[2]	Yes	Yes	T76,T74,T66	Yes	T76,T74,T66	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_error	No	No		No		INPUT
tl_edn0_i.d_user.data_intg[0]	Yes	Yes	*T76,*T74,*T66	Yes	T76,T74,T66	INPUT
tl_edn0_i.d_user.data_intg[1]	No	No		No		INPUT
tl_edn0_i.d_user.data_intg[6:2]	Yes	Yes	T76,T74,T66	Yes	T76,T74,T66	INPUT
tl_edn0_i.d_user.rsp_intg[1:0]	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_edn0_i.d_user.rsp_intg[5:4]	Yes	Yes	*T31,*T32,*T33	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_sink	No	No		No		INPUT
tl_edn0_i.d_source[0]	No	No		No		INPUT
tl_edn0_i.d_source[1]	Yes	Yes	*T31,*T32,*T33	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_source[5:2]	No	No		No		INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[0]	No	No		No		INPUT
tl_edn0_i.d_size[1]	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T76,*T74,*T66	Yes	T76,T74,T66	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_o.d_ready	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T76,T74,T66	Yes	T76,T74,T66	OUTPUT
tl_edn1_o.a_user.cmd_intg[0]	Yes	Yes	*T76,*T74,*T66	Yes	T76,T74,T66	OUTPUT
tl_edn1_o.a_user.cmd_intg[1]	No	No		No		OUTPUT
tl_edn1_o.a_user.cmd_intg[6:2]	Yes	Yes	T76,T74,T66	Yes	T76,T74,T66	OUTPUT
tl_edn1_o.a_user.instr_type[0]	Yes	Yes	*T76,*T74,*T66	Yes	T76,T74,T66	OUTPUT
tl_edn1_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_edn1_o.a_user.instr_type[3]	Yes	Yes	T76,T74,T66	Yes	T76,T74,T66	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T76,T74,T66	Yes	T76,T74,T66	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T76,T74,T66	Yes	T76,T74,T66	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[0]	No	No		No		OUTPUT
tl_edn1_o.a_source[1]	Yes	Yes	*T76,*T74,*T66	Yes	T76,T74,T66	OUTPUT
tl_edn1_o.a_source[5:2]	No	No		No		OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[0]	No	No		No		OUTPUT
tl_edn1_o.a_size[1]	Yes	Yes	T76,T74,T66	Yes	T76,T74,T66	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_edn1_o.a_opcode[2]	Yes	Yes	T76,T74,T66	Yes	T76,T74,T66	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T76,T74,T66	Yes	T76,T74,T66	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T76,T74,T66	Yes	T76,T74,T66	INPUT
tl_edn1_i.d_error	No	No		No		INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T76,T74,T66	Yes	T76,T74,T66	INPUT
tl_edn1_i.d_user.rsp_intg[1:0]	Yes	Yes	T76,T74,T66	Yes	T76,T74,T66	INPUT
tl_edn1_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_edn1_i.d_user.rsp_intg[5:4]	Yes	Yes	T66,T132,*T133	Yes	T76,T74,T66	INPUT
tl_edn1_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T76,T74,T66	Yes	T76,T74,T66	INPUT
tl_edn1_i.d_sink	No	No		No		INPUT
tl_edn1_i.d_source[0]	No	No		No		INPUT
tl_edn1_i.d_source[1]	Yes	Yes	*T76,*T74,*T66	Yes	T76,T74,T66	INPUT
tl_edn1_i.d_source[5:2]	No	No		No		INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[0]	No	No		No		INPUT
tl_edn1_i.d_size[1]	Yes	Yes	T66,T132,T133	Yes	T76,T74,T66	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T76,*T74,*T66	Yes	T76,T74,T66	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T76,T74,T66	Yes	T76,T74,T66	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T1,T2,T31	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	OUTPUT
tl_rv_plic_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T31	Yes	T1,T2,T31	OUTPUT
tl_rv_plic_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_rv_plic_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[0]	No	No		No		OUTPUT
tl_rv_plic_o.a_source[1]	Yes	Yes	*T1,*T2,*T31	Yes	T1,T2,T31	OUTPUT
tl_rv_plic_o.a_source[5:2]	No	No		No		OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[0]	No	No		No		OUTPUT
tl_rv_plic_o.a_size[1]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_rv_plic_o.a_opcode[2]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	INPUT
tl_rv_plic_i.d_error	No	No		No		INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T31,T118,T33	Yes	T31,T118,T33	INPUT
tl_rv_plic_i.d_user.rsp_intg[1:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	INPUT
tl_rv_plic_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_rv_plic_i.d_user.rsp_intg[5:4]	Yes	Yes	T31,T33,T134	Yes	T1,T2,T31	INPUT
tl_rv_plic_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	INPUT
tl_rv_plic_i.d_sink	No	No		No		INPUT
tl_rv_plic_i.d_source[0]	No	No		No		INPUT
tl_rv_plic_i.d_source[1]	Yes	Yes	*T1,*T2,*T31	Yes	T1,T2,T31	INPUT
tl_rv_plic_i.d_source[5:2]	No	No		No		INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[0]	No	No		No		INPUT
tl_rv_plic_i.d_size[1]	Yes	Yes	T31,T33,T134	Yes	T1,T2,T31	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T31	Yes	T1,T2,T31	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	INPUT
tl_otbn_o.d_ready	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T76,T127,T135	Yes	T76,T127,T135	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T119,T76,T127	Yes	T119,T76,T127	OUTPUT
tl_otbn_o.a_user.instr_type[0]	Yes	Yes	*T119,*T76,*T127	Yes	T119,T76,T127	OUTPUT
tl_otbn_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_otbn_o.a_user.instr_type[3]	Yes	Yes	T119,T76,T127	Yes	T119,T76,T127	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T76,T127,T135	Yes	T76,T127,T135	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T119,T76,T127	Yes	T119,T76,T127	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[1:0]	Yes	Yes	*T60,*T136,*T137	Yes	T60,T136,T137	OUTPUT
tl_otbn_o.a_source[5:2]	No	No		No		OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[0]	No	No		No		OUTPUT
tl_otbn_o.a_size[1]	Yes	Yes	T119,T76,T127	Yes	T119,T76,T127	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_otbn_o.a_opcode[2]	Yes	Yes	T119,T76,T127	Yes	T119,T76,T127	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T119,T76,T127	Yes	T119,T76,T127	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T119,T76,T127	Yes	T119,T76,T127	INPUT
tl_otbn_i.d_error	No	No		No		INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T76,T127,T135	Yes	T76,T127,T135	INPUT
tl_otbn_i.d_user.rsp_intg[1:0]	Yes	Yes	T119,T76,T127	Yes	T119,T76,T127	INPUT
tl_otbn_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_otbn_i.d_user.rsp_intg[5:4]	Yes	Yes	*T119,T76,T127	Yes	T119,T76,T127	INPUT
tl_otbn_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T119,T76,T127	Yes	T119,T76,T127	INPUT
tl_otbn_i.d_sink	No	No		No		INPUT
tl_otbn_i.d_source[1:0]	Yes	Yes	*T60,*T136,*T137	Yes	T60,T136,T137	INPUT
tl_otbn_i.d_source[5:2]	No	No		No		INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[0]	No	No		No		INPUT
tl_otbn_i.d_size[1]	Yes	Yes	T119,T76,T127	Yes	T119,T76,T127	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T76,*T127,*T135	Yes	T76,T127,T135	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T119,T76,T127	Yes	T119,T76,T127	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T32,T69,T127	Yes	T32,T69,T127	OUTPUT
tl_keymgr_o.a_user.cmd_intg[0]	Yes	Yes	*T32,*T69,*T127	Yes	T32,T69,T127	OUTPUT
tl_keymgr_o.a_user.cmd_intg[1]	No	No		No		OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:2]	Yes	Yes	T32,T69,T127	Yes	T32,T69,T127	OUTPUT
tl_keymgr_o.a_user.instr_type[0]	Yes	Yes	*T32,*T69,*T127	Yes	T32,T69,T127	OUTPUT
tl_keymgr_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_keymgr_o.a_user.instr_type[3]	Yes	Yes	T32,T69,T127	Yes	T32,T69,T127	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T32,T69,T127	Yes	T32,T69,T127	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T32,T69,T127	Yes	T32,T69,T127	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[0]	No	No		No		OUTPUT
tl_keymgr_o.a_source[1]	Yes	Yes	*T32,*T69,*T127	Yes	T32,T69,T127	OUTPUT
tl_keymgr_o.a_source[5:2]	No	No		No		OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[0]	No	No		No		OUTPUT
tl_keymgr_o.a_size[1]	Yes	Yes	T32,T69,T127	Yes	T32,T69,T127	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_keymgr_o.a_opcode[2]	Yes	Yes	T32,T69,T127	Yes	T32,T69,T127	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T32,T69,T127	Yes	T32,T69,T127	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T32,T69,T127	Yes	T32,T69,T127	INPUT
tl_keymgr_i.d_error	No	No		No		INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T32,T69,T127	Yes	T32,T69,T127	INPUT
tl_keymgr_i.d_user.rsp_intg[1:0]	Yes	Yes	T32,T69,T127	Yes	T32,T69,T127	INPUT
tl_keymgr_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_keymgr_i.d_user.rsp_intg[5:4]	Yes	Yes	T32,T138,T139	Yes	T32,T69,T127	INPUT
tl_keymgr_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T32,T69,T127	Yes	T32,T69,T127	INPUT
tl_keymgr_i.d_sink	No	No		No		INPUT
tl_keymgr_i.d_source[0]	No	No		No		INPUT
tl_keymgr_i.d_source[1]	Yes	Yes	*T32,*T69,*T127	Yes	T32,T69,T127	INPUT
tl_keymgr_i.d_source[5:2]	No	No		No		INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[0]	No	No		No		INPUT
tl_keymgr_i.d_size[1]	Yes	Yes	T32,T138,T139	Yes	T32,T69,T127	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T32,*T69,*T127	Yes	T32,T69,T127	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T32,T69,T127	Yes	T32,T69,T127	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[1]	No	No		No		OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[1:0]	Yes	Yes	*T49,*T52,*T1	Yes	T49,T52,T1	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:2]	No	No		No		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[0]	No	No		No		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T49,T52	Yes	T49,T52	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[2:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[3]	No	No		No		INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[5:4]	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	INPUT
tl_rv_core_ibex__cfg_i.d_sink	No	No		No		INPUT
tl_rv_core_ibex__cfg_i.d_source[1:0]	Yes	Yes	*T49,*T52,*T1	Yes	T49,T52,T1	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:2]	No	No		No		INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[0]	No	No		No		INPUT
tl_rv_core_ibex__cfg_i.d_size[1]	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T46,T43,T47	Yes	T46,T43,T47	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[0]	Yes	Yes	*T46,*T140,*T43	Yes	T46,T140,T43	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[1]	No	No		No		OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:2]	Yes	Yes	T140,T141,T142	Yes	T140,T141,T142	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[0]	Yes	Yes	*T46,*T140,*T43	Yes	T46,T140,T43	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3]	Yes	Yes	T46,T140,T43	Yes	T46,T140,T43	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[3:0]	Yes	Yes	*T46,*T43,*T47	Yes	T46,T43,T47	OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:4]	No	No		No		OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T46,T140,T43	Yes	T46,T140,T43	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[0]	No	No		No		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[1]	Yes	Yes	*T142,*T143,*T144	Yes	T142,T143,T144	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:2]	No	No		No		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[0]	No	No		No		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1]	Yes	Yes	T46,T140,T43	Yes	T46,T140,T43	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2]	Yes	Yes	T140,T141,T142	Yes	T140,T141,T142	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T46,T140,T43	Yes	T46,T140,T43	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T46,T140,T43	Yes	T46,T140,T43	INPUT
tl_sram_ctrl_main__regs_i.d_error	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[5:0]	Yes	Yes	*T142,*T143,*T145	Yes	T142,T143,T145	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6]	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[1:0]	Yes	Yes	T43,T44,T45	Yes	T46,T43,T47	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[5:4]	Yes	Yes	*T43,*T44,*T45	Yes	T46,T140,T43	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T43,T44,T45	Yes	T46,T43,T47	INPUT
tl_sram_ctrl_main__regs_i.d_sink	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_source[0]	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_source[1]	Yes	Yes	*T142,*T143,*T144	Yes	T142,T143,T144	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:2]	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[0]	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_size[1]	Yes	Yes	T43,T44,T45	Yes	T46,T140,T43	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T142,*T143,*T144	Yes	T140,T141,T142	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T46,T140,T43	Yes	T46,T140,T43	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[4:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5]	No	No		No		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[0]	No	No		No		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[1]	No	No		No		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T31,T32,T33	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[3]	No	No		No		INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[5:4]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_sink	No	No		No		INPUT
tl_sram_ctrl_main__ram_i.d_source[4:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_source[5]	No	No		No		INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[0]	No	No		No		INPUT
tl_sram_ctrl_main__ram_i.d_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range