Unified Coverage Report :: Module :: xbar_peri

Module : xbar_peri

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.02			88.02

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_peri	88.02			88.02

---

Module Instance : tb.dut.top_earlgrey.u_xbar_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.02			88.02

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.02			88.02

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.57	92.83		90.88			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_peri

	Total	Covered	Percent
Totals	562	365	64.95
Total Bits	7060	6214	88.02
Total Bits 0->1	3530	3108	88.05
Total Bits 1->0	3530	3106	87.99

Ports	562	365	64.95
Port Bits	7060	6214	88.02
Port Bits 0->1	3530	3108	88.05
Port Bits 1->0	3530	3106	87.99

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_peri_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_peri_ni	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
tl_main_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_main_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_source[5:0]	Yes	Yes	*T4,*T49,*T59	Yes	T4,T49,T59	INPUT
tl_main_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
tl_main_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_opcode[0]	Yes	Yes	*T49,*T60,*T52	Yes	T49,T60,T52	INPUT
tl_main_i.a_opcode[1]	No	No		No		INPUT
tl_main_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_error	Yes	Yes	T101,T111,T107	Yes	T101,T111,T107	OUTPUT
tl_main_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_main_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_sink	No	No		No		OUTPUT
tl_main_o.d_source[5:0]	Yes	Yes	*T4,*T49,*T59	Yes	T4,T49,T59	OUTPUT
tl_main_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
tl_main_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.data_intg[6:0]	Yes	Yes	T32,T117,T250	Yes	T32,T117,T250	OUTPUT
tl_uart0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_uart0_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_data[31:0]	Yes	Yes	T32,T117,T250	Yes	T32,T117,T250	OUTPUT
tl_uart0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_source[5:0]	Yes	Yes	*T4,*T49,*T59	Yes	T4,T49,T59	OUTPUT
tl_uart0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
tl_uart0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_opcode[0]	Yes	Yes	*T49,*T60,*T52	Yes	T49,T60,T52	OUTPUT
tl_uart0_o.a_opcode[1]	No	No		No		OUTPUT
tl_uart0_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_valid	Yes	Yes	T32,T117,T250	Yes	T32,T117,T250	OUTPUT
tl_uart0_i.a_ready	Yes	Yes	T117,T250,T46	Yes	T117,T250,T46	INPUT
tl_uart0_i.d_error	No	No		No		INPUT
tl_uart0_i.d_user.data_intg[6:0]	Yes	Yes	T117,T250,T43	Yes	T117,T250,T43	INPUT
tl_uart0_i.d_user.rsp_intg[1:0]	Yes	Yes	T117,T250,T43	Yes	T117,T250,T46	INPUT
tl_uart0_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_uart0_i.d_user.rsp_intg[5:4]	Yes	Yes	T43,T44,T45	Yes	T117,T250,T46	INPUT
tl_uart0_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_uart0_i.d_data[31:0]	Yes	Yes	T117,T250,T43	Yes	T117,T250,T46	INPUT
tl_uart0_i.d_sink	No	No		No		INPUT
tl_uart0_i.d_source[0]	No	No		No		INPUT
tl_uart0_i.d_source[1]	Yes	Yes	*T117,*T250,*T46	Yes	T117,T250,T46	INPUT
tl_uart0_i.d_source[5:2]	No	No		No		INPUT
tl_uart0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_size[0]	No	No		No		INPUT
tl_uart0_i.d_size[1]	Yes	Yes	T43,T44,T45	Yes	T117,T250,T46	INPUT
tl_uart0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_opcode[0]	Yes	Yes	*T117,*T250,*T43	Yes	T117,T250,T43	INPUT
tl_uart0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_valid	Yes	Yes	T117,T250,T46	Yes	T117,T250,T46	INPUT
tl_uart1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.data_intg[6:0]	Yes	Yes	T117,T213,T263	Yes	T117,T213,T263	OUTPUT
tl_uart1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_uart1_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_data[31:0]	Yes	Yes	T117,T213,T263	Yes	T117,T213,T263	OUTPUT
tl_uart1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_source[5:0]	Yes	Yes	*T4,*T49,*T59	Yes	T4,T49,T59	OUTPUT
tl_uart1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
tl_uart1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_opcode[0]	Yes	Yes	*T49,*T60,*T52	Yes	T49,T60,T52	OUTPUT
tl_uart1_o.a_opcode[1]	No	No		No		OUTPUT
tl_uart1_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_valid	Yes	Yes	T117,T106,T213	Yes	T117,T106,T213	OUTPUT
tl_uart1_i.a_ready	Yes	Yes	T117,T106,T213	Yes	T117,T106,T213	INPUT
tl_uart1_i.d_error	No	No		No		INPUT
tl_uart1_i.d_user.data_intg[6:0]	Yes	Yes	T117,T213,T263	Yes	T117,T213,T263	INPUT
tl_uart1_i.d_user.rsp_intg[1:0]	Yes	Yes	T117,T213,T263	Yes	T117,T106,T213	INPUT
tl_uart1_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_uart1_i.d_user.rsp_intg[5:4]	Yes	Yes	*T217,*T99,*T310	Yes	T117,T106,T213	INPUT
tl_uart1_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_uart1_i.d_data[31:0]	Yes	Yes	T117,T213,T263	Yes	T117,T106,T213	INPUT
tl_uart1_i.d_sink	No	No		No		INPUT
tl_uart1_i.d_source[1:0]	Yes	Yes	*T99,*T117,*T213	Yes	T99,T117,T213	INPUT
tl_uart1_i.d_source[5:2]	No	No		No		INPUT
tl_uart1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_size[0]	No	No		No		INPUT
tl_uart1_i.d_size[1]	Yes	Yes	T217,T99,T310	Yes	T117,T106,T213	INPUT
tl_uart1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_opcode[0]	Yes	Yes	*T117,*T213,*T263	Yes	T117,T213,T263	INPUT
tl_uart1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_valid	Yes	Yes	T117,T106,T213	Yes	T117,T106,T213	INPUT
tl_uart2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.data_intg[6:0]	Yes	Yes	T117,T213,T311	Yes	T117,T213,T311	OUTPUT
tl_uart2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_uart2_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_data[31:0]	Yes	Yes	T117,T213,T311	Yes	T117,T213,T311	OUTPUT
tl_uart2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_source[5:0]	Yes	Yes	*T4,*T49,*T59	Yes	T4,T49,T59	OUTPUT
tl_uart2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
tl_uart2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_opcode[0]	Yes	Yes	*T49,*T60,*T52	Yes	T49,T60,T52	OUTPUT
tl_uart2_o.a_opcode[1]	No	No		No		OUTPUT
tl_uart2_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_valid	Yes	Yes	T117,T106,T213	Yes	T117,T106,T213	OUTPUT
tl_uart2_i.a_ready	Yes	Yes	T117,T106,T213	Yes	T117,T106,T213	INPUT
tl_uart2_i.d_error	No	No		No		INPUT
tl_uart2_i.d_user.data_intg[6:0]	Yes	Yes	T117,T213,T311	Yes	T117,T213,T311	INPUT
tl_uart2_i.d_user.rsp_intg[1:0]	Yes	Yes	T117,T213,T311	Yes	T117,T106,T213	INPUT
tl_uart2_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_uart2_i.d_user.rsp_intg[5:4]	Yes	Yes	*T217,T99,*T310	Yes	T117,T106,T213	INPUT
tl_uart2_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_uart2_i.d_data[31:0]	Yes	Yes	T117,T213,T311	Yes	T117,T106,T213	INPUT
tl_uart2_i.d_sink	No	No		No		INPUT
tl_uart2_i.d_source[1:0]	Yes	Yes	*T99,*T117,*T213	Yes	T99,T117,T213	INPUT
tl_uart2_i.d_source[5:2]	No	No		No		INPUT
tl_uart2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_size[0]	No	No		No		INPUT
tl_uart2_i.d_size[1]	Yes	Yes	T217,T99,T310	Yes	T117,T106,T213	INPUT
tl_uart2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_opcode[0]	Yes	Yes	*T117,*T213,*T311	Yes	T117,T213,T311	INPUT
tl_uart2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_valid	Yes	Yes	T117,T106,T213	Yes	T117,T106,T213	INPUT
tl_uart3_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.data_intg[6:0]	Yes	Yes	T117,T15,T252	Yes	T117,T15,T252	OUTPUT
tl_uart3_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_uart3_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_data[31:0]	Yes	Yes	T117,T15,T252	Yes	T117,T15,T252	OUTPUT
tl_uart3_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_source[5:0]	Yes	Yes	*T4,*T49,*T59	Yes	T4,T49,T59	OUTPUT
tl_uart3_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
tl_uart3_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_opcode[0]	Yes	Yes	*T49,*T60,*T52	Yes	T49,T60,T52	OUTPUT
tl_uart3_o.a_opcode[1]	No	No		No		OUTPUT
tl_uart3_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_valid	Yes	Yes	T117,T15,T252	Yes	T117,T15,T252	OUTPUT
tl_uart3_i.a_ready	Yes	Yes	T117,T15,T252	Yes	T117,T15,T252	INPUT
tl_uart3_i.d_error	No	No		No		INPUT
tl_uart3_i.d_user.data_intg[6:0]	Yes	Yes	T117,T15,T252	Yes	T117,T15,T252	INPUT
tl_uart3_i.d_user.rsp_intg[1:0]	Yes	Yes	T117,T15,T252	Yes	T117,T15,T252	INPUT
tl_uart3_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_uart3_i.d_user.rsp_intg[5:4]	Yes	Yes	*T217,*T99,*T310	Yes	T117,T15,T252	INPUT
tl_uart3_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_uart3_i.d_data[31:0]	Yes	Yes	T117,T15,T252	Yes	T117,T15,T252	INPUT
tl_uart3_i.d_sink	No	No		No		INPUT
tl_uart3_i.d_source[1:0]	Yes	Yes	*T99,*T117,*T15	Yes	T99,T117,T15	INPUT
tl_uart3_i.d_source[5:2]	No	No		No		INPUT
tl_uart3_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_size[0]	No	No		No		INPUT
tl_uart3_i.d_size[1]	Yes	Yes	T217,T99,T310	Yes	T117,T15,T252	INPUT
tl_uart3_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_opcode[0]	Yes	Yes	*T117,*T15,*T252	Yes	T117,T15,T252	INPUT
tl_uart3_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_valid	Yes	Yes	T117,T15,T252	Yes	T117,T15,T252	INPUT
tl_i2c0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.data_intg[6:0]	Yes	Yes	T215,T112,T208	Yes	T215,T112,T208	OUTPUT
tl_i2c0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_i2c0_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_data[31:0]	Yes	Yes	T215,T112,T208	Yes	T215,T112,T208	OUTPUT
tl_i2c0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_source[5:0]	Yes	Yes	*T4,*T49,*T59	Yes	T4,T49,T59	OUTPUT
tl_i2c0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
tl_i2c0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_opcode[0]	Yes	Yes	*T49,*T60,*T52	Yes	T49,T60,T52	OUTPUT
tl_i2c0_o.a_opcode[1]	No	No		No		OUTPUT
tl_i2c0_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_valid	Yes	Yes	T215,T106,T112	Yes	T215,T106,T112	OUTPUT
tl_i2c0_i.a_ready	Yes	Yes	T215,T106,T112	Yes	T215,T106,T112	INPUT
tl_i2c0_i.d_error	No	No		No		INPUT
tl_i2c0_i.d_user.data_intg[6:0]	Yes	Yes	T215,T208,T209	Yes	T215,T208,T209	INPUT
tl_i2c0_i.d_user.rsp_intg[1:0]	Yes	Yes	T215,T112,T208	Yes	T215,T106,T112	INPUT
tl_i2c0_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_i2c0_i.d_user.rsp_intg[5:4]	Yes	Yes	T112,T114,*T217	Yes	T215,T106,T112	INPUT
tl_i2c0_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_i2c0_i.d_data[31:0]	Yes	Yes	T215,T112,T208	Yes	T215,T106,T112	INPUT
tl_i2c0_i.d_sink	No	No		No		INPUT
tl_i2c0_i.d_source[0]	No	No		No		INPUT
tl_i2c0_i.d_source[1]	Yes	Yes	*T215,*T112,*T208	Yes	T215,T106,T112	INPUT
tl_i2c0_i.d_source[5:2]	No	No		No		INPUT
tl_i2c0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_size[0]	No	No		No		INPUT
tl_i2c0_i.d_size[1]	Yes	Yes	T112,T114,T217	Yes	T215,T106,T112	INPUT
tl_i2c0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_opcode[0]	Yes	Yes	*T215,*T112,*T208	Yes	T215,T112,T208	INPUT
tl_i2c0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_valid	Yes	Yes	T215,T106,T112	Yes	T215,T106,T112	INPUT
tl_i2c1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.data_intg[6:0]	Yes	Yes	T112,T219,T208	Yes	T112,T219,T208	OUTPUT
tl_i2c1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_i2c1_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_data[31:0]	Yes	Yes	T112,T219,T208	Yes	T112,T219,T208	OUTPUT
tl_i2c1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_source[5:0]	Yes	Yes	*T4,*T49,*T59	Yes	T4,T49,T59	OUTPUT
tl_i2c1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
tl_i2c1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_opcode[0]	Yes	Yes	*T49,*T60,*T52	Yes	T49,T60,T52	OUTPUT
tl_i2c1_o.a_opcode[1]	No	No		No		OUTPUT
tl_i2c1_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_valid	Yes	Yes	T106,T112,T219	Yes	T106,T112,T219	OUTPUT
tl_i2c1_i.a_ready	Yes	Yes	T106,T112,T219	Yes	T106,T112,T219	INPUT
tl_i2c1_i.d_error	No	No		No		INPUT
tl_i2c1_i.d_user.data_intg[6:0]	Yes	Yes	T112,T219,T208	Yes	T112,T219,T208	INPUT
tl_i2c1_i.d_user.rsp_intg[1:0]	Yes	Yes	T112,T219,T208	Yes	T106,T112,T219	INPUT
tl_i2c1_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_i2c1_i.d_user.rsp_intg[5:4]	Yes	Yes	T112,T114,*T217	Yes	T106,T112,T219	INPUT
tl_i2c1_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_i2c1_i.d_data[31:0]	Yes	Yes	T112,T219,T208	Yes	T106,T112,T219	INPUT
tl_i2c1_i.d_sink	No	No		No		INPUT
tl_i2c1_i.d_source[0]	No	No		No		INPUT
tl_i2c1_i.d_source[1]	Yes	Yes	*T112,*T219,*T208	Yes	T106,T112,T219	INPUT
tl_i2c1_i.d_source[5:2]	No	No		No		INPUT
tl_i2c1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_size[0]	No	No		No		INPUT
tl_i2c1_i.d_size[1]	Yes	Yes	T112,T114,T217	Yes	T106,T112,T219	INPUT
tl_i2c1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_opcode[0]	Yes	Yes	*T112,*T219,*T208	Yes	T112,T219,T208	INPUT
tl_i2c1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_valid	Yes	Yes	T106,T112,T219	Yes	T106,T112,T219	INPUT
tl_i2c2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.data_intg[6:0]	Yes	Yes	T112,T216,T208	Yes	T112,T216,T208	OUTPUT
tl_i2c2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_i2c2_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_data[31:0]	Yes	Yes	T112,T216,T208	Yes	T112,T216,T208	OUTPUT
tl_i2c2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_source[5:0]	Yes	Yes	*T4,*T49,*T59	Yes	T4,T49,T59	OUTPUT
tl_i2c2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
tl_i2c2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_opcode[0]	Yes	Yes	*T49,*T60,*T52	Yes	T49,T60,T52	OUTPUT
tl_i2c2_o.a_opcode[1]	No	No		No		OUTPUT
tl_i2c2_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_valid	Yes	Yes	T106,T112,T216	Yes	T106,T112,T216	OUTPUT
tl_i2c2_i.a_ready	Yes	Yes	T106,T112,T216	Yes	T106,T112,T216	INPUT
tl_i2c2_i.d_error	No	No		No		INPUT
tl_i2c2_i.d_user.data_intg[6:0]	Yes	Yes	T216,T208,T209	Yes	T216,T208,T209	INPUT
tl_i2c2_i.d_user.rsp_intg[1:0]	Yes	Yes	T112,T216,T208	Yes	T106,T112,T216	INPUT
tl_i2c2_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_i2c2_i.d_user.rsp_intg[5:4]	Yes	Yes	T112,T114,*T217	Yes	T106,T112,T216	INPUT
tl_i2c2_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_i2c2_i.d_data[31:0]	Yes	Yes	T112,T216,T208	Yes	T106,T112,T216	INPUT
tl_i2c2_i.d_sink	No	No		No		INPUT
tl_i2c2_i.d_source[0]	No	No		No		INPUT
tl_i2c2_i.d_source[1]	Yes	Yes	*T112,*T216,*T208	Yes	T106,T112,T216	INPUT
tl_i2c2_i.d_source[5:2]	No	No		No		INPUT
tl_i2c2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_size[0]	No	No		No		INPUT
tl_i2c2_i.d_size[1]	Yes	Yes	T112,T114,T217	Yes	T106,T112,T216	INPUT
tl_i2c2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_opcode[0]	Yes	Yes	*T112,*T216,*T208	Yes	T112,T216,T208	INPUT
tl_i2c2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_valid	Yes	Yes	T106,T112,T216	Yes	T106,T112,T216	INPUT
tl_pattgen_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.data_intg[6:0]	Yes	Yes	T253,T312,T116	Yes	T253,T312,T116	OUTPUT
tl_pattgen_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_pattgen_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_data[31:0]	Yes	Yes	T253,T312,T116	Yes	T253,T312,T116	OUTPUT
tl_pattgen_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_source[5:0]	Yes	Yes	*T4,*T49,*T59	Yes	T4,T49,T59	OUTPUT
tl_pattgen_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
tl_pattgen_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_opcode[0]	Yes	Yes	*T49,*T60,*T52	Yes	T49,T60,T52	OUTPUT
tl_pattgen_o.a_opcode[1]	No	No		No		OUTPUT
tl_pattgen_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_valid	Yes	Yes	T253,T106,T312	Yes	T253,T106,T312	OUTPUT
tl_pattgen_i.a_ready	Yes	Yes	T253,T106,T312	Yes	T253,T106,T312	INPUT
tl_pattgen_i.d_error	No	No		No		INPUT
tl_pattgen_i.d_user.data_intg[6:0]	Yes	Yes	T253,T312,T116	Yes	T253,T312,T116	INPUT
tl_pattgen_i.d_user.rsp_intg[1:0]	Yes	Yes	T253,T312,T116	Yes	T253,T106,T312	INPUT
tl_pattgen_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_pattgen_i.d_user.rsp_intg[4]	No	No		Yes	T253,T106,T312	INPUT
tl_pattgen_i.d_user.rsp_intg[5]	Yes	Yes	*T253,*T312,*T116	Yes	T253,T312,T116	INPUT
tl_pattgen_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_pattgen_i.d_data[31:0]	Yes	Yes	T253,T312,T116	Yes	T253,T106,T312	INPUT
tl_pattgen_i.d_sink	No	No		No		INPUT
tl_pattgen_i.d_source[0]	No	No		No		INPUT
tl_pattgen_i.d_source[1]	Yes	Yes	*T253,*T312,*T116	Yes	T253,T312,T116	INPUT
tl_pattgen_i.d_source[5:2]	No	No		No		INPUT
tl_pattgen_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_size[0]	No	No		No		INPUT
tl_pattgen_i.d_size[1]	No	No		Yes	T253,T106,T312	INPUT
tl_pattgen_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_opcode[0]	Yes	Yes	*T253,*T312,*T116	Yes	T253,T312,T116	INPUT
tl_pattgen_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_valid	Yes	Yes	T253,T106,T312	Yes	T253,T106,T312	INPUT
tl_pwm_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.data_intg[6:0]	Yes	Yes	T65,T49,T72	Yes	T65,T49,T72	OUTPUT
tl_pwm_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_pwm_aon_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_data[31:0]	Yes	Yes	T65,T49,T72	Yes	T65,T49,T72	OUTPUT
tl_pwm_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_source[5:0]	Yes	Yes	*T4,*T49,*T59	Yes	T4,T49,T59	OUTPUT
tl_pwm_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
tl_pwm_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_opcode[0]	Yes	Yes	*T49,*T60,*T52	Yes	T49,T60,T52	OUTPUT
tl_pwm_aon_o.a_opcode[1]	No	No		No		OUTPUT
tl_pwm_aon_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_valid	Yes	Yes	T65,T49,T106	Yes	T65,T49,T106	OUTPUT
tl_pwm_aon_i.a_ready	Yes	Yes	T65,T49,T106	Yes	T65,T49,T106	INPUT
tl_pwm_aon_i.d_error	No	No		No		INPUT
tl_pwm_aon_i.d_user.data_intg[6:0]	Yes	Yes	T65,T49,T72	Yes	T65,T49,T72	INPUT
tl_pwm_aon_i.d_user.rsp_intg[1:0]	Yes	Yes	T65,T49,T72	Yes	T65,T49,T106	INPUT
tl_pwm_aon_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_pwm_aon_i.d_user.rsp_intg[5:4]	Yes	Yes	T49,T52,*T65	Yes	T65,T49,T106	INPUT
tl_pwm_aon_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_pwm_aon_i.d_data[31:0]	Yes	Yes	T65,T49,T72	Yes	T65,T49,T106	INPUT
tl_pwm_aon_i.d_sink	No	No		No		INPUT
tl_pwm_aon_i.d_source[1:0]	Yes	Yes	*T49,*T52,*T65	Yes	T49,T52,T65	INPUT
tl_pwm_aon_i.d_source[5:2]	No	No		No		INPUT
tl_pwm_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_size[0]	No	No		No		INPUT
tl_pwm_aon_i.d_size[1]	Yes	Yes	T49,T52	Yes	T65,T49,T106	INPUT
tl_pwm_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_opcode[0]	Yes	Yes	*T65,*T49,*T72	Yes	T65,T49,T72	INPUT
tl_pwm_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_valid	Yes	Yes	T65,T49,T106	Yes	T65,T49,T106	INPUT
tl_gpio_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_gpio_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_source[5:0]	Yes	Yes	*T4,*T49,*T59	Yes	T4,T49,T59	OUTPUT
tl_gpio_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
tl_gpio_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_opcode[0]	Yes	Yes	*T49,*T60,*T52	Yes	T49,T60,T52	OUTPUT
tl_gpio_o.a_opcode[1]	No	No		No		OUTPUT
tl_gpio_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_gpio_i.d_error	No	No		No		INPUT
tl_gpio_i.d_user.data_intg[6:0]	Yes	Yes	T14,T162,T208	Yes	T14,T162,T208	INPUT
tl_gpio_i.d_user.rsp_intg[1:0]	Yes	Yes	T14,T162,T208	Yes	T13,T14,T106	INPUT
tl_gpio_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_gpio_i.d_user.rsp_intg[5:4]	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
tl_gpio_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_gpio_i.d_data[31:0]	Yes	Yes	T14,T162,T208	Yes	T13,T14,T106	INPUT
tl_gpio_i.d_sink	No	No		No		INPUT
tl_gpio_i.d_source[0]	No	No		No		INPUT
tl_gpio_i.d_source[1]	Yes	Yes	*T31,*T32,*T33	Yes	T1,T2,T3	INPUT
tl_gpio_i.d_source[5:2]	No	No		No		INPUT
tl_gpio_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_size[0]	No	No		No		INPUT
tl_gpio_i.d_size[1]	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
tl_gpio_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_opcode[0]	Yes	Yes	*T31,*T32,*T33	Yes	T1,T2,T3	INPUT
tl_gpio_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_device_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.data_intg[6:0]	Yes	Yes	T4,T10,T62	Yes	T4,T10,T62	OUTPUT
tl_spi_device_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_spi_device_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_data[31:0]	Yes	Yes	T4,T10,T62	Yes	T4,T10,T62	OUTPUT
tl_spi_device_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_source[5:0]	Yes	Yes	*T4,*T49,*T59	Yes	T4,T49,T59	OUTPUT
tl_spi_device_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
tl_spi_device_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_opcode[0]	Yes	Yes	*T49,*T60,*T52	Yes	T49,T60,T52	OUTPUT
tl_spi_device_o.a_opcode[1]	No	No		No		OUTPUT
tl_spi_device_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_valid	Yes	Yes	T4,T10,T62	Yes	T4,T10,T62	OUTPUT
tl_spi_device_i.a_ready	Yes	Yes	T4,T10,T62	Yes	T4,T10,T62	INPUT
tl_spi_device_i.d_error	No	No		No		INPUT
tl_spi_device_i.d_user.data_intg[6:0]	Yes	Yes	T4,T10,T62	Yes	T4,T10,T62	INPUT
tl_spi_device_i.d_user.rsp_intg[1:0]	Yes	Yes	T4,T10,T62	Yes	T4,T10,T62	INPUT
tl_spi_device_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_spi_device_i.d_user.rsp_intg[5:4]	Yes	Yes	T4,T10,T62	Yes	T4,T10,T62	INPUT
tl_spi_device_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_spi_device_i.d_data[31:0]	Yes	Yes	T4,T10,T62	Yes	T4,T10,T62	INPUT
tl_spi_device_i.d_sink	No	No		No		INPUT
tl_spi_device_i.d_source[0]	No	No		No		INPUT
tl_spi_device_i.d_source[1]	Yes	Yes	*T4,*T10,*T62	Yes	T4,T10,T62	INPUT
tl_spi_device_i.d_source[5:2]	No	No		No		INPUT
tl_spi_device_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_size[0]	No	No		No		INPUT
tl_spi_device_i.d_size[1]	Yes	Yes	T4,T10,T62	Yes	T4,T10,T62	INPUT
tl_spi_device_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_opcode[0]	Yes	Yes	*T4,*T10,*T62	Yes	T4,T10,T62	INPUT
tl_spi_device_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_valid	Yes	Yes	T4,T10,T62	Yes	T4,T10,T62	INPUT
tl_rv_timer_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.data_intg[6:0]	Yes	Yes	T3,T292,T276	Yes	T3,T292,T276	OUTPUT
tl_rv_timer_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_rv_timer_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_data[31:0]	Yes	Yes	T3,T292,T276	Yes	T3,T292,T276	OUTPUT
tl_rv_timer_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_source[5:0]	Yes	Yes	*T4,*T49,*T59	Yes	T4,T49,T59	OUTPUT
tl_rv_timer_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
tl_rv_timer_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_opcode[0]	Yes	Yes	*T49,*T60,*T52	Yes	T49,T60,T52	OUTPUT
tl_rv_timer_o.a_opcode[1]	No	No		No		OUTPUT
tl_rv_timer_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_valid	Yes	Yes	T3,T292,T276	Yes	T3,T292,T276	OUTPUT
tl_rv_timer_i.a_ready	Yes	Yes	T3,T292,T276	Yes	T3,T292,T276	INPUT
tl_rv_timer_i.d_error	No	No		No		INPUT
tl_rv_timer_i.d_user.data_intg[6:0]	Yes	Yes	T3,T292,T276	Yes	T3,T292,T276	INPUT
tl_rv_timer_i.d_user.rsp_intg[1:0]	Yes	Yes	T3,T292,T276	Yes	T3,T292,T276	INPUT
tl_rv_timer_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_rv_timer_i.d_user.rsp_intg[5:4]	Yes	Yes	T72,*T313,*T3	Yes	T3,T292,T276	INPUT
tl_rv_timer_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_rv_timer_i.d_data[31:0]	Yes	Yes	T3,T292,T276	Yes	T3,T292,T276	INPUT
tl_rv_timer_i.d_sink	No	No		No		INPUT
tl_rv_timer_i.d_source[0]	No	No		No		INPUT
tl_rv_timer_i.d_source[1]	Yes	Yes	*T3,*T292,*T276	Yes	T3,T292,T276	INPUT
tl_rv_timer_i.d_source[5:2]	No	No		No		INPUT
tl_rv_timer_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_size[0]	No	No		No		INPUT
tl_rv_timer_i.d_size[1]	Yes	Yes	T72,T313	Yes	T3,T292,T276	INPUT
tl_rv_timer_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_opcode[0]	Yes	Yes	*T3,*T292,*T276	Yes	T3,T292,T276	INPUT
tl_rv_timer_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_valid	Yes	Yes	T3,T292,T276	Yes	T3,T292,T276	INPUT
tl_pwrmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T67	Yes	T1,T2,T67	OUTPUT
tl_pwrmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T67	Yes	T1,T2,T67	OUTPUT
tl_pwrmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_source[5:0]	Yes	Yes	*T4,*T49,*T59	Yes	T4,T49,T59	OUTPUT
tl_pwrmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
tl_pwrmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_opcode[0]	Yes	Yes	*T49,*T60,*T52	Yes	T49,T60,T52	OUTPUT
tl_pwrmgr_aon_o.a_opcode[1]	No	No		No		OUTPUT
tl_pwrmgr_aon_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_valid	Yes	Yes	T1,T2,T67	Yes	T1,T2,T67	OUTPUT
tl_pwrmgr_aon_i.a_ready	Yes	Yes	T1,T2,T67	Yes	T1,T2,T67	INPUT
tl_pwrmgr_aon_i.d_error	No	No		No		INPUT
tl_pwrmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T67	Yes	T1,T2,T67	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[1:0]	Yes	Yes	T1,T2,T67	Yes	T1,T2,T67	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[5:4]	Yes	Yes	*T277,*T314,*T49	Yes	T1,T2,T67	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_pwrmgr_aon_i.d_data[31:0]	Yes	Yes	T1,T2,T67	Yes	T1,T2,T67	INPUT
tl_pwrmgr_aon_i.d_sink	No	No		No		INPUT
tl_pwrmgr_aon_i.d_source[1:0]	Yes	Yes	*T49,*T52,*T1	Yes	T49,T52,T1	INPUT
tl_pwrmgr_aon_i.d_source[5:2]	No	No		No		INPUT
tl_pwrmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_size[0]	No	No		No		INPUT
tl_pwrmgr_aon_i.d_size[1]	Yes	Yes	T277,T314,T49	Yes	T1,T2,T67	INPUT
tl_pwrmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T67	Yes	T1,T2,T67	INPUT
tl_pwrmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_valid	Yes	Yes	T1,T2,T67	Yes	T1,T2,T67	INPUT
tl_rstmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_source[5:0]	Yes	Yes	*T4,*T49,*T59	Yes	T4,T49,T59	OUTPUT
tl_rstmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
tl_rstmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_opcode[0]	Yes	Yes	*T49,*T60,*T52	Yes	T49,T60,T52	OUTPUT
tl_rstmgr_aon_o.a_opcode[1]	No	No		No		OUTPUT
tl_rstmgr_aon_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_error	No	No		No		INPUT
tl_rstmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[1:0]	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[5:4]	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_rstmgr_aon_i.d_data[31:0]	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_sink	No	No		No		INPUT
tl_rstmgr_aon_i.d_source[1:0]	Yes	Yes	*T49,*T52,*T31	Yes	T49,T52,T1	INPUT
tl_rstmgr_aon_i.d_source[5:2]	No	No		No		INPUT
tl_rstmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_size[0]	No	No		No		INPUT
tl_rstmgr_aon_i.d_size[1]	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T32,T159,T119	Yes	T32,T159,T119	OUTPUT
tl_clkmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_data[31:0]	Yes	Yes	T68,T32,T159	Yes	T68,T32,T159	OUTPUT
tl_clkmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_source[5:0]	Yes	Yes	*T4,*T49,*T59	Yes	T4,T49,T59	OUTPUT
tl_clkmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
tl_clkmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_opcode[0]	Yes	Yes	*T49,*T60,*T52	Yes	T49,T60,T52	OUTPUT
tl_clkmgr_aon_o.a_opcode[1]	No	No		No		OUTPUT
tl_clkmgr_aon_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_error	No	No		No		INPUT
tl_clkmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T159,T15,T250	Yes	T159,T15,T250	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[1:0]	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[5:4]	Yes	Yes	*T31,T32,*T33	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_clkmgr_aon_i.d_data[31:0]	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_sink	No	No		No		INPUT
tl_clkmgr_aon_i.d_source[0]	No	No		No		INPUT
tl_clkmgr_aon_i.d_source[1]	Yes	Yes	*T31,*T32,*T33	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_source[5:2]	No	No		No		INPUT
tl_clkmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_size[0]	No	No		No		INPUT
tl_clkmgr_aon_i.d_size[1]	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_opcode[0]	Yes	Yes	*T32,*T159,*T119	Yes	T32,T159,T119	INPUT
tl_clkmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_pinmux_aon_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_source[5:0]	Yes	Yes	*T4,*T49,*T59	Yes	T4,T49,T59	OUTPUT
tl_pinmux_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
tl_pinmux_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_opcode[0]	Yes	Yes	*T49,*T60,*T52	Yes	T49,T60,T52	OUTPUT
tl_pinmux_aon_o.a_opcode[1]	No	No		No		OUTPUT
tl_pinmux_aon_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_error	No	No		No		INPUT
tl_pinmux_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[2]	No	No		No		INPUT
tl_pinmux_aon_i.d_user.rsp_intg[5:3]	Yes	Yes	*T28,*T29,*T30	Yes	T28,T29,T30	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_pinmux_aon_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_sink	No	No		No		INPUT
tl_pinmux_aon_i.d_source[5:0]	Yes	Yes	*T49,*T52,*T1	Yes	T49,T52,T1	INPUT
tl_pinmux_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
tl_pinmux_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_source[5:0]	Yes	Yes	*T4,*T49,*T59	Yes	T4,T49,T59	OUTPUT
tl_otp_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
tl_otp_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_opcode[0]	Yes	Yes	*T49,*T60,*T52	Yes	T49,T60,T52	OUTPUT
tl_otp_ctrl__core_o.a_opcode[1]	No	No		No		OUTPUT
tl_otp_ctrl__core_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_error	No	No		No		INPUT
tl_otp_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[5:4]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_otp_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_sink	No	No		No		INPUT
tl_otp_ctrl__core_i.d_source[1:0]	Yes	Yes	*T4,*T59,*T174	Yes	T4,T59,T174	INPUT
tl_otp_ctrl__core_i.d_source[5:2]	No	No		No		INPUT
tl_otp_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_size[0]	No	No		No		INPUT
tl_otp_ctrl__core_i.d_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_opcode[0]	Yes	Yes	*T4,*T69,*T6	Yes	T4,T69,T6	INPUT
tl_otp_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__prim_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.data_intg[6:0]	No	No		No		OUTPUT
tl_otp_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_data[31:0]	No	No		No		OUTPUT
tl_otp_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T4,*T49,*T59	Yes	T4,T49,T59	OUTPUT
tl_otp_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
tl_otp_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[0]	Yes	Yes	*T49,*T60,*T52	Yes	T49,T60,T52	OUTPUT
tl_otp_ctrl__prim_o.a_opcode[1]	No	No		No		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_valid	No	No		No		OUTPUT
tl_otp_ctrl__prim_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__prim_i.d_error	Yes	Yes	T1,T2,T3	Yes	T31,T32,T33	INPUT
tl_otp_ctrl__prim_i.d_user.data_intg[6:0]	No	No		No		INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[1:0]	No	No		No		INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[2]	Yes	Yes	*T1,*T2,*T3	Yes	T31,T32,T33	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[4:3]	No	No		No		INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[5]	Yes	Yes	*T31,*T32,*T33	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_otp_ctrl__prim_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T31,T32,T33	INPUT
tl_otp_ctrl__prim_i.d_sink	No	No		No		INPUT
tl_otp_ctrl__prim_i.d_source[5:0]	No	No		No		INPUT
tl_otp_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_size[1:0]	No	No		No		INPUT
tl_otp_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T31,T32,T33	INPUT
tl_otp_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_valid	No	No		No		INPUT
tl_lc_ctrl_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.data_intg[6:0]	Yes	Yes	T101,T4,T111	Yes	T101,T4,T111	OUTPUT
tl_lc_ctrl_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_lc_ctrl_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_data[31:0]	Yes	Yes	T101,T4,T111	Yes	T101,T4,T111	OUTPUT
tl_lc_ctrl_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_source[5:0]	Yes	Yes	*T4,*T49,*T59	Yes	T4,T49,T59	OUTPUT
tl_lc_ctrl_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
tl_lc_ctrl_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_opcode[0]	Yes	Yes	*T49,*T60,*T52	Yes	T49,T60,T52	OUTPUT
tl_lc_ctrl_o.a_opcode[1]	No	No		No		OUTPUT
tl_lc_ctrl_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_valid	Yes	Yes	T101,T4,T111	Yes	T101,T4,T111	OUTPUT
tl_lc_ctrl_i.a_ready	Yes	Yes	T101,T4,T111	Yes	T101,T4,T111	INPUT
tl_lc_ctrl_i.d_error	No	No		No		INPUT
tl_lc_ctrl_i.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T61	Yes	T101,T4,T111	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[1:0]	Yes	Yes	T6,T61,T132	Yes	T6,T61,T132	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_lc_ctrl_i.d_user.rsp_intg[5:4]	Yes	Yes	T101,T4,T111	Yes	T101,T4,T111	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_lc_ctrl_i.d_data[31:0]	Yes	Yes	T101,T4,T111	Yes	T101,T4,T111	INPUT
tl_lc_ctrl_i.d_sink	No	No		No		INPUT
tl_lc_ctrl_i.d_source[1:0]	Yes	Yes	*T103,*T104,*T105	Yes	T103,T104,T105	INPUT
tl_lc_ctrl_i.d_source[5:2]	No	No		No		INPUT
tl_lc_ctrl_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_size[0]	No	No		No		INPUT
tl_lc_ctrl_i.d_size[1]	Yes	Yes	T101,T4,T111	Yes	T101,T4,T111	INPUT
tl_lc_ctrl_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_opcode[0]	Yes	Yes	*T101,*T4,*T111	Yes	T101,T4,T111	INPUT
tl_lc_ctrl_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_valid	Yes	Yes	T101,T4,T111	Yes	T101,T4,T111	INPUT
tl_sensor_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T4,*T49,*T59	Yes	T4,T49,T59	OUTPUT
tl_sensor_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
tl_sensor_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[0]	Yes	Yes	*T49,*T60,*T52	Yes	T49,T60,T52	OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[1]	No	No		No		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_error	No	No		No		INPUT
tl_sensor_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T66,T78,T63	Yes	T66,T78,T63	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[1:0]	Yes	Yes	T66,T78,T63	Yes	T66,T78,T63	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[5:4]	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_sensor_ctrl_aon_i.d_data[31:0]	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_sink	No	No		No		INPUT
tl_sensor_ctrl_aon_i.d_source[0]	No	No		No		INPUT
tl_sensor_ctrl_aon_i.d_source[1]	Yes	Yes	*T31,*T32,*T33	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_source[5:2]	No	No		No		INPUT
tl_sensor_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_size[0]	No	No		No		INPUT
tl_sensor_ctrl_aon_i.d_size[1]	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T31,*T32,*T33	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_alert_handler_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	OUTPUT
tl_alert_handler_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_alert_handler_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_data[31:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	OUTPUT
tl_alert_handler_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_source[5:0]	Yes	Yes	*T4,*T49,*T59	Yes	T4,T49,T59	OUTPUT
tl_alert_handler_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
tl_alert_handler_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_opcode[0]	Yes	Yes	*T49,*T60,*T52	Yes	T49,T60,T52	OUTPUT
tl_alert_handler_o.a_opcode[1]	No	No		No		OUTPUT
tl_alert_handler_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_valid	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	OUTPUT
tl_alert_handler_i.a_ready	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	INPUT
tl_alert_handler_i.d_error	No	No		No		INPUT
tl_alert_handler_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	INPUT
tl_alert_handler_i.d_user.rsp_intg[1:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	INPUT
tl_alert_handler_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_alert_handler_i.d_user.rsp_intg[5:4]	Yes	Yes	T31,T32,T33	Yes	T1,T2,T31	INPUT
tl_alert_handler_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_alert_handler_i.d_data[31:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	INPUT
tl_alert_handler_i.d_sink	No	No		No		INPUT
tl_alert_handler_i.d_source[0]	No	No		No		INPUT
tl_alert_handler_i.d_source[1]	Yes	Yes	*T1,*T2,*T31	Yes	T1,T2,T31	INPUT
tl_alert_handler_i.d_source[5:2]	No	No		No		INPUT
tl_alert_handler_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_size[0]	No	No		No		INPUT
tl_alert_handler_i.d_size[1]	Yes	Yes	T31,T32,T33	Yes	T1,T2,T31	INPUT
tl_alert_handler_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T31	Yes	T1,T2,T31	INPUT
tl_alert_handler_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_valid	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	INPUT
tl_sram_ctrl_ret_aon__regs_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.data_intg[6:0]	Yes	Yes	T46,T43,T47	Yes	T46,T43,T47	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_data[31:0]	Yes	Yes	T46,T43,T47	Yes	T46,T43,T47	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[5:0]	Yes	Yes	*T4,*T49,*T59	Yes	T4,T49,T59	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[0]	Yes	Yes	*T49,*T60,*T52	Yes	T49,T60,T52	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[1]	No	No		No		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_valid	Yes	Yes	T46,T43,T47	Yes	T46,T43,T47	OUTPUT
tl_sram_ctrl_ret_aon__regs_i.a_ready	Yes	Yes	T46,T43,T47	Yes	T46,T43,T47	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_error	No	No		No		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[5:0]	Yes	Yes	*T144,*T199,T200	Yes	T144,T199,T200	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[6]	No	No		No		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[1:0]	Yes	Yes	T43,T44,T45	Yes	T46,T43,T47	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[5:4]	Yes	Yes	*T43,*T44,*T45	Yes	T46,T43,T47	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_data[31:0]	Yes	Yes	T43,T44,T45	Yes	T46,T43,T47	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_sink	No	No		No		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[0]	No	No		No		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[1]	Yes	Yes	*T43,*T44,*T45	Yes	T46,T43,T47	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[5:2]	No	No		No		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[0]	No	No		No		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[1]	Yes	Yes	T43,T44,T45	Yes	T46,T43,T47	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[0]	Yes	Yes	*T144,*T199,*T200	Yes	T144,T199,T200	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_valid	Yes	Yes	T46,T43,T47	Yes	T46,T43,T47	INPUT
tl_sram_ctrl_ret_aon__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[5:0]	Yes	Yes	*T4,*T49,*T59	Yes	T4,T49,T59	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[0]	Yes	Yes	*T49,*T60,*T52	Yes	T49,T60,T52	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[1]	No	No		No		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T31,T32,T33	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[2:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[3]	No	No		No		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[5:4]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_sink	No	No		No		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[1:0]	Yes	Yes	*T60,*T136,*T137	Yes	T60,T136,T137	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[5:2]	No	No		No		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[0]	No	No		No		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_aon_timer_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	OUTPUT
tl_aon_timer_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	OUTPUT
tl_aon_timer_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_source[5:0]	Yes	Yes	*T4,*T49,*T59	Yes	T4,T49,T59	OUTPUT
tl_aon_timer_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
tl_aon_timer_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_opcode[0]	Yes	Yes	*T49,*T60,*T52	Yes	T49,T60,T52	OUTPUT
tl_aon_timer_aon_o.a_opcode[1]	No	No		No		OUTPUT
tl_aon_timer_aon_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_valid	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	OUTPUT
tl_aon_timer_aon_i.a_ready	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	INPUT
tl_aon_timer_aon_i.d_error	No	No		No		INPUT
tl_aon_timer_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[1:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[5:4]	Yes	Yes	T31,T33,T119	Yes	T1,T2,T31	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_aon_timer_aon_i.d_data[31:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	INPUT
tl_aon_timer_aon_i.d_sink	No	No		No		INPUT
tl_aon_timer_aon_i.d_source[0]	No	No		No		INPUT
tl_aon_timer_aon_i.d_source[1]	Yes	Yes	*T1,*T2,*T31	Yes	T1,T2,T31	INPUT
tl_aon_timer_aon_i.d_source[5:2]	No	No		No		INPUT
tl_aon_timer_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_size[0]	No	No		No		INPUT
tl_aon_timer_aon_i.d_size[1]	Yes	Yes	T31,T33,T119	Yes	T1,T2,T31	INPUT
tl_aon_timer_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T31	Yes	T1,T2,T31	INPUT
tl_aon_timer_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_valid	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	INPUT
tl_sysrst_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T262,T20,T117	Yes	T262,T20,T117	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_data[31:0]	Yes	Yes	T262,T20,T117	Yes	T262,T20,T117	OUTPUT
tl_sysrst_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T4,*T49,*T59	Yes	T4,T49,T59	OUTPUT
tl_sysrst_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
tl_sysrst_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[0]	Yes	Yes	*T49,*T60,*T52	Yes	T49,T60,T52	OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[1]	No	No		No		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_valid	Yes	Yes	T262,T20,T117	Yes	T262,T20,T117	OUTPUT
tl_sysrst_ctrl_aon_i.a_ready	Yes	Yes	T262,T20,T117	Yes	T262,T20,T117	INPUT
tl_sysrst_ctrl_aon_i.d_error	No	No		No		INPUT
tl_sysrst_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T262,T20,T117	Yes	T262,T20,T117	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[1:0]	Yes	Yes	T20,T117,T21	Yes	T20,T117,T21	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[5:4]	Yes	Yes	T20,T21,T22	Yes	T262,T20,T117	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_sysrst_ctrl_aon_i.d_data[31:0]	Yes	Yes	T262,T20,T21	Yes	T262,T20,T117	INPUT
tl_sysrst_ctrl_aon_i.d_sink	No	No		No		INPUT
tl_sysrst_ctrl_aon_i.d_source[0]	No	No		No		INPUT
tl_sysrst_ctrl_aon_i.d_source[1]	Yes	Yes	*T262,*T20,*T21	Yes	T262,T20,T117	INPUT
tl_sysrst_ctrl_aon_i.d_source[5:2]	No	No		No		INPUT
tl_sysrst_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_size[0]	No	No		No		INPUT
tl_sysrst_ctrl_aon_i.d_size[1]	Yes	Yes	T20,T21,T22	Yes	T262,T20,T117	INPUT
tl_sysrst_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T20,*T117,*T21	Yes	T262,T20,T117	INPUT
tl_sysrst_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_valid	Yes	Yes	T262,T20,T117	Yes	T262,T20,T117	INPUT
tl_adc_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T66,T18,T208	Yes	T66,T18,T208	OUTPUT
tl_adc_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_data[31:0]	Yes	Yes	T66,T18,T208	Yes	T66,T18,T208	OUTPUT
tl_adc_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T4,*T49,*T59	Yes	T4,T49,T59	OUTPUT
tl_adc_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
tl_adc_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[0]	Yes	Yes	*T49,*T60,*T52	Yes	T49,T60,T52	OUTPUT
tl_adc_ctrl_aon_o.a_opcode[1]	No	No		No		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_valid	Yes	Yes	T66,T106,T18	Yes	T66,T106,T18	OUTPUT
tl_adc_ctrl_aon_i.a_ready	Yes	Yes	T66,T106,T18	Yes	T66,T106,T18	INPUT
tl_adc_ctrl_aon_i.d_error	No	No		No		INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T66,T18,T208	Yes	T66,T18,T208	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[1:0]	Yes	Yes	T66,T18,T208	Yes	T66,T106,T18	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[5:4]	Yes	Yes	T50,*T51,*T315	Yes	T66,T106,T18	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_adc_ctrl_aon_i.d_data[31:0]	Yes	Yes	T66,T18,T72	Yes	T66,T106,T18	INPUT
tl_adc_ctrl_aon_i.d_sink	No	No		No		INPUT
tl_adc_ctrl_aon_i.d_source[0]	No	No		No		INPUT
tl_adc_ctrl_aon_i.d_source[1]	Yes	Yes	*T66,*T18,*T208	Yes	T66,T18,T208	INPUT
tl_adc_ctrl_aon_i.d_source[5:2]	No	No		No		INPUT
tl_adc_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_size[0]	No	No		No		INPUT
tl_adc_ctrl_aon_i.d_size[1]	Yes	Yes	T50,T51,T315	Yes	T66,T106,T18	INPUT
tl_adc_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T66,*T18,*T208	Yes	T66,T18,T208	INPUT
tl_adc_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_valid	Yes	Yes	T66,T106,T18	Yes	T66,T106,T18	INPUT
tl_ast_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_ast_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_source[5:0]	Yes	Yes	*T4,*T49,*T59	Yes	T4,T49,T59	OUTPUT
tl_ast_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
tl_ast_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_opcode[0]	Yes	Yes	*T49,*T60,*T52	Yes	T49,T60,T52	OUTPUT
tl_ast_o.a_opcode[1]	No	No		No		OUTPUT
tl_ast_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_ast_i.d_error	No	No		No		INPUT
tl_ast_i.d_user.data_intg[6:0]	No	No		No		INPUT
tl_ast_i.d_user.rsp_intg[1:0]	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
tl_ast_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_ast_i.d_user.rsp_intg[4]	Yes	Yes	*T31,*T32,*T33	Yes	T1,T2,T3	INPUT
tl_ast_i.d_user.rsp_intg[6:5]	No	No		No		INPUT
tl_ast_i.d_data[31:0]	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
tl_ast_i.d_sink	No	No		No		INPUT
tl_ast_i.d_source[0]	No	No		No		INPUT
tl_ast_i.d_source[5:1]	Yes	Yes	T49,T60,T52	Yes	T49,T60,T52	INPUT
tl_ast_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_size[0]	No	No		No		INPUT
tl_ast_i.d_size[1]	Yes	Yes	T31,T32,T33	Yes	T1,T2,T3	INPUT
tl_ast_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_opcode[0]	No	No		No		INPUT
tl_ast_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range