Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	96.55	100.00	93.33			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T49,T202,T203
0	1	Covered	T202,T203,T275
1	0	Covered	T49,T52

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T49,T202,T203
1	Covered	T49,T202,T203

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T49,T202,T203
1	Covered	T49,T202,T203

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T202,T203,T275
1	1	Covered	T49,T202,T203

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T49,T202,T203
1	0	Covered	T49,T202,T203
1	1	Covered	T202,T203,T275

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T49,T202,T203

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T49,T202,T203
0	Covered	T49,T202,T203

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T49,T202,T203
0	Covered	T49,T202,T203

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	857612898	843096342	0	0
CheckNGreaterZero_A	1908	1908	0	0
GntImpliesReady_A	857612898	5355	0	0
GntImpliesValid_A	857612898	5355	0	0
GrantKnown_A	857612898	843096342	0	0
IdxKnown_A	857612898	843096342	0	0
IndexIsCorrect_A	857612898	5355	0	0
NoReadyValidNoGrant_A	857612898	0	0	0
Priority_A	857612898	5355	0	0
ReadyAndValidImplyGrant_A	857612898	5355	0	0
ReqAndReadyImplyGrant_A	857612898	5355	0	0
ReqImpliesValid_A	857612898	5355	0	0
ValidKnown_A	857612898	843096342	0	0
gen_data_port_assertion.DataFlow_A	857612898	5355	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	857612898	843096342	0	0
T1	298348	298232	0	0
T2	256540	256424	0	0
T3	173988	173878	0	0
T31	612742	612516	0	0
T32	528774	528556	0	0
T33	576242	576010	0	0
T67	294884	294774	0	0
T68	174090	173980	0	0
T118	271092	270976	0	0
T159	324452	324336	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1908	1908	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T31	2	2	0	0
T32	2	2	0	0
T33	2	2	0	0
T67	2	2	0	0
T68	2	2	0	0
T118	2	2	0	0
T159	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	857612898	5355	0	0
T146	964240	0	0	0
T157	531296	0	0	0
T161	520772	0	0	0
T162	170922	0	0	0
T163	349240	0	0	0
T164	231160	0	0	0
T165	168346	0	0	0
T166	257636	0	0	0
T202	146510	1786	0	0
T203	0	1785	0	0
T275	0	1784	0	0
T396	454846	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	857612898	5355	0	0
T146	964240	0	0	0
T157	531296	0	0	0
T161	520772	0	0	0
T162	170922	0	0	0
T163	349240	0	0	0
T164	231160	0	0	0
T165	168346	0	0	0
T166	257636	0	0	0
T202	146510	1786	0	0
T203	0	1785	0	0
T275	0	1784	0	0
T396	454846	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	857612898	843096342	0	0
T1	298348	298232	0	0
T2	256540	256424	0	0
T3	173988	173878	0	0
T31	612742	612516	0	0
T32	528774	528556	0	0
T33	576242	576010	0	0
T67	294884	294774	0	0
T68	174090	173980	0	0
T118	271092	270976	0	0
T159	324452	324336	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	857612898	843096342	0	0
T1	298348	298232	0	0
T2	256540	256424	0	0
T3	173988	173878	0	0
T31	612742	612516	0	0
T32	528774	528556	0	0
T33	576242	576010	0	0
T67	294884	294774	0	0
T68	174090	173980	0	0
T118	271092	270976	0	0
T159	324452	324336	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	857612898	5355	0	0
T146	964240	0	0	0
T157	531296	0	0	0
T161	520772	0	0	0
T162	170922	0	0	0
T163	349240	0	0	0
T164	231160	0	0	0
T165	168346	0	0	0
T166	257636	0	0	0
T202	146510	1786	0	0
T203	0	1785	0	0
T275	0	1784	0	0
T396	454846	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	857612898	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	857612898	5355	0	0
T146	964240	0	0	0
T157	531296	0	0	0
T161	520772	0	0	0
T162	170922	0	0	0
T163	349240	0	0	0
T164	231160	0	0	0
T165	168346	0	0	0
T166	257636	0	0	0
T202	146510	1786	0	0
T203	0	1785	0	0
T275	0	1784	0	0
T396	454846	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	857612898	5355	0	0
T146	964240	0	0	0
T157	531296	0	0	0
T161	520772	0	0	0
T162	170922	0	0	0
T163	349240	0	0	0
T164	231160	0	0	0
T165	168346	0	0	0
T166	257636	0	0	0
T202	146510	1786	0	0
T203	0	1785	0	0
T275	0	1784	0	0
T396	454846	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	857612898	5355	0	0
T146	964240	0	0	0
T157	531296	0	0	0
T161	520772	0	0	0
T162	170922	0	0	0
T163	349240	0	0	0
T164	231160	0	0	0
T165	168346	0	0	0
T166	257636	0	0	0
T202	146510	1786	0	0
T203	0	1785	0	0
T275	0	1784	0	0
T396	454846	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	857612898	5355	0	0
T146	964240	0	0	0
T157	531296	0	0	0
T161	520772	0	0	0
T162	170922	0	0	0
T163	349240	0	0	0
T164	231160	0	0	0
T165	168346	0	0	0
T166	257636	0	0	0
T202	146510	1786	0	0
T203	0	1785	0	0
T275	0	1784	0	0
T396	454846	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	857612898	843096342	0	0
T1	298348	298232	0	0
T2	256540	256424	0	0
T3	173988	173878	0	0
T31	612742	612516	0	0
T32	528774	528556	0	0
T33	576242	576010	0	0
T67	294884	294774	0	0
T68	174090	173980	0	0
T118	271092	270976	0	0
T159	324452	324336	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	857612898	5355	0	0
T146	964240	0	0	0
T157	531296	0	0	0
T161	520772	0	0	0
T162	170922	0	0	0
T163	349240	0	0	0
T164	231160	0	0	0
T165	168346	0	0	0
T166	257636	0	0	0
T202	146510	1786	0	0
T203	0	1785	0	0
T275	0	1784	0	0
T396	454846	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T49,T202,T203
0	1	Covered	T202,T203,T275
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T202,T203,T275
1	Covered	T49,T202,T203

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T202,T203,T275
1	Covered	T49,T202,T203

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T202,T203,T275
1	1	Covered	T202,T203,T275

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T49,T202,T203
1	0	Covered	T202,T203,T275
1	1	Covered	T202,T203,T275

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T202,T203,T275

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T49,T202,T203
0	Covered	T202,T203,T275

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T49,T202,T203
0	Covered	T202,T203,T275

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	428806449	421548171	0	0
CheckNGreaterZero_A	954	954	0	0
GntImpliesReady_A	428806449	4317	0	0
GntImpliesValid_A	428806449	4317	0	0
GrantKnown_A	428806449	421548171	0	0
IdxKnown_A	428806449	421548171	0	0
IndexIsCorrect_A	428806449	4317	0	0
NoReadyValidNoGrant_A	428806449	0	0	0
Priority_A	428806449	4317	0	0
ReadyAndValidImplyGrant_A	428806449	4317	0	0
ReqAndReadyImplyGrant_A	428806449	4317	0	0
ReqImpliesValid_A	428806449	4317	0	0
ValidKnown_A	428806449	421548171	0	0
gen_data_port_assertion.DataFlow_A	428806449	4317	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	421548171	0	0
T1	149174	149116	0	0
T2	128270	128212	0	0
T3	86994	86939	0	0
T31	306371	306258	0	0
T32	264387	264278	0	0
T33	288121	288005	0	0
T67	147442	147387	0	0
T68	87045	86990	0	0
T118	135546	135488	0	0
T159	162226	162168	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T118	1	1	0	0
T159	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	4317	0	0
T146	482120	0	0	0
T157	265648	0	0	0
T161	260386	0	0	0
T162	85461	0	0	0
T163	174620	0	0	0
T164	115580	0	0	0
T165	84173	0	0	0
T166	128818	0	0	0
T202	73255	1440	0	0
T203	0	1439	0	0
T275	0	1438	0	0
T396	227423	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	4317	0	0
T146	482120	0	0	0
T157	265648	0	0	0
T161	260386	0	0	0
T162	85461	0	0	0
T163	174620	0	0	0
T164	115580	0	0	0
T165	84173	0	0	0
T166	128818	0	0	0
T202	73255	1440	0	0
T203	0	1439	0	0
T275	0	1438	0	0
T396	227423	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	421548171	0	0
T1	149174	149116	0	0
T2	128270	128212	0	0
T3	86994	86939	0	0
T31	306371	306258	0	0
T32	264387	264278	0	0
T33	288121	288005	0	0
T67	147442	147387	0	0
T68	87045	86990	0	0
T118	135546	135488	0	0
T159	162226	162168	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	421548171	0	0
T1	149174	149116	0	0
T2	128270	128212	0	0
T3	86994	86939	0	0
T31	306371	306258	0	0
T32	264387	264278	0	0
T33	288121	288005	0	0
T67	147442	147387	0	0
T68	87045	86990	0	0
T118	135546	135488	0	0
T159	162226	162168	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	4317	0	0
T146	482120	0	0	0
T157	265648	0	0	0
T161	260386	0	0	0
T162	85461	0	0	0
T163	174620	0	0	0
T164	115580	0	0	0
T165	84173	0	0	0
T166	128818	0	0	0
T202	73255	1440	0	0
T203	0	1439	0	0
T275	0	1438	0	0
T396	227423	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	4317	0	0
T146	482120	0	0	0
T157	265648	0	0	0
T161	260386	0	0	0
T162	85461	0	0	0
T163	174620	0	0	0
T164	115580	0	0	0
T165	84173	0	0	0
T166	128818	0	0	0
T202	73255	1440	0	0
T203	0	1439	0	0
T275	0	1438	0	0
T396	227423	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	4317	0	0
T146	482120	0	0	0
T157	265648	0	0	0
T161	260386	0	0	0
T162	85461	0	0	0
T163	174620	0	0	0
T164	115580	0	0	0
T165	84173	0	0	0
T166	128818	0	0	0
T202	73255	1440	0	0
T203	0	1439	0	0
T275	0	1438	0	0
T396	227423	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	4317	0	0
T146	482120	0	0	0
T157	265648	0	0	0
T161	260386	0	0	0
T162	85461	0	0	0
T163	174620	0	0	0
T164	115580	0	0	0
T165	84173	0	0	0
T166	128818	0	0	0
T202	73255	1440	0	0
T203	0	1439	0	0
T275	0	1438	0	0
T396	227423	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	4317	0	0
T146	482120	0	0	0
T157	265648	0	0	0
T161	260386	0	0	0
T162	85461	0	0	0
T163	174620	0	0	0
T164	115580	0	0	0
T165	84173	0	0	0
T166	128818	0	0	0
T202	73255	1440	0	0
T203	0	1439	0	0
T275	0	1438	0	0
T396	227423	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	421548171	0	0
T1	149174	149116	0	0
T2	128270	128212	0	0
T3	86994	86939	0	0
T31	306371	306258	0	0
T32	264387	264278	0	0
T33	288121	288005	0	0
T67	147442	147387	0	0
T68	87045	86990	0	0
T118	135546	135488	0	0
T159	162226	162168	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	4317	0	0
T146	482120	0	0	0
T157	265648	0	0	0
T161	260386	0	0	0
T162	85461	0	0	0
T163	174620	0	0	0
T164	115580	0	0	0
T165	84173	0	0	0
T166	128818	0	0	0
T202	73255	1440	0	0
T203	0	1439	0	0
T275	0	1438	0	0
T396	227423	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T49,T202,T203
0	1	Covered	T202,T203,T275
1	0	Covered	T49,T52

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T49,T202,T203
1	Covered	T49,T202,T203

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T49,T202,T203
1	Covered	T49,T202,T203

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T202,T203,T275
1	1	Covered	T49,T202,T203

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T49,T202,T203
1	0	Covered	T49,T202,T203
1	1	Covered	T202,T203,T275

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T49,T202,T203

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T49,T202,T203
0	Covered	T49,T202,T203

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T49,T202,T203
0	Covered	T49,T202,T203

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	428806449	421548171	0	0
CheckNGreaterZero_A	954	954	0	0
GntImpliesReady_A	428806449	1038	0	0
GntImpliesValid_A	428806449	1038	0	0
GrantKnown_A	428806449	421548171	0	0
IdxKnown_A	428806449	421548171	0	0
IndexIsCorrect_A	428806449	1038	0	0
NoReadyValidNoGrant_A	428806449	0	0	0
Priority_A	428806449	1038	0	0
ReadyAndValidImplyGrant_A	428806449	1038	0	0
ReqAndReadyImplyGrant_A	428806449	1038	0	0
ReqImpliesValid_A	428806449	1038	0	0
ValidKnown_A	428806449	421548171	0	0
gen_data_port_assertion.DataFlow_A	428806449	1038	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	421548171	0	0
T1	149174	149116	0	0
T2	128270	128212	0	0
T3	86994	86939	0	0
T31	306371	306258	0	0
T32	264387	264278	0	0
T33	288121	288005	0	0
T67	147442	147387	0	0
T68	87045	86990	0	0
T118	135546	135488	0	0
T159	162226	162168	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T118	1	1	0	0
T159	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	1038	0	0
T146	482120	0	0	0
T157	265648	0	0	0
T161	260386	0	0	0
T162	85461	0	0	0
T163	174620	0	0	0
T164	115580	0	0	0
T165	84173	0	0	0
T166	128818	0	0	0
T202	73255	346	0	0
T203	0	346	0	0
T275	0	346	0	0
T396	227423	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	1038	0	0
T146	482120	0	0	0
T157	265648	0	0	0
T161	260386	0	0	0
T162	85461	0	0	0
T163	174620	0	0	0
T164	115580	0	0	0
T165	84173	0	0	0
T166	128818	0	0	0
T202	73255	346	0	0
T203	0	346	0	0
T275	0	346	0	0
T396	227423	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	421548171	0	0
T1	149174	149116	0	0
T2	128270	128212	0	0
T3	86994	86939	0	0
T31	306371	306258	0	0
T32	264387	264278	0	0
T33	288121	288005	0	0
T67	147442	147387	0	0
T68	87045	86990	0	0
T118	135546	135488	0	0
T159	162226	162168	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	421548171	0	0
T1	149174	149116	0	0
T2	128270	128212	0	0
T3	86994	86939	0	0
T31	306371	306258	0	0
T32	264387	264278	0	0
T33	288121	288005	0	0
T67	147442	147387	0	0
T68	87045	86990	0	0
T118	135546	135488	0	0
T159	162226	162168	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	1038	0	0
T146	482120	0	0	0
T157	265648	0	0	0
T161	260386	0	0	0
T162	85461	0	0	0
T163	174620	0	0	0
T164	115580	0	0	0
T165	84173	0	0	0
T166	128818	0	0	0
T202	73255	346	0	0
T203	0	346	0	0
T275	0	346	0	0
T396	227423	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	1038	0	0
T146	482120	0	0	0
T157	265648	0	0	0
T161	260386	0	0	0
T162	85461	0	0	0
T163	174620	0	0	0
T164	115580	0	0	0
T165	84173	0	0	0
T166	128818	0	0	0
T202	73255	346	0	0
T203	0	346	0	0
T275	0	346	0	0
T396	227423	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	1038	0	0
T146	482120	0	0	0
T157	265648	0	0	0
T161	260386	0	0	0
T162	85461	0	0	0
T163	174620	0	0	0
T164	115580	0	0	0
T165	84173	0	0	0
T166	128818	0	0	0
T202	73255	346	0	0
T203	0	346	0	0
T275	0	346	0	0
T396	227423	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	1038	0	0
T146	482120	0	0	0
T157	265648	0	0	0
T161	260386	0	0	0
T162	85461	0	0	0
T163	174620	0	0	0
T164	115580	0	0	0
T165	84173	0	0	0
T166	128818	0	0	0
T202	73255	346	0	0
T203	0	346	0	0
T275	0	346	0	0
T396	227423	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	1038	0	0
T146	482120	0	0	0
T157	265648	0	0	0
T161	260386	0	0	0
T162	85461	0	0	0
T163	174620	0	0	0
T164	115580	0	0	0
T165	84173	0	0	0
T166	128818	0	0	0
T202	73255	346	0	0
T203	0	346	0	0
T275	0	346	0	0
T396	227423	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	421548171	0	0
T1	149174	149116	0	0
T2	128270	128212	0	0
T3	86994	86939	0	0
T31	306371	306258	0	0
T32	264387	264278	0	0
T33	288121	288005	0	0
T67	147442	147387	0	0
T68	87045	86990	0	0
T118	135546	135488	0	0
T159	162226	162168	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428806449	1038	0	0
T146	482120	0	0	0
T157	265648	0	0	0
T161	260386	0	0	0
T162	85461	0	0	0
T163	174620	0	0	0
T164	115580	0	0	0
T165	84173	0	0	0
T166	128818	0	0	0
T202	73255	346	0	0
T203	0	346	0	0
T275	0	346	0	0
T396	227423	0	0	0