Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : edn
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.45 95.45

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_edn1 92.56 92.56
tb.dut.top_earlgrey.u_edn0 95.19 95.19


Module Instance : tb.dut.top_earlgrey.u_edn1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.56 92.56


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.56 92.56


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.57 92.83 90.88 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_edn0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 95.19


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 95.19


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.57 92.83 90.88 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : edn
TotalCoveredPercent
Totals 78 63 80.77
Total Bits 1208 1153 95.45
Total Bits 0->1 604 578 95.70
Total Bits 1->0 604 575 95.20

Ports 78 63 80.77
Port Bits 1208 1153 95.45
Port Bits 0->1 604 578 95.70
Port Bits 1->0 604 575 95.20

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T31,T32,T33 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T76,T74,T66 Yes T76,T74,T66 INPUT
tl_i.a_user.cmd_intg[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[1] No No No INPUT
tl_i.a_user.cmd_intg[6:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T76,T74,T66 Yes T76,T74,T66 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[6:2] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20:16] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[0] No No No INPUT
tl_i.a_source[1] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_source[5:2] No No No INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[0] No No No INPUT
tl_i.a_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[1:0] No No No INPUT
tl_i.a_opcode[2] Yes Yes T76,T74,T66 Yes T76,T74,T66 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T76,T74,T66 Yes T76,T74,T66 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T31,T32,T33 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:4] Yes Yes *T31,*T32,*T33 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T31,T32,T33 Yes T1,T2,T3 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[0] No No No OUTPUT
tl_o.d_source[1] Yes Yes *T31,*T32,*T33 Yes T1,T2,T3 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] Yes Yes T31,T32,T33 Yes T1,T2,T3 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T76,*T74,*T66 Yes T76,T74,T66 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_i[0].edn_req Yes Yes T32,T69,T127 Yes T32,T69,T127 INPUT
edn_i[1].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[2].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[3].edn_req Yes Yes T127,T380,T324 Yes T127,T380,T324 INPUT
edn_i[4].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[5].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[6].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[7].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T32,T69,T127 Yes T32,T69,T127 OUTPUT
edn_o[0].edn_fips Yes Yes T135,T205,T77 Yes T127,T135,T288 OUTPUT
edn_o[0].edn_ack Yes Yes T32,T69,T127 Yes T32,T69,T127 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[1].edn_fips No No Yes T76,T172,T173 OUTPUT
edn_o[1].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T2,T31,T68 Yes T1,T2,T3 OUTPUT
edn_o[2].edn_fips Yes Yes T66,T77,T73 Yes T66,T77,T73 OUTPUT
edn_o[2].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T127,T380,T324 Yes T127,T380,T324 OUTPUT
edn_o[3].edn_fips No No Yes T127,T324,T381 OUTPUT
edn_o[3].edn_ack Yes Yes T127,T380,T324 Yes T127,T380,T324 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T32,T33,T134 Yes T3,T32,T33 OUTPUT
edn_o[4].edn_fips No No Yes T382,T383,T384 OUTPUT
edn_o[4].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[5].edn_fips Yes Yes T385,T386,T387 Yes T127,T388,T324 OUTPUT
edn_o[5].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[6].edn_fips Yes Yes T135,T205,T77 Yes T76,T127,T135 OUTPUT
edn_o[6].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[7].edn_bus[31:0] Yes Yes T31,T67,T118 Yes T31,T67,T68 OUTPUT
edn_o[7].edn_fips Yes Yes T66,T135,T205 Yes T66,T127,T135 OUTPUT
edn_o[7].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T31,T32,T33 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.genbits_fips Yes Yes T66,T205,T389 Yes T76,T66,T127 INPUT
csrng_cmd_i.genbits_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_rsp_sts[1:0] No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T74,T75,T135 Yes T74,T75,T135 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T74,T75,T106 Yes T74,T75,T106 INPUT
alert_rx_i[0].ping_n Yes Yes T147,T148,T158 Yes T147,T148,T158 INPUT
alert_rx_i[0].ping_p Yes Yes T147,T148,T158 Yes T147,T148,T158 INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T390,T106,T147 Yes T390,T106,T147 INPUT
alert_rx_i[1].ping_n Yes Yes T147,T148,T158 Yes T147,T148,T158 INPUT
alert_rx_i[1].ping_p Yes Yes T147,T148,T158 Yes T147,T148,T158 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T74,T75,T106 Yes T74,T75,T106 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T390,T106,T147 Yes T390,T106,T147 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T208,T209,T342 Yes T208,T209,T342 OUTPUT
intr_edn_fatal_err_o Yes Yes T208,T209,T210 Yes T208,T209,T210 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn1
TotalCoveredPercent
Totals 50 37 74.00
Total Bits 712 659 92.56
Total Bits 0->1 356 330 92.70
Total Bits 1->0 356 329 92.42

Ports 50 37 74.00
Port Bits 712 659 92.56
Port Bits 0->1 356 330 92.70
Port Bits 1->0 356 329 92.42

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T31,T32,T33 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T31,T32,T33 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T76,T74,T66 Yes T76,T74,T66 INPUT
tl_i.a_user.cmd_intg[0] Yes Yes *T76,*T74,*T66 Yes T76,T74,T66 INPUT
tl_i.a_user.cmd_intg[1] No No No INPUT
tl_i.a_user.cmd_intg[6:2] Yes Yes T76,T74,T66 Yes T76,T74,T66 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T76,*T74,*T66 Yes T76,T74,T66 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T76,T74,T66 Yes T76,T74,T66 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T76,T74,T66 Yes T76,T74,T66 INPUT
tl_i.a_mask[3:0] Yes Yes T76,T74,T66 Yes T76,T74,T66 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[6:2] Yes Yes *T76,*T74,*T66 Yes T76,T74,T66 INPUT
tl_i.a_address[18:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20:19] Yes Yes T76,T74,T66 Yes T76,T74,T66 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T76,*T74,*T66 Yes T76,T74,T66 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T76,*T74,*T66 Yes T76,T74,T66 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[0] No No No INPUT
tl_i.a_source[1] Yes Yes *T76,*T74,*T66 Yes T76,T74,T66 INPUT
tl_i.a_source[5:2] No No No INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[0] No No No INPUT
tl_i.a_size[1] Yes Yes T76,T74,T66 Yes T76,T74,T66 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[1:0] No No No INPUT
tl_i.a_opcode[2] Yes Yes T76,T74,T66 Yes T76,T74,T66 INPUT
tl_i.a_valid Yes Yes T76,T74,T66 Yes T76,T74,T66 INPUT
tl_o.a_ready Yes Yes T76,T74,T66 Yes T76,T74,T66 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T76,T74,T66 Yes T76,T74,T66 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T76,T74,T66 Yes T76,T74,T66 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:4] Yes Yes T66,T132,*T133 Yes T76,T74,T66 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T76,T74,T66 Yes T76,T74,T66 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[0] No No No OUTPUT
tl_o.d_source[1] Yes Yes *T76,*T74,*T66 Yes T76,T74,T66 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] Yes Yes T66,T132,T133 Yes T76,T74,T66 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T76,*T74,*T66 Yes T76,T74,T66 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T76,T74,T66 Yes T76,T74,T66 OUTPUT
edn_i[0].edn_req Yes Yes T127,T135,T205 Yes T127,T135,T205 INPUT
edn_i[1].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[2].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[3].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[4].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[5].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[6].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[7].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_o[0].edn_bus[31:0] Yes Yes T127,T135,T205 Yes T127,T135,T205 OUTPUT
edn_o[0].edn_fips Yes Yes T135,T205,T77 Yes T127,T135,T205 OUTPUT
edn_o[0].edn_ack Yes Yes T127,T135,T205 Yes T127,T135,T205 OUTPUT
edn_o[1].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[1].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[1].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
csrng_cmd_o.genbits_ready Yes Yes T76,T74,T66 Yes T76,T74,T66 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T74,T66,T75 Yes T76,T74,T66 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T76,T74,T66 Yes T76,T74,T66 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T74,T66,T127 Yes T76,T66,T75 INPUT
csrng_cmd_i.genbits_fips No No Yes T205,T389,T391 INPUT
csrng_cmd_i.genbits_valid Yes Yes T76,T74,T66 Yes T76,T74,T66 INPUT
csrng_cmd_i.csrng_rsp_sts[1:0] No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T76,T74,T66 Yes T76,T74,T66 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T135,T77,T392 Yes T135,T77,T392 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T106,T147,T148 Yes T106,T147,T148 INPUT
alert_rx_i[0].ping_n Yes Yes T147,T148,T158 Yes T147,T148,T158 INPUT
alert_rx_i[0].ping_p Yes Yes T147,T148,T158 Yes T147,T148,T158 INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T390,T106,T147 Yes T390,T106,T147 INPUT
alert_rx_i[1].ping_n Yes Yes T147,T148,T158 Yes T148,T158,T245 INPUT
alert_rx_i[1].ping_p Yes Yes T148,T158,T245 Yes T147,T148,T158 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T106,T147,T148 Yes T106,T147,T148 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T390,T106,T147 Yes T390,T106,T147 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T208,T209,T342 Yes T208,T209,T342 OUTPUT
intr_edn_fatal_err_o Yes Yes T208,T209,T210 Yes T208,T209,T210 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn0
TotalCoveredPercent
Totals 78 61 78.21
Total Bits 1206 1148 95.19
Total Bits 0->1 603 576 95.52
Total Bits 1->0 603 572 94.86

Ports 78 61 78.21
Port Bits 1206 1148 95.19
Port Bits 0->1 603 576 95.52
Port Bits 1->0 603 572 94.86

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T31,T32,T33 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T76,T74,T66 Yes T76,T74,T66 INPUT
tl_i.a_user.cmd_intg[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[1] No No No INPUT
tl_i.a_user.cmd_intg[6:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T76,T74,T66 Yes T76,T74,T66 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[6:2] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[18:16] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[19] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[0] No No No INPUT
tl_i.a_source[1] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_source[5:2] No No No INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[0] No No No INPUT
tl_i.a_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[1:0] No No No INPUT
tl_i.a_opcode[2] Yes Yes T76,T74,T66 Yes T76,T74,T66 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[0] Yes Yes *T76,*T74,*T66 Yes T76,T74,T66 OUTPUT
tl_o.d_user.data_intg[1] No No No OUTPUT
tl_o.d_user.data_intg[6:2] Yes Yes T76,T74,T66 Yes T76,T74,T66 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T31,T32,T33 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:4] Yes Yes *T31,*T32,*T33 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T31,T32,T33 Yes T1,T2,T3 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[0] No No No OUTPUT
tl_o.d_source[1] Yes Yes *T31,*T32,*T33 Yes T1,T2,T3 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] Yes Yes T31,T32,T33 Yes T1,T2,T3 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T76,*T74,*T66 Yes T76,T74,T66 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_i[0].edn_req Yes Yes T32,T69,T127 Yes T32,T69,T127 INPUT
edn_i[1].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[2].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[3].edn_req Yes Yes T127,T380,T324 Yes T127,T380,T324 INPUT
edn_i[4].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[5].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[6].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[7].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T32,T69,T127 Yes T32,T69,T127 OUTPUT
edn_o[0].edn_fips No No Yes T127,T288,T324 OUTPUT
edn_o[0].edn_ack Yes Yes T32,T69,T127 Yes T32,T69,T127 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[1].edn_fips No No Yes T76,T172,T173 OUTPUT
edn_o[1].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T2,T31,T68 Yes T1,T2,T3 OUTPUT
edn_o[2].edn_fips Yes Yes T66,T77,T73 Yes T66,T77,T73 OUTPUT
edn_o[2].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T127,T380,T324 Yes T127,T380,T324 OUTPUT
edn_o[3].edn_fips No No Yes T127,T324,T381 OUTPUT
edn_o[3].edn_ack Yes Yes T127,T380,T324 Yes T127,T380,T324 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T32,T33,T134 Yes T3,T32,T33 OUTPUT
edn_o[4].edn_fips No No Yes T382,T383,T384 OUTPUT
edn_o[4].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[5].edn_fips Yes Yes T385,T386,T387 Yes T127,T388,T324 OUTPUT
edn_o[5].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[6].edn_fips Yes Yes T135,T205,T77 Yes T76,T127,T135 OUTPUT
edn_o[6].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[7].edn_bus[31:0] Yes Yes T31,T67,T118 Yes T31,T67,T68 OUTPUT
edn_o[7].edn_fips Yes Yes T66,T135,T205 Yes T66,T127,T135 OUTPUT
edn_o[7].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T31,T32,T33 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.genbits_fips Yes Yes T66,T205,T389 Yes T76,T66,T127 INPUT
csrng_cmd_i.genbits_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_rsp_sts[1:0] No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T74,T75,T135 Yes T74,T75,T135 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T74,T75,T106 Yes T74,T75,T106 INPUT
alert_rx_i[0].ping_n Yes Yes T147,T148,T158 Yes T147,T148,T158 INPUT
alert_rx_i[0].ping_p Yes Yes T147,T148,T158 Yes T147,T148,T158 INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T106,T147,T148 Yes T106,T147,T148 INPUT
alert_rx_i[1].ping_n Yes Yes T147,T148,T158 Yes T147,T148,T158 INPUT
alert_rx_i[1].ping_p Yes Yes T147,T148,T158 Yes T147,T148,T158 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T74,T75,T106 Yes T74,T75,T106 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T106,T147,T148 Yes T106,T147,T148 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T208,T209,T342 Yes T208,T209,T342 OUTPUT
intr_edn_fatal_err_o Yes Yes T208,T209,T210 Yes T208,T209,T210 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%