Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
88.96 89.80 79.30 90.01 91.93 97.38 85.31


Total test records in report: 954
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html
T89 /workspace/coverage/default/4.chip_tap_straps_testunlock0.1235059744 Apr 15 04:11:57 PM PDT 24 Apr 15 04:18:51 PM PDT 24 4818342529 ps
T115 /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.2221285872 Apr 15 04:09:12 PM PDT 24 Apr 15 04:26:26 PM PDT 24 10768171846 ps
T451 /workspace/coverage/default/25.chip_sw_all_escalation_resets.3650294442 Apr 15 04:15:55 PM PDT 24 Apr 15 04:25:49 PM PDT 24 4850714224 ps
T541 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1161012504 Apr 15 04:06:14 PM PDT 24 Apr 15 04:18:00 PM PDT 24 3505766420 ps
T399 /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.3784941560 Apr 15 03:45:46 PM PDT 24 Apr 15 03:51:13 PM PDT 24 2858184955 ps
T542 /workspace/coverage/default/2.chip_sw_hmac_enc.775527983 Apr 15 04:07:04 PM PDT 24 Apr 15 04:12:29 PM PDT 24 2856136506 ps
T543 /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.3738691726 Apr 15 04:10:12 PM PDT 24 Apr 15 04:14:09 PM PDT 24 3292535372 ps
T487 /workspace/coverage/default/83.chip_sw_all_escalation_resets.414308 Apr 15 04:20:18 PM PDT 24 Apr 15 04:29:32 PM PDT 24 5290476706 ps
T325 /workspace/coverage/default/12.chip_sw_all_escalation_resets.4249230262 Apr 15 04:13:20 PM PDT 24 Apr 15 04:25:06 PM PDT 24 6200264088 ps
T411 /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3100885715 Apr 15 04:22:03 PM PDT 24 Apr 15 04:28:22 PM PDT 24 3577406992 ps
T408 /workspace/coverage/default/1.rom_volatile_raw_unlock.1493782195 Apr 15 04:00:16 PM PDT 24 Apr 15 04:02:16 PM PDT 24 1930111929 ps
T544 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.4244006453 Apr 15 03:47:46 PM PDT 24 Apr 15 03:57:50 PM PDT 24 3895329440 ps
T129 /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.3447185702 Apr 15 04:01:16 PM PDT 24 Apr 15 04:08:03 PM PDT 24 5119433022 ps
T545 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.1086668207 Apr 15 03:45:44 PM PDT 24 Apr 15 03:49:06 PM PDT 24 3063502864 ps
T546 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.2911679507 Apr 15 04:01:09 PM PDT 24 Apr 15 04:11:50 PM PDT 24 4523992650 ps
T37 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.827645446 Apr 15 03:45:15 PM PDT 24 Apr 15 03:56:16 PM PDT 24 5809665458 ps
T91 /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.1198370508 Apr 15 03:42:49 PM PDT 24 Apr 15 03:50:09 PM PDT 24 3458980316 ps
T547 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.2793559105 Apr 15 03:47:44 PM PDT 24 Apr 15 04:03:59 PM PDT 24 6691520013 ps
T501 /workspace/coverage/default/94.chip_sw_all_escalation_resets.3720018656 Apr 15 04:20:59 PM PDT 24 Apr 15 04:29:59 PM PDT 24 5580711260 ps
T130 /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.560975022 Apr 15 04:01:19 PM PDT 24 Apr 15 04:10:41 PM PDT 24 5570807000 ps
T548 /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.3898204162 Apr 15 04:15:11 PM PDT 24 Apr 15 04:27:00 PM PDT 24 8580804597 ps
T424 /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.1520684577 Apr 15 04:14:06 PM PDT 24 Apr 15 04:20:36 PM PDT 24 3642939278 ps
T272 /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.2063346245 Apr 15 04:18:14 PM PDT 24 Apr 15 04:25:10 PM PDT 24 3581224892 ps
T190 /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.2813213431 Apr 15 03:49:49 PM PDT 24 Apr 15 05:28:06 PM PDT 24 49882308992 ps
T549 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.2417454977 Apr 15 03:51:00 PM PDT 24 Apr 15 03:59:44 PM PDT 24 6594518327 ps
T154 /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.3110094321 Apr 15 03:48:02 PM PDT 24 Apr 15 03:55:05 PM PDT 24 6203755256 ps
T550 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.3747892594 Apr 15 03:48:01 PM PDT 24 Apr 15 03:58:32 PM PDT 24 4188504299 ps
T551 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.564772869 Apr 15 03:57:03 PM PDT 24 Apr 15 04:07:35 PM PDT 24 4374679290 ps
T397 /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.2058212095 Apr 15 04:15:37 PM PDT 24 Apr 15 04:20:43 PM PDT 24 3246431432 ps
T552 /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.1237540024 Apr 15 03:51:47 PM PDT 24 Apr 15 04:48:54 PM PDT 24 14668807314 ps
T553 /workspace/coverage/default/4.chip_tap_straps_rma.1816165408 Apr 15 04:10:44 PM PDT 24 Apr 15 04:13:32 PM PDT 24 2574076318 ps
T403 /workspace/coverage/default/1.chip_sw_otbn_randomness.1103049203 Apr 15 03:51:11 PM PDT 24 Apr 15 04:07:25 PM PDT 24 6005745050 ps
T368 /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.2154715155 Apr 15 04:20:24 PM PDT 24 Apr 15 04:27:25 PM PDT 24 3891871786 ps
T371 /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.4280182637 Apr 15 04:18:18 PM PDT 24 Apr 15 04:23:19 PM PDT 24 3392361712 ps
T110 /workspace/coverage/default/1.chip_sw_kmac_app_rom.2823543857 Apr 15 03:55:35 PM PDT 24 Apr 15 03:58:42 PM PDT 24 2494344710 ps
T50 /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.1164103404 Apr 15 03:58:30 PM PDT 24 Apr 15 04:05:53 PM PDT 24 3715292262 ps
T372 /workspace/coverage/default/0.chip_sw_kmac_idle.3869843541 Apr 15 03:45:19 PM PDT 24 Apr 15 03:49:20 PM PDT 24 3243527456 ps
T263 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.2150200026 Apr 15 03:45:43 PM PDT 24 Apr 15 03:56:01 PM PDT 24 4073005736 ps
T373 /workspace/coverage/default/44.chip_sw_all_escalation_resets.1644070382 Apr 15 04:17:00 PM PDT 24 Apr 15 04:25:52 PM PDT 24 5309471420 ps
T133 /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.3370359244 Apr 15 04:05:57 PM PDT 24 Apr 15 04:19:28 PM PDT 24 7328350522 ps
T374 /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.1793745792 Apr 15 04:15:46 PM PDT 24 Apr 15 04:21:40 PM PDT 24 4129944736 ps
T375 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.1715566798 Apr 15 03:43:51 PM PDT 24 Apr 15 03:54:23 PM PDT 24 4036664720 ps
T273 /workspace/coverage/default/5.chip_sw_all_escalation_resets.621497867 Apr 15 04:11:53 PM PDT 24 Apr 15 04:25:41 PM PDT 24 4758156830 ps
T73 /workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.1593710583 Apr 15 03:59:19 PM PDT 24 Apr 15 04:41:38 PM PDT 24 18312119649 ps
T156 /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.2763056862 Apr 15 04:11:08 PM PDT 24 Apr 15 04:17:17 PM PDT 24 5050771818 ps
T554 /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.3684753166 Apr 15 03:51:19 PM PDT 24 Apr 15 04:08:52 PM PDT 24 6057219865 ps
T555 /workspace/coverage/default/0.chip_sival_flash_info_access.3437133393 Apr 15 03:45:16 PM PDT 24 Apr 15 03:50:58 PM PDT 24 3386155456 ps
T556 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.2018562490 Apr 15 04:08:26 PM PDT 24 Apr 15 04:15:49 PM PDT 24 3247133316 ps
T486 /workspace/coverage/default/19.chip_sw_all_escalation_resets.2810152080 Apr 15 04:14:23 PM PDT 24 Apr 15 04:24:44 PM PDT 24 4702780480 ps
T295 /workspace/coverage/default/3.chip_sw_data_integrity_escalation.375822792 Apr 15 04:10:37 PM PDT 24 Apr 15 04:22:35 PM PDT 24 5279639000 ps
T557 /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.4286322941 Apr 15 04:01:29 PM PDT 24 Apr 15 04:04:18 PM PDT 24 2188181376 ps
T558 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.881690540 Apr 15 04:04:20 PM PDT 24 Apr 15 04:09:18 PM PDT 24 2915945141 ps
T471 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.424486730 Apr 15 03:44:53 PM PDT 24 Apr 15 03:50:15 PM PDT 24 3589619516 ps
T191 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.1409987320 Apr 15 03:44:13 PM PDT 24 Apr 15 03:56:34 PM PDT 24 9075052312 ps
T559 /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.1351696469 Apr 15 03:43:07 PM PDT 24 Apr 15 03:49:47 PM PDT 24 6664782736 ps
T560 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.3313891694 Apr 15 03:51:37 PM PDT 24 Apr 15 04:15:04 PM PDT 24 9776478456 ps
T53 /workspace/coverage/default/2.chip_sw_sleep_pin_wake.2920227823 Apr 15 04:02:39 PM PDT 24 Apr 15 04:08:45 PM PDT 24 3459573800 ps
T561 /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.1207398131 Apr 15 03:51:18 PM PDT 24 Apr 15 04:05:15 PM PDT 24 8250716944 ps
T212 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.1273153404 Apr 15 04:04:06 PM PDT 24 Apr 15 04:28:11 PM PDT 24 7269217808 ps
T562 /workspace/coverage/default/0.chip_sw_hmac_smoketest.3584810519 Apr 15 03:48:11 PM PDT 24 Apr 15 03:53:11 PM PDT 24 3176772584 ps
T377 /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.769830151 Apr 15 03:45:49 PM PDT 24 Apr 15 03:50:20 PM PDT 24 2804358464 ps
T23 /workspace/coverage/default/0.chip_sw_usbdev_config_host.791949007 Apr 15 03:45:41 PM PDT 24 Apr 15 04:16:00 PM PDT 24 8467572558 ps
T223 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2093350 Apr 15 03:46:41 PM PDT 24 Apr 15 03:59:48 PM PDT 24 4165365580 ps
T563 /workspace/coverage/default/2.chip_sival_flash_info_access.3009702234 Apr 15 04:02:20 PM PDT 24 Apr 15 04:06:59 PM PDT 24 3476219012 ps
T564 /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.3445120931 Apr 15 03:44:50 PM PDT 24 Apr 15 03:52:36 PM PDT 24 4806056476 ps
T248 /workspace/coverage/default/70.chip_sw_all_escalation_resets.4265109040 Apr 15 04:19:23 PM PDT 24 Apr 15 04:26:20 PM PDT 24 4748084440 ps
T226 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.1856073596 Apr 15 03:48:29 PM PDT 24 Apr 15 03:59:53 PM PDT 24 4636902720 ps
T332 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.2071219163 Apr 15 03:49:46 PM PDT 24 Apr 15 04:02:12 PM PDT 24 4343498274 ps
T268 /workspace/coverage/default/1.chip_sw_gpio_smoketest.1770653232 Apr 15 04:00:37 PM PDT 24 Apr 15 04:04:37 PM PDT 24 2378258602 ps
T565 /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.1705690253 Apr 15 03:45:50 PM PDT 24 Apr 15 03:57:22 PM PDT 24 4270060960 ps
T566 /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.3674481441 Apr 15 04:16:00 PM PDT 24 Apr 15 04:22:38 PM PDT 24 4240303008 ps
T567 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1587761640 Apr 15 03:44:52 PM PDT 24 Apr 15 04:37:44 PM PDT 24 44411224056 ps
T143 /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.1549008865 Apr 15 04:05:21 PM PDT 24 Apr 15 04:16:55 PM PDT 24 9050378758 ps
T144 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.110305828 Apr 15 04:05:43 PM PDT 24 Apr 15 04:17:41 PM PDT 24 5340089960 ps
T324 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.3796792776 Apr 15 03:46:19 PM PDT 24 Apr 15 04:00:16 PM PDT 24 5448254260 ps
T148 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.756031789 Apr 15 03:45:28 PM PDT 24 Apr 15 04:07:34 PM PDT 24 10208167550 ps
T568 /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.1779035923 Apr 15 03:54:44 PM PDT 24 Apr 15 04:01:01 PM PDT 24 3365470248 ps
T569 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.1115895312 Apr 15 03:53:10 PM PDT 24 Apr 15 03:57:20 PM PDT 24 3317824511 ps
T333 /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.3746703920 Apr 15 04:13:34 PM PDT 24 Apr 15 04:34:06 PM PDT 24 7879530444 ps
T203 /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.28552671 Apr 15 03:45:04 PM PDT 24 Apr 15 03:50:08 PM PDT 24 2773286720 ps
T249 /workspace/coverage/default/38.chip_sw_all_escalation_resets.2779721613 Apr 15 04:16:11 PM PDT 24 Apr 15 04:25:29 PM PDT 24 4784488040 ps
T414 /workspace/coverage/default/61.chip_sw_all_escalation_resets.331580735 Apr 15 04:21:23 PM PDT 24 Apr 15 04:30:20 PM PDT 24 6141306420 ps
T570 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.543482208 Apr 15 04:01:00 PM PDT 24 Apr 15 04:21:06 PM PDT 24 7021596577 ps
T355 /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1221288666 Apr 15 03:44:52 PM PDT 24 Apr 15 03:56:16 PM PDT 24 18732373420 ps
T571 /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.2634876878 Apr 15 03:47:48 PM PDT 24 Apr 15 04:13:39 PM PDT 24 7356742918 ps
T572 /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.1431760993 Apr 15 04:09:38 PM PDT 24 Apr 15 04:30:02 PM PDT 24 5551287800 ps
T573 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.2382482562 Apr 15 04:02:48 PM PDT 24 Apr 15 04:21:05 PM PDT 24 10400580966 ps
T574 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.263866319 Apr 15 03:52:16 PM PDT 24 Apr 15 04:44:11 PM PDT 24 12373865644 ps
T79 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1833660650 Apr 15 04:00:16 PM PDT 24 Apr 15 04:07:42 PM PDT 24 5266608168 ps
T422 /workspace/coverage/default/97.chip_sw_all_escalation_resets.407866442 Apr 15 04:21:07 PM PDT 24 Apr 15 04:33:23 PM PDT 24 6302619280 ps
T467 /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.3628230903 Apr 15 04:18:13 PM PDT 24 Apr 15 04:26:01 PM PDT 24 3880043190 ps
T416 /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.389413272 Apr 15 04:14:44 PM PDT 24 Apr 15 04:21:29 PM PDT 24 3560156952 ps
T488 /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.718846608 Apr 15 04:18:07 PM PDT 24 Apr 15 04:24:05 PM PDT 24 3958226808 ps
T56 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.2404535288 Apr 15 04:07:42 PM PDT 24 Apr 15 04:34:42 PM PDT 24 22067844816 ps
T229 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.2684786995 Apr 15 03:45:51 PM PDT 24 Apr 15 05:31:11 PM PDT 24 48259492394 ps
T221 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.2666122041 Apr 15 03:49:42 PM PDT 24 Apr 15 04:03:18 PM PDT 24 5413581348 ps
T409 /workspace/coverage/default/2.rom_volatile_raw_unlock.4033297430 Apr 15 04:10:14 PM PDT 24 Apr 15 04:11:54 PM PDT 24 2409208133 ps
T40 /workspace/coverage/default/0.chip_sw_spi_device_tpm.1093788082 Apr 15 03:46:17 PM PDT 24 Apr 15 03:50:40 PM PDT 24 3432101870 ps
T575 /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.372294867 Apr 15 03:53:41 PM PDT 24 Apr 15 03:56:52 PM PDT 24 2366375510 ps
T576 /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.3699521859 Apr 15 04:07:43 PM PDT 24 Apr 15 04:18:40 PM PDT 24 5760777496 ps
T432 /workspace/coverage/default/89.chip_sw_all_escalation_resets.4164093821 Apr 15 04:21:17 PM PDT 24 Apr 15 04:30:26 PM PDT 24 4777508730 ps
T577 /workspace/coverage/default/2.chip_sw_uart_smoketest.2689035576 Apr 15 04:11:27 PM PDT 24 Apr 15 04:16:30 PM PDT 24 2921312734 ps
T472 /workspace/coverage/default/6.chip_sw_all_escalation_resets.3843679289 Apr 15 04:12:36 PM PDT 24 Apr 15 04:21:44 PM PDT 24 5397824278 ps
T405 /workspace/coverage/default/2.chip_tap_straps_dev.1503144818 Apr 15 04:07:16 PM PDT 24 Apr 15 04:29:57 PM PDT 24 12865064616 ps
T578 /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.1714028393 Apr 15 04:03:07 PM PDT 24 Apr 15 04:09:59 PM PDT 24 6459412960 ps
T257 /workspace/coverage/default/1.chip_sw_power_sleep_load.1320601550 Apr 15 04:00:38 PM PDT 24 Apr 15 04:07:53 PM PDT 24 4130275170 ps
T579 /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.3313583711 Apr 15 04:03:48 PM PDT 24 Apr 15 04:56:34 PM PDT 24 16023937003 ps
T580 /workspace/coverage/default/0.chip_sw_alert_handler_escalation.1295816181 Apr 15 03:46:19 PM PDT 24 Apr 15 03:53:14 PM PDT 24 5694836550 ps
T80 /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.1082685307 Apr 15 04:12:27 PM PDT 24 Apr 15 04:22:34 PM PDT 24 5204765776 ps
T581 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.1160150132 Apr 15 04:04:49 PM PDT 24 Apr 15 04:10:23 PM PDT 24 3020650780 ps
T222 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.1543764171 Apr 15 04:03:40 PM PDT 24 Apr 15 04:18:21 PM PDT 24 4948535888 ps
T57 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3860669395 Apr 15 04:07:34 PM PDT 24 Apr 15 04:29:47 PM PDT 24 18477252626 ps
T342 /workspace/coverage/default/2.chip_sw_entropy_src_csrng.95246596 Apr 15 04:06:20 PM PDT 24 Apr 15 04:33:16 PM PDT 24 7246978350 ps
T103 /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2067472793 Apr 15 04:07:54 PM PDT 24 Apr 15 04:18:42 PM PDT 24 5379816510 ps
T582 /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.1494602171 Apr 15 04:15:49 PM PDT 24 Apr 15 04:25:59 PM PDT 24 4273208910 ps
T583 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.3222744424 Apr 15 03:44:55 PM PDT 24 Apr 15 03:54:53 PM PDT 24 7431286114 ps
T264 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.2682033291 Apr 15 03:44:19 PM PDT 24 Apr 15 03:56:15 PM PDT 24 3961972268 ps
T321 /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.4111930522 Apr 15 04:07:23 PM PDT 24 Apr 15 04:13:16 PM PDT 24 4008913600 ps
T280 /workspace/coverage/default/73.chip_sw_all_escalation_resets.1288698570 Apr 15 04:20:30 PM PDT 24 Apr 15 04:28:41 PM PDT 24 5141968408 ps
T584 /workspace/coverage/default/2.rom_e2e_asm_init_dev.1044203796 Apr 15 04:14:26 PM PDT 24 Apr 15 05:00:25 PM PDT 24 15107041914 ps
T358 /workspace/coverage/default/1.chip_sw_hmac_enc.2432733441 Apr 15 03:54:30 PM PDT 24 Apr 15 03:57:44 PM PDT 24 3123423198 ps
T296 /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.2019274222 Apr 15 03:52:06 PM PDT 24 Apr 15 04:02:13 PM PDT 24 4132236000 ps
T114 /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.1934465449 Apr 15 04:04:10 PM PDT 24 Apr 15 04:07:36 PM PDT 24 2765396380 ps
T585 /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.620493431 Apr 15 03:45:10 PM PDT 24 Apr 15 03:53:12 PM PDT 24 5058609440 ps
T338 /workspace/coverage/default/0.chip_sw_power_idle_load.1125583848 Apr 15 03:44:06 PM PDT 24 Apr 15 03:54:01 PM PDT 24 4135860344 ps
T586 /workspace/coverage/default/1.chip_sw_flash_ctrl_access.3357431665 Apr 15 03:48:32 PM PDT 24 Apr 15 04:05:12 PM PDT 24 5069150608 ps
T587 /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.1625443792 Apr 15 04:00:43 PM PDT 24 Apr 15 04:07:21 PM PDT 24 5345448764 ps
T588 /workspace/coverage/default/2.chip_sw_example_flash.361777160 Apr 15 04:00:58 PM PDT 24 Apr 15 04:03:48 PM PDT 24 2422483608 ps
T589 /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.4234658339 Apr 15 04:16:39 PM PDT 24 Apr 15 04:33:28 PM PDT 24 11834042120 ps
T590 /workspace/coverage/default/1.chip_tap_straps_dev.3827714438 Apr 15 03:57:56 PM PDT 24 Apr 15 04:00:54 PM PDT 24 3147998367 ps
T591 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1413349553 Apr 15 03:57:06 PM PDT 24 Apr 15 04:07:59 PM PDT 24 4446523252 ps
T592 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1266578603 Apr 15 03:50:41 PM PDT 24 Apr 15 04:40:53 PM PDT 24 12385633058 ps
T593 /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.2261578702 Apr 15 04:14:02 PM PDT 24 Apr 15 04:35:42 PM PDT 24 7988318362 ps
T594 /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.2851469768 Apr 15 04:13:20 PM PDT 24 Apr 15 04:25:08 PM PDT 24 6632038913 ps
T84 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.73948822 Apr 15 04:07:20 PM PDT 24 Apr 15 04:14:43 PM PDT 24 5756908144 ps
T430 /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.1123752196 Apr 15 04:18:45 PM PDT 24 Apr 15 04:25:18 PM PDT 24 4137276288 ps
T258 /workspace/coverage/default/1.chip_sw_plic_sw_irq.3242554566 Apr 15 04:00:56 PM PDT 24 Apr 15 04:04:26 PM PDT 24 3403092000 ps
T595 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3567603841 Apr 15 04:03:40 PM PDT 24 Apr 15 04:23:58 PM PDT 24 7744934636 ps
T336 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.2182840129 Apr 15 03:45:00 PM PDT 24 Apr 15 03:55:38 PM PDT 24 4939968567 ps
T231 /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.3152721838 Apr 15 03:47:56 PM PDT 24 Apr 15 05:14:36 PM PDT 24 46339604040 ps
T265 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.189381332 Apr 15 04:11:49 PM PDT 24 Apr 15 04:23:34 PM PDT 24 4075832720 ps
T596 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.222039835 Apr 15 03:50:48 PM PDT 24 Apr 15 04:25:25 PM PDT 24 19353860190 ps
T492 /workspace/coverage/default/67.chip_sw_all_escalation_resets.2408085663 Apr 15 04:21:31 PM PDT 24 Apr 15 04:30:32 PM PDT 24 5573902780 ps
T597 /workspace/coverage/default/1.rom_e2e_asm_init_prod.1963406971 Apr 15 04:03:30 PM PDT 24 Apr 15 05:02:56 PM PDT 24 15678685928 ps
T598 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.1673006293 Apr 15 03:48:31 PM PDT 24 Apr 15 04:09:31 PM PDT 24 8272191200 ps
T599 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3275090086 Apr 15 03:50:00 PM PDT 24 Apr 15 04:50:25 PM PDT 24 31524891962 ps
T600 /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.789706119 Apr 15 03:45:46 PM PDT 24 Apr 15 07:22:16 PM PDT 24 76983218392 ps
T426 /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.430657952 Apr 15 04:20:50 PM PDT 24 Apr 15 04:26:25 PM PDT 24 3889606104 ps
T340 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.1061561940 Apr 15 03:46:19 PM PDT 24 Apr 15 03:54:35 PM PDT 24 4228056838 ps
T419 /workspace/coverage/default/84.chip_sw_all_escalation_resets.2084458952 Apr 15 04:22:19 PM PDT 24 Apr 15 04:32:27 PM PDT 24 5709886874 ps
T281 /workspace/coverage/default/16.chip_sw_all_escalation_resets.3577125548 Apr 15 04:13:29 PM PDT 24 Apr 15 04:23:37 PM PDT 24 5829675008 ps
T601 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3407462700 Apr 15 04:06:12 PM PDT 24 Apr 15 04:17:04 PM PDT 24 4913497576 ps
T602 /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.1236718915 Apr 15 04:10:09 PM PDT 24 Apr 15 04:18:37 PM PDT 24 4804475400 ps
T423 /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.4197519567 Apr 15 04:18:39 PM PDT 24 Apr 15 04:23:07 PM PDT 24 3099650360 ps
T603 /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.2141907679 Apr 15 04:00:07 PM PDT 24 Apr 15 04:03:47 PM PDT 24 2514708240 ps
T477 /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1432403698 Apr 15 04:16:38 PM PDT 24 Apr 15 04:22:17 PM PDT 24 3158114934 ps
T427 /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.2345835077 Apr 15 04:17:10 PM PDT 24 Apr 15 04:24:33 PM PDT 24 3967062584 ps
T158 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.3912398393 Apr 15 03:54:32 PM PDT 24 Apr 15 04:15:40 PM PDT 24 9473539256 ps
T291 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.128380280 Apr 15 03:52:58 PM PDT 24 Apr 15 04:48:46 PM PDT 24 14464865036 ps
T604 /workspace/coverage/default/0.chip_sw_flash_ctrl_access.2480082909 Apr 15 03:43:44 PM PDT 24 Apr 15 03:58:26 PM PDT 24 5974043060 ps
T605 /workspace/coverage/default/2.chip_sw_example_manufacturer.2540055502 Apr 15 03:59:59 PM PDT 24 Apr 15 04:03:25 PM PDT 24 2858057896 ps
T326 /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.2410413691 Apr 15 04:15:44 PM PDT 24 Apr 15 04:20:53 PM PDT 24 3641948648 ps
T606 /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.2544597302 Apr 15 04:02:45 PM PDT 24 Apr 15 04:37:51 PM PDT 24 9920079847 ps
T484 /workspace/coverage/default/79.chip_sw_all_escalation_resets.2776842832 Apr 15 04:23:18 PM PDT 24 Apr 15 04:32:55 PM PDT 24 4950817704 ps
T456 /workspace/coverage/default/51.chip_sw_all_escalation_resets.4037355527 Apr 15 04:18:19 PM PDT 24 Apr 15 04:27:41 PM PDT 24 5681791040 ps
T607 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.1122782271 Apr 15 03:59:01 PM PDT 24 Apr 15 04:29:54 PM PDT 24 11295954705 ps
T193 /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.2285350776 Apr 15 03:46:00 PM PDT 24 Apr 15 03:49:00 PM PDT 24 3758983496 ps
T429 /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.2504711989 Apr 15 04:17:33 PM PDT 24 Apr 15 04:25:16 PM PDT 24 4127605296 ps
T608 /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.2124644427 Apr 15 04:01:01 PM PDT 24 Apr 15 04:11:56 PM PDT 24 5248987616 ps
T245 /workspace/coverage/default/0.chip_sw_alert_handler_entropy.3241966268 Apr 15 03:47:49 PM PDT 24 Apr 15 03:53:41 PM PDT 24 3910457164 ps
T609 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.649430176 Apr 15 03:44:28 PM PDT 24 Apr 15 03:58:03 PM PDT 24 8551379128 ps
T610 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.126856448 Apr 15 03:51:02 PM PDT 24 Apr 15 04:03:10 PM PDT 24 4241978480 ps
T82 /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1821261634 Apr 15 03:56:15 PM PDT 24 Apr 15 04:13:00 PM PDT 24 8241384980 ps
T611 /workspace/coverage/default/1.chip_sw_edn_sw_mode.530911871 Apr 15 03:52:45 PM PDT 24 Apr 15 04:17:25 PM PDT 24 6247096296 ps
T612 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.4098835629 Apr 15 03:58:45 PM PDT 24 Apr 15 04:03:02 PM PDT 24 3015996421 ps
T613 /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.1052952418 Apr 15 03:47:07 PM PDT 24 Apr 15 03:50:55 PM PDT 24 3200940152 ps
T614 /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.200598173 Apr 15 03:49:42 PM PDT 24 Apr 15 03:56:35 PM PDT 24 3383523224 ps
T255 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.3094104370 Apr 15 03:44:31 PM PDT 24 Apr 15 03:49:09 PM PDT 24 2820897690 ps
T350 /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.4147995724 Apr 15 03:46:28 PM PDT 24 Apr 15 03:52:03 PM PDT 24 3392552608 ps
T406 /workspace/coverage/default/3.chip_tap_straps_dev.4018666656 Apr 15 04:11:50 PM PDT 24 Apr 15 04:27:27 PM PDT 24 9330894562 ps
T393 /workspace/coverage/default/2.chip_sw_power_idle_load.1552448552 Apr 15 04:07:33 PM PDT 24 Apr 15 04:19:04 PM PDT 24 4771597542 ps
T615 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1598552660 Apr 15 04:11:26 PM PDT 24 Apr 15 04:32:20 PM PDT 24 7431931266 ps
T616 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.4148142955 Apr 15 04:04:15 PM PDT 24 Apr 15 04:13:40 PM PDT 24 7237989270 ps
T617 /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.1637612096 Apr 15 04:04:34 PM PDT 24 Apr 15 04:12:35 PM PDT 24 4947633720 ps
T438 /workspace/coverage/default/29.chip_sw_all_escalation_resets.2527585076 Apr 15 04:14:39 PM PDT 24 Apr 15 04:22:12 PM PDT 24 4239220728 ps
T618 /workspace/coverage/default/1.chip_sw_hmac_smoketest.2868275177 Apr 15 03:59:45 PM PDT 24 Apr 15 04:05:55 PM PDT 24 3320862804 ps
T619 /workspace/coverage/default/2.chip_sw_flash_ctrl_access.4114001442 Apr 15 04:04:24 PM PDT 24 Apr 15 04:23:15 PM PDT 24 5724040070 ps
T620 /workspace/coverage/default/1.chip_sw_aes_enc.463462485 Apr 15 03:53:56 PM PDT 24 Apr 15 03:57:48 PM PDT 24 2653983356 ps
T621 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.2597273330 Apr 15 04:03:56 PM PDT 24 Apr 15 04:14:11 PM PDT 24 6128466216 ps
T622 /workspace/coverage/default/0.chip_sw_example_flash.472930623 Apr 15 03:46:38 PM PDT 24 Apr 15 03:50:21 PM PDT 24 3198149294 ps
T382 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3815798069 Apr 15 03:46:11 PM PDT 24 Apr 15 04:53:38 PM PDT 24 25063420616 ps
T623 /workspace/coverage/default/1.chip_sw_aes_masking_off.1015194067 Apr 15 03:52:17 PM PDT 24 Apr 15 03:57:00 PM PDT 24 2609079217 ps
T624 /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.3761934437 Apr 15 03:46:01 PM PDT 24 Apr 15 04:06:35 PM PDT 24 7379817304 ps
T625 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.2227828010 Apr 15 03:52:16 PM PDT 24 Apr 15 04:41:25 PM PDT 24 12545152810 ps
T626 /workspace/coverage/default/2.chip_sw_gpio_smoketest.1260615422 Apr 15 04:09:48 PM PDT 24 Apr 15 04:15:15 PM PDT 24 2984329685 ps
T441 /workspace/coverage/default/57.chip_sw_all_escalation_resets.963709135 Apr 15 04:19:13 PM PDT 24 Apr 15 04:29:00 PM PDT 24 4596639178 ps
T457 /workspace/coverage/default/66.chip_sw_all_escalation_resets.349675264 Apr 15 04:19:55 PM PDT 24 Apr 15 04:30:54 PM PDT 24 5224833408 ps
T627 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.3058580355 Apr 15 04:04:43 PM PDT 24 Apr 15 04:27:32 PM PDT 24 5923444030 ps
T628 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1788708204 Apr 15 04:07:03 PM PDT 24 Apr 15 04:17:03 PM PDT 24 5539564700 ps
T359 /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.1882628770 Apr 15 04:04:29 PM PDT 24 Apr 15 04:21:49 PM PDT 24 4131147688 ps
T629 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.94889532 Apr 15 04:03:03 PM PDT 24 Apr 15 04:10:57 PM PDT 24 5074526925 ps
T58 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.2289383901 Apr 15 03:59:47 PM PDT 24 Apr 15 04:27:45 PM PDT 24 22048168632 ps
T630 /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.727337903 Apr 15 04:11:19 PM PDT 24 Apr 15 04:16:40 PM PDT 24 2715873704 ps
T631 /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.448415207 Apr 15 04:13:55 PM PDT 24 Apr 15 04:43:12 PM PDT 24 8101657400 ps
T460 /workspace/coverage/default/26.chip_sw_all_escalation_resets.1251097235 Apr 15 04:14:12 PM PDT 24 Apr 15 04:24:04 PM PDT 24 5455291868 ps
T448 /workspace/coverage/default/4.chip_sw_all_escalation_resets.688906403 Apr 15 04:11:11 PM PDT 24 Apr 15 04:22:10 PM PDT 24 4698064540 ps
T224 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.793835959 Apr 15 04:02:09 PM PDT 24 Apr 15 04:13:41 PM PDT 24 4752282008 ps
T199 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.3947434949 Apr 15 03:49:13 PM PDT 24 Apr 15 03:59:28 PM PDT 24 4504497670 ps
T313 /workspace/coverage/default/2.chip_sw_power_sleep_load.2975103779 Apr 15 04:10:53 PM PDT 24 Apr 15 04:20:46 PM PDT 24 10144878680 ps
T200 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.1679031705 Apr 15 04:05:59 PM PDT 24 Apr 15 04:17:56 PM PDT 24 8182829674 ps
T632 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2738192636 Apr 15 04:11:05 PM PDT 24 Apr 15 04:20:18 PM PDT 24 4089304295 ps
T633 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.2180008339 Apr 15 03:52:19 PM PDT 24 Apr 15 04:28:47 PM PDT 24 8669919160 ps
T634 /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.3528499560 Apr 15 04:03:09 PM PDT 24 Apr 15 04:07:07 PM PDT 24 2419189938 ps
T51 /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.2621481213 Apr 15 03:49:02 PM PDT 24 Apr 15 03:58:25 PM PDT 24 5227919264 ps
T635 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2602164310 Apr 15 03:59:50 PM PDT 24 Apr 15 04:10:43 PM PDT 24 4643628188 ps
T385 /workspace/coverage/default/2.chip_sw_edn_auto_mode.39868596 Apr 15 04:06:09 PM PDT 24 Apr 15 04:24:39 PM PDT 24 4173340650 ps
T636 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.3763619094 Apr 15 04:06:54 PM PDT 24 Apr 15 04:10:57 PM PDT 24 3435198656 ps
T637 /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.186315739 Apr 15 04:12:07 PM PDT 24 Apr 15 04:23:23 PM PDT 24 5728130423 ps
T638 /workspace/coverage/default/1.rom_e2e_asm_init_dev.1867572593 Apr 15 04:04:59 PM PDT 24 Apr 15 05:05:55 PM PDT 24 15229830506 ps
T54 /workspace/coverage/default/0.chip_sw_sleep_pin_wake.334064599 Apr 15 03:44:47 PM PDT 24 Apr 15 03:50:46 PM PDT 24 3085990018 ps
T639 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.3004527077 Apr 15 03:54:45 PM PDT 24 Apr 15 03:58:56 PM PDT 24 2952291244 ps
T458 /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.842430367 Apr 15 04:13:40 PM PDT 24 Apr 15 04:19:45 PM PDT 24 3798325496 ps
T640 /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.3362435565 Apr 15 03:42:57 PM PDT 24 Apr 15 03:58:55 PM PDT 24 12041449966 ps
T482 /workspace/coverage/default/78.chip_sw_all_escalation_resets.965003208 Apr 15 04:23:03 PM PDT 24 Apr 15 04:32:16 PM PDT 24 6239964152 ps
T312 /workspace/coverage/default/1.chip_sw_pattgen_ios.2008321843 Apr 15 03:48:44 PM PDT 24 Apr 15 03:53:04 PM PDT 24 2887436320 ps
T641 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.4094502738 Apr 15 03:51:59 PM PDT 24 Apr 15 04:39:25 PM PDT 24 15147451664 ps
T483 /workspace/coverage/default/74.chip_sw_all_escalation_resets.3106297137 Apr 15 04:19:40 PM PDT 24 Apr 15 04:28:01 PM PDT 24 5199946624 ps
T642 /workspace/coverage/default/1.chip_sw_rv_timer_irq.3137407097 Apr 15 03:50:23 PM PDT 24 Apr 15 03:55:17 PM PDT 24 2445374270 ps
T643 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.1179075589 Apr 15 04:00:28 PM PDT 24 Apr 15 04:15:05 PM PDT 24 9715550965 ps
T644 /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.2472386113 Apr 15 03:53:09 PM PDT 24 Apr 15 04:09:36 PM PDT 24 5876565610 ps
T386 /workspace/coverage/default/1.chip_sw_edn_auto_mode.4106262450 Apr 15 03:57:45 PM PDT 24 Apr 15 04:19:10 PM PDT 24 4269190888 ps
T645 /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.969525786 Apr 15 04:13:24 PM PDT 24 Apr 15 04:22:06 PM PDT 24 4067669216 ps
T233 /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.3668169719 Apr 15 03:44:40 PM PDT 24 Apr 15 05:16:16 PM PDT 24 45278494125 ps
T646 /workspace/coverage/default/1.chip_sw_uart_tx_rx.1221823070 Apr 15 03:49:33 PM PDT 24 Apr 15 04:02:19 PM PDT 24 4812309840 ps
T495 /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.763914620 Apr 15 04:21:04 PM PDT 24 Apr 15 04:28:07 PM PDT 24 4013512976 ps
T647 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.470421886 Apr 15 03:59:49 PM PDT 24 Apr 15 04:10:09 PM PDT 24 8386352968 ps
T450 /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3802770660 Apr 15 04:23:16 PM PDT 24 Apr 15 04:29:39 PM PDT 24 3554996930 ps
T90 /workspace/coverage/default/2.chip_tap_straps_rma.2150105466 Apr 15 04:06:48 PM PDT 24 Apr 15 04:17:45 PM PDT 24 7064000153 ps
T648 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.903651503 Apr 15 03:45:11 PM PDT 24 Apr 15 03:53:48 PM PDT 24 7408744160 ps
T649 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3013832525 Apr 15 04:00:54 PM PDT 24 Apr 15 04:09:24 PM PDT 24 4153365450 ps
T282 /workspace/coverage/default/98.chip_sw_all_escalation_resets.3703997525 Apr 15 04:22:04 PM PDT 24 Apr 15 04:30:20 PM PDT 24 5270652688 ps
T194 /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.2111979164 Apr 15 03:46:46 PM PDT 24 Apr 15 03:49:31 PM PDT 24 3484705312 ps
T650 /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.2132063059 Apr 15 04:06:06 PM PDT 24 Apr 15 04:15:12 PM PDT 24 4744961500 ps
T504 /workspace/coverage/default/58.chip_sw_all_escalation_resets.3437250264 Apr 15 04:18:35 PM PDT 24 Apr 15 04:27:42 PM PDT 24 5511777896 ps
T493 /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3582822062 Apr 15 04:14:33 PM PDT 24 Apr 15 04:22:44 PM PDT 24 3722200818 ps
T651 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.4214342313 Apr 15 03:48:30 PM PDT 24 Apr 15 03:51:54 PM PDT 24 3142017939 ps
T26 /workspace/coverage/default/2.chip_sw_gpio.1810050452 Apr 15 04:01:46 PM PDT 24 Apr 15 04:11:19 PM PDT 24 3479418016 ps
T652 /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.2403217579 Apr 15 04:00:59 PM PDT 24 Apr 15 04:03:55 PM PDT 24 2856919304 ps
T653 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.2904418387 Apr 15 03:52:32 PM PDT 24 Apr 15 04:28:16 PM PDT 24 9075768900 ps
T654 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.1080112117 Apr 15 03:48:18 PM PDT 24 Apr 15 03:53:25 PM PDT 24 3238132309 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%