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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
88.96 89.80 79.30 90.01 91.93 97.38 85.31


Total test records in report: 954
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T232 /workspace/coverage/default/1.chip_sw_flash_init.1668711119 Apr 15 03:47:50 PM PDT 24 Apr 15 04:25:48 PM PDT 24 21498096700 ps
T421 /workspace/coverage/default/95.chip_sw_all_escalation_resets.3277103867 Apr 15 04:21:53 PM PDT 24 Apr 15 04:30:29 PM PDT 24 5384556024 ps
T655 /workspace/coverage/default/2.chip_sw_kmac_idle.3794496061 Apr 15 04:06:32 PM PDT 24 Apr 15 04:10:33 PM PDT 24 2458865906 ps
T60 /workspace/coverage/default/0.chip_jtag_mem_access.1860427621 Apr 15 03:36:39 PM PDT 24 Apr 15 03:57:29 PM PDT 24 13751945693 ps
T656 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.4181284569 Apr 15 03:44:13 PM PDT 24 Apr 15 03:55:08 PM PDT 24 3783070324 ps
T657 /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.3332314800 Apr 15 03:56:17 PM PDT 24 Apr 15 04:42:59 PM PDT 24 29627559434 ps
T658 /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.1630793419 Apr 15 04:17:34 PM PDT 24 Apr 15 05:11:42 PM PDT 24 15265858561 ps
T659 /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.1149758287 Apr 15 03:45:06 PM PDT 24 Apr 15 05:10:29 PM PDT 24 44774439320 ps
T660 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.580191108 Apr 15 03:51:22 PM PDT 24 Apr 15 04:08:46 PM PDT 24 11781124724 ps
T52 /workspace/coverage/default/0.chip_jtag_csr_rw.2070800614 Apr 15 03:36:35 PM PDT 24 Apr 15 04:05:26 PM PDT 24 12250529706 ps
T661 /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.816151341 Apr 15 03:46:24 PM PDT 24 Apr 15 03:52:38 PM PDT 24 3614049510 ps
T24 /workspace/coverage/default/0.chip_sw_usbdev_pincfg.4249002548 Apr 15 03:43:39 PM PDT 24 Apr 15 05:38:51 PM PDT 24 31612271530 ps
T662 /workspace/coverage/default/15.chip_sw_all_escalation_resets.1345498306 Apr 15 04:13:34 PM PDT 24 Apr 15 04:23:51 PM PDT 24 5257144760 ps
T297 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3070450919 Apr 15 04:10:43 PM PDT 24 Apr 15 04:21:49 PM PDT 24 4877427272 ps
T412 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.418316246 Apr 15 03:55:58 PM PDT 24 Apr 15 04:03:01 PM PDT 24 3406293160 ps
T439 /workspace/coverage/default/59.chip_sw_all_escalation_resets.778192753 Apr 15 04:19:18 PM PDT 24 Apr 15 04:30:42 PM PDT 24 4619082856 ps
T489 /workspace/coverage/default/20.chip_sw_all_escalation_resets.964274778 Apr 15 04:14:32 PM PDT 24 Apr 15 04:26:44 PM PDT 24 5412957040 ps
T663 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.3614900780 Apr 15 03:48:21 PM PDT 24 Apr 15 03:58:20 PM PDT 24 4463692452 ps
T664 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.2374918219 Apr 15 04:00:48 PM PDT 24 Apr 15 04:11:05 PM PDT 24 4045659470 ps
T665 /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.3338744035 Apr 15 03:50:33 PM PDT 24 Apr 15 04:01:13 PM PDT 24 5411002364 ps
T666 /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.2666949941 Apr 15 03:56:51 PM PDT 24 Apr 15 04:05:38 PM PDT 24 10013905868 ps
T468 /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.382172161 Apr 15 04:16:43 PM PDT 24 Apr 15 04:22:18 PM PDT 24 3732462636 ps
T667 /workspace/coverage/default/2.chip_sw_kmac_smoketest.1594996329 Apr 15 04:09:52 PM PDT 24 Apr 15 04:15:28 PM PDT 24 3225056534 ps
T668 /workspace/coverage/default/62.chip_sw_all_escalation_resets.1365411598 Apr 15 04:19:12 PM PDT 24 Apr 15 04:27:55 PM PDT 24 5712313712 ps
T669 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.4217925003 Apr 15 03:54:09 PM PDT 24 Apr 15 04:59:18 PM PDT 24 15179891510 ps
T670 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.3651231687 Apr 15 03:55:39 PM PDT 24 Apr 15 04:00:37 PM PDT 24 3373202903 ps
T494 /workspace/coverage/default/3.chip_sw_all_escalation_resets.3863583231 Apr 15 04:10:55 PM PDT 24 Apr 15 04:22:08 PM PDT 24 4693375224 ps
T363 /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.4087099608 Apr 15 04:04:36 PM PDT 24 Apr 15 04:28:27 PM PDT 24 11481321816 ps
T440 /workspace/coverage/default/63.chip_sw_all_escalation_resets.1244640535 Apr 15 04:19:30 PM PDT 24 Apr 15 04:29:08 PM PDT 24 5079561616 ps
T506 /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.239912192 Apr 15 04:20:43 PM PDT 24 Apr 15 04:27:18 PM PDT 24 3967912968 ps
T671 /workspace/coverage/default/1.chip_sw_hmac_enc_idle.4238876423 Apr 15 03:54:34 PM PDT 24 Apr 15 03:59:07 PM PDT 24 3080742728 ps
T298 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1102095998 Apr 15 03:58:09 PM PDT 24 Apr 15 04:06:18 PM PDT 24 4348875680 ps
T672 /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.345767564 Apr 15 04:00:29 PM PDT 24 Apr 15 04:09:31 PM PDT 24 4251682180 ps
T446 /workspace/coverage/default/10.chip_sw_all_escalation_resets.4284676702 Apr 15 04:13:28 PM PDT 24 Apr 15 04:21:48 PM PDT 24 4560378640 ps
T673 /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.2988933186 Apr 15 04:04:27 PM PDT 24 Apr 15 04:12:51 PM PDT 24 5344266116 ps
T104 /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2602038691 Apr 15 03:44:49 PM PDT 24 Apr 15 03:52:14 PM PDT 24 5220667300 ps
T674 /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.3821695288 Apr 15 04:01:01 PM PDT 24 Apr 15 04:05:18 PM PDT 24 3868669426 ps
T303 /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.4069179519 Apr 15 03:46:10 PM PDT 24 Apr 15 03:51:24 PM PDT 24 2870663625 ps
T675 /workspace/coverage/default/0.chip_sw_edn_kat.1511072976 Apr 15 03:44:48 PM PDT 24 Apr 15 03:56:08 PM PDT 24 3345803544 ps
T676 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.4112685020 Apr 15 03:44:54 PM PDT 24 Apr 15 03:53:33 PM PDT 24 7119223064 ps
T677 /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.3914124352 Apr 15 04:12:54 PM PDT 24 Apr 15 04:20:01 PM PDT 24 5091309807 ps
T678 /workspace/coverage/default/0.chip_sw_otbn_randomness.1264995292 Apr 15 03:44:55 PM PDT 24 Apr 15 04:03:34 PM PDT 24 5893155160 ps
T679 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.355965315 Apr 15 03:45:59 PM PDT 24 Apr 15 03:52:22 PM PDT 24 4795762360 ps
T680 /workspace/coverage/default/0.chip_sw_kmac_entropy.3790262968 Apr 15 03:44:50 PM PDT 24 Apr 15 03:49:56 PM PDT 24 2592643040 ps
T681 /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.1450689225 Apr 15 04:03:19 PM PDT 24 Apr 15 04:12:57 PM PDT 24 6726939170 ps
T402 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.2025274701 Apr 15 04:03:01 PM PDT 24 Apr 15 05:01:15 PM PDT 24 19003332114 ps
T274 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.3583573461 Apr 15 03:55:09 PM PDT 24 Apr 15 05:10:41 PM PDT 24 18924091130 ps
T682 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.2692242905 Apr 15 03:55:09 PM PDT 24 Apr 15 04:59:59 PM PDT 24 17535070069 ps
T683 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.2664518036 Apr 15 04:04:12 PM PDT 24 Apr 15 04:06:23 PM PDT 24 2730653568 ps
T299 /workspace/coverage/default/2.chip_sw_data_integrity_escalation.3493605056 Apr 15 04:00:43 PM PDT 24 Apr 15 04:12:47 PM PDT 24 4918992472 ps
T479 /workspace/coverage/default/64.chip_sw_all_escalation_resets.2645836402 Apr 15 04:20:45 PM PDT 24 Apr 15 04:31:14 PM PDT 24 5358028654 ps
T684 /workspace/coverage/default/0.chip_tap_straps_testunlock0.778442028 Apr 15 03:45:33 PM PDT 24 Apr 15 03:54:38 PM PDT 24 5736822919 ps
T227 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.3355789761 Apr 15 03:44:56 PM PDT 24 Apr 15 03:58:12 PM PDT 24 4317847998 ps
T485 /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2133725349 Apr 15 04:21:11 PM PDT 24 Apr 15 04:28:19 PM PDT 24 3513408818 ps
T234 /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.237111824 Apr 15 03:50:54 PM PDT 24 Apr 15 05:14:18 PM PDT 24 48695337871 ps
T685 /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.687379923 Apr 15 04:02:32 PM PDT 24 Apr 15 05:27:13 PM PDT 24 42664141304 ps
T81 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1783014475 Apr 15 04:06:26 PM PDT 24 Apr 15 04:14:49 PM PDT 24 5541049700 ps
T455 /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.1461201208 Apr 15 04:21:00 PM PDT 24 Apr 15 04:27:27 PM PDT 24 3471816880 ps
T452 /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3709534608 Apr 15 04:23:19 PM PDT 24 Apr 15 04:30:03 PM PDT 24 3540117800 ps
T686 /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.450893270 Apr 15 04:00:22 PM PDT 24 Apr 15 04:04:28 PM PDT 24 2523456056 ps
T687 /workspace/coverage/default/0.chip_sw_usbdev_setuprx.4155520825 Apr 15 03:44:31 PM PDT 24 Apr 15 03:52:39 PM PDT 24 3865959366 ps
T688 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.4172472886 Apr 15 03:51:25 PM PDT 24 Apr 15 05:12:09 PM PDT 24 18550524930 ps
T348 /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.1915038133 Apr 15 03:50:08 PM PDT 24 Apr 15 03:58:00 PM PDT 24 3077812356 ps
T689 /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.2980023448 Apr 15 04:00:43 PM PDT 24 Apr 15 04:26:46 PM PDT 24 8386482400 ps
T690 /workspace/coverage/default/1.chip_sw_kmac_idle.3537136169 Apr 15 03:56:24 PM PDT 24 Apr 15 04:01:09 PM PDT 24 3570430606 ps
T691 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.2377525983 Apr 15 04:07:23 PM PDT 24 Apr 15 04:11:53 PM PDT 24 2403139976 ps
T692 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.301956933 Apr 15 03:44:34 PM PDT 24 Apr 15 03:54:03 PM PDT 24 4575072640 ps
T464 /workspace/coverage/default/11.chip_sw_all_escalation_resets.1746486119 Apr 15 04:12:57 PM PDT 24 Apr 15 04:23:10 PM PDT 24 5488723832 ps
T237 /workspace/coverage/default/0.chip_sw_flash_init.476548573 Apr 15 03:43:25 PM PDT 24 Apr 15 04:16:01 PM PDT 24 15215903378 ps
T693 /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3470419110 Apr 15 03:52:42 PM PDT 24 Apr 15 07:28:38 PM PDT 24 254834916120 ps
T694 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.877738809 Apr 15 03:51:05 PM PDT 24 Apr 15 04:58:49 PM PDT 24 19185997360 ps
T38 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1193208986 Apr 15 04:02:47 PM PDT 24 Apr 15 04:12:10 PM PDT 24 5710354976 ps
T381 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.925631091 Apr 15 03:56:00 PM PDT 24 Apr 15 04:14:12 PM PDT 24 4790175060 ps
T695 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.2041266934 Apr 15 03:52:11 PM PDT 24 Apr 15 04:07:01 PM PDT 24 7337598250 ps
T238 /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.4062308985 Apr 15 03:58:11 PM PDT 24 Apr 15 04:39:31 PM PDT 24 26712774107 ps
T696 /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.3311372243 Apr 15 03:44:28 PM PDT 24 Apr 15 03:51:01 PM PDT 24 4446557100 ps
T697 /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.741542911 Apr 15 04:01:04 PM PDT 24 Apr 15 04:05:23 PM PDT 24 2311303170 ps
T698 /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.3857973522 Apr 15 03:43:33 PM PDT 24 Apr 15 04:09:53 PM PDT 24 10781405880 ps
T278 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.1562135717 Apr 15 04:04:32 PM PDT 24 Apr 15 04:30:44 PM PDT 24 12202401624 ps
T699 /workspace/coverage/default/0.chip_sw_example_rom.3560681736 Apr 15 03:43:51 PM PDT 24 Apr 15 03:45:52 PM PDT 24 2607890630 ps
T700 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.3236140297 Apr 15 03:52:21 PM PDT 24 Apr 15 03:54:11 PM PDT 24 2403720309 ps
T415 /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.1307348308 Apr 15 04:17:31 PM PDT 24 Apr 15 04:24:06 PM PDT 24 3925710296 ps
T184 /workspace/coverage/default/37.chip_sw_all_escalation_resets.4086257301 Apr 15 04:16:03 PM PDT 24 Apr 15 04:24:12 PM PDT 24 4621131200 ps
T701 /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.2949305039 Apr 15 04:09:29 PM PDT 24 Apr 15 04:18:08 PM PDT 24 5491412760 ps
T702 /workspace/coverage/default/3.chip_tap_straps_prod.2895040669 Apr 15 04:12:15 PM PDT 24 Apr 15 04:32:47 PM PDT 24 11357417163 ps
T703 /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.2037443461 Apr 15 04:14:43 PM PDT 24 Apr 15 04:29:55 PM PDT 24 11020717273 ps
T704 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2338471559 Apr 15 04:11:30 PM PDT 24 Apr 15 04:28:26 PM PDT 24 8307100974 ps
T705 /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.937808696 Apr 15 03:51:33 PM PDT 24 Apr 15 04:56:57 PM PDT 24 15107409056 ps
T706 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.1025658704 Apr 15 03:52:25 PM PDT 24 Apr 15 04:16:04 PM PDT 24 6344671960 ps
T180 /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.1368679260 Apr 15 03:51:47 PM PDT 24 Apr 15 03:55:00 PM PDT 24 2595060140 ps
T707 /workspace/coverage/default/1.chip_sw_flash_crash_alert.3872857023 Apr 15 03:57:47 PM PDT 24 Apr 15 04:08:20 PM PDT 24 5890126548 ps
T708 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.3429204451 Apr 15 03:48:18 PM PDT 24 Apr 15 04:34:00 PM PDT 24 16165515290 ps
T709 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2348811438 Apr 15 04:06:52 PM PDT 24 Apr 15 04:11:13 PM PDT 24 2914848490 ps
T710 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.1373876843 Apr 15 03:53:53 PM PDT 24 Apr 15 04:58:41 PM PDT 24 17402139824 ps
T711 /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.3886829298 Apr 15 03:50:46 PM PDT 24 Apr 15 03:57:46 PM PDT 24 5026547756 ps
T712 /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.2744624901 Apr 15 04:04:12 PM PDT 24 Apr 15 04:09:19 PM PDT 24 2796994861 ps
T713 /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.1449601069 Apr 15 03:46:55 PM PDT 24 Apr 15 03:52:40 PM PDT 24 3175720904 ps
T714 /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.443564524 Apr 15 03:49:03 PM PDT 24 Apr 15 04:28:02 PM PDT 24 33571419224 ps
T715 /workspace/coverage/default/1.chip_sw_aes_smoketest.3458449819 Apr 15 04:02:08 PM PDT 24 Apr 15 04:05:40 PM PDT 24 2375090700 ps
T387 /workspace/coverage/default/0.chip_sw_edn_auto_mode.205991273 Apr 15 03:43:25 PM PDT 24 Apr 15 04:03:40 PM PDT 24 5561150120 ps
T716 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.2198739107 Apr 15 03:53:34 PM PDT 24 Apr 15 04:22:35 PM PDT 24 8527016008 ps
T481 /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1523452099 Apr 15 04:19:39 PM PDT 24 Apr 15 04:24:28 PM PDT 24 3442679848 ps
T717 /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.410112421 Apr 15 04:12:51 PM PDT 24 Apr 15 04:41:55 PM PDT 24 10820603270 ps
T718 /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.2330447147 Apr 15 04:03:28 PM PDT 24 Apr 15 04:20:04 PM PDT 24 5226776220 ps
T719 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3254957304 Apr 15 03:46:52 PM PDT 24 Apr 15 03:59:07 PM PDT 24 4478966726 ps
T720 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.220950441 Apr 15 03:45:17 PM PDT 24 Apr 15 03:53:18 PM PDT 24 4374642576 ps
T465 /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.36562544 Apr 15 04:14:33 PM PDT 24 Apr 15 04:21:05 PM PDT 24 4303132388 ps
T420 /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3997737025 Apr 15 04:18:27 PM PDT 24 Apr 15 04:23:04 PM PDT 24 3671622908 ps
T160 /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.1583431576 Apr 15 04:16:28 PM PDT 24 Apr 15 04:22:30 PM PDT 24 3832834828 ps
T721 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.3978187254 Apr 15 03:51:09 PM PDT 24 Apr 15 04:38:38 PM PDT 24 10248451272 ps
T357 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3077012150 Apr 15 03:44:48 PM PDT 24 Apr 15 03:58:19 PM PDT 24 5225636658 ps
T722 /workspace/coverage/default/2.chip_sw_aes_entropy.3619649718 Apr 15 04:05:02 PM PDT 24 Apr 15 04:09:45 PM PDT 24 2626248496 ps
T443 /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.2246935982 Apr 15 04:15:18 PM PDT 24 Apr 15 04:22:48 PM PDT 24 4424560052 ps
T723 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.1653701683 Apr 15 03:52:17 PM PDT 24 Apr 15 04:00:22 PM PDT 24 5949357615 ps
T724 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.3659871216 Apr 15 03:47:56 PM PDT 24 Apr 15 03:53:57 PM PDT 24 3877471742 ps
T136 /workspace/coverage/default/1.chip_jtag_mem_access.3010441817 Apr 15 03:50:18 PM PDT 24 Apr 15 04:16:06 PM PDT 24 13574753332 ps
T725 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.3595538162 Apr 15 03:52:43 PM PDT 24 Apr 15 04:46:32 PM PDT 24 13424379974 ps
T726 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.920568478 Apr 15 04:04:13 PM PDT 24 Apr 15 04:07:56 PM PDT 24 2806586221 ps
T727 /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3721078355 Apr 15 04:13:13 PM PDT 24 Apr 15 04:18:57 PM PDT 24 4049363576 ps
T151 /workspace/coverage/default/0.chip_sw_alert_test.456990910 Apr 15 03:43:37 PM PDT 24 Apr 15 03:48:18 PM PDT 24 3624640276 ps
T728 /workspace/coverage/default/8.chip_sw_all_escalation_resets.268244738 Apr 15 04:12:39 PM PDT 24 Apr 15 04:22:14 PM PDT 24 5833630256 ps
T116 /workspace/coverage/default/0.chip_plic_all_irqs_10.3864713290 Apr 15 03:48:30 PM PDT 24 Apr 15 03:59:12 PM PDT 24 3818186324 ps
T729 /workspace/coverage/default/2.chip_sw_hmac_smoketest.1663276989 Apr 15 04:10:49 PM PDT 24 Apr 15 04:16:40 PM PDT 24 2369782000 ps
T343 /workspace/coverage/default/1.chip_sw_entropy_src_csrng.3474113242 Apr 15 03:56:07 PM PDT 24 Apr 15 04:26:24 PM PDT 24 6763645812 ps
T730 /workspace/coverage/default/2.chip_tap_straps_prod.488192693 Apr 15 04:06:10 PM PDT 24 Apr 15 04:36:57 PM PDT 24 15845965891 ps
T369 /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1957207648 Apr 15 04:23:12 PM PDT 24 Apr 15 04:30:43 PM PDT 24 4566984648 ps
T283 /workspace/coverage/default/35.chip_sw_all_escalation_resets.3333905651 Apr 15 04:15:56 PM PDT 24 Apr 15 04:26:23 PM PDT 24 4611958128 ps
T170 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.866702756 Apr 15 03:45:11 PM PDT 24 Apr 15 03:50:05 PM PDT 24 7431349224 ps
T466 /workspace/coverage/default/49.chip_sw_all_escalation_resets.1583744463 Apr 15 04:19:11 PM PDT 24 Apr 15 04:30:17 PM PDT 24 4969981672 ps
T731 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.523297679 Apr 15 03:51:28 PM PDT 24 Apr 15 04:40:46 PM PDT 24 12675529450 ps
T732 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.3513870551 Apr 15 03:47:33 PM PDT 24 Apr 15 03:56:28 PM PDT 24 3064891317 ps
T733 /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.921013918 Apr 15 04:02:47 PM PDT 24 Apr 15 04:21:37 PM PDT 24 6564736020 ps
T235 /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.1978038157 Apr 15 04:07:22 PM PDT 24 Apr 15 04:37:20 PM PDT 24 18813226010 ps
T178 /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.2401740435 Apr 15 04:03:37 PM PDT 24 Apr 15 04:05:24 PM PDT 24 2228653372 ps
T734 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1184463859 Apr 15 04:00:35 PM PDT 24 Apr 15 04:05:30 PM PDT 24 3757746095 ps
T505 /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.485557882 Apr 15 04:18:06 PM PDT 24 Apr 15 04:24:44 PM PDT 24 3833243600 ps
T417 /workspace/coverage/default/47.chip_sw_all_escalation_resets.3505217103 Apr 15 04:17:59 PM PDT 24 Apr 15 04:27:19 PM PDT 24 4524518378 ps
T735 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.4276436152 Apr 15 04:07:09 PM PDT 24 Apr 15 04:18:20 PM PDT 24 5170803886 ps
T736 /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.3091240940 Apr 15 04:12:39 PM PDT 24 Apr 15 04:17:21 PM PDT 24 2847720678 ps
T737 /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.3791760777 Apr 15 03:46:39 PM PDT 24 Apr 15 03:51:07 PM PDT 24 3413218186 ps
T738 /workspace/coverage/default/0.chip_sw_example_manufacturer.195370666 Apr 15 03:42:42 PM PDT 24 Apr 15 03:45:30 PM PDT 24 2746732160 ps
T739 /workspace/coverage/default/0.chip_tap_straps_prod.3641364876 Apr 15 03:44:54 PM PDT 24 Apr 15 04:03:02 PM PDT 24 9657037571 ps
T740 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.3359945337 Apr 15 03:51:15 PM PDT 24 Apr 15 04:49:23 PM PDT 24 12516784200 ps
T741 /workspace/coverage/default/2.rom_e2e_asm_init_prod.2845478488 Apr 15 04:13:02 PM PDT 24 Apr 15 05:14:36 PM PDT 24 15495718266 ps
T742 /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.953362884 Apr 15 04:05:55 PM PDT 24 Apr 15 04:10:10 PM PDT 24 2788060472 ps
T743 /workspace/coverage/default/2.chip_sw_aes_enc.2583038394 Apr 15 04:04:36 PM PDT 24 Apr 15 04:09:50 PM PDT 24 3231411300 ps
T744 /workspace/coverage/default/0.chip_sw_csrng_kat_test.905004318 Apr 15 03:48:22 PM PDT 24 Apr 15 03:53:17 PM PDT 24 2847117272 ps
T370 /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1697844187 Apr 15 04:16:27 PM PDT 24 Apr 15 04:23:57 PM PDT 24 3925857856 ps
T745 /workspace/coverage/default/96.chip_sw_all_escalation_resets.3122264159 Apr 15 04:22:35 PM PDT 24 Apr 15 04:32:38 PM PDT 24 4607773392 ps
T746 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.899189749 Apr 15 04:03:05 PM PDT 24 Apr 15 04:13:47 PM PDT 24 4374254065 ps
T300 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.2652094107 Apr 15 03:55:59 PM PDT 24 Apr 15 04:03:51 PM PDT 24 5237962648 ps
T315 /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.2361987539 Apr 15 04:06:47 PM PDT 24 Apr 15 04:12:53 PM PDT 24 3185425304 ps
T747 /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.339690903 Apr 15 04:12:06 PM PDT 24 Apr 15 04:17:23 PM PDT 24 3226510936 ps
T748 /workspace/coverage/default/0.rom_keymgr_functest.463401285 Apr 15 03:47:10 PM PDT 24 Apr 15 03:56:48 PM PDT 24 5672619098 ps
T749 /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.920564300 Apr 15 04:13:00 PM PDT 24 Apr 15 04:27:01 PM PDT 24 10437005789 ps
T750 /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.4073180406 Apr 15 04:15:25 PM PDT 24 Apr 15 04:25:08 PM PDT 24 3916805428 ps
T475 /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.745965549 Apr 15 04:17:54 PM PDT 24 Apr 15 04:23:51 PM PDT 24 3025278500 ps
T86 /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.2388976531 Apr 15 04:12:14 PM PDT 24 Apr 15 04:23:20 PM PDT 24 6770392896 ps
T751 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1192095527 Apr 15 03:46:24 PM PDT 24 Apr 15 03:57:22 PM PDT 24 3786858098 ps
T210 /workspace/coverage/default/1.chip_plic_all_irqs_0.1624855569 Apr 15 03:59:58 PM PDT 24 Apr 15 04:23:27 PM PDT 24 6136298228 ps
T752 /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3252676723 Apr 15 04:11:54 PM PDT 24 Apr 15 04:34:10 PM PDT 24 8479652160 ps
T301 /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.2864952468 Apr 15 04:21:17 PM PDT 24 Apr 15 04:28:15 PM PDT 24 3154646264 ps
T753 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.1544097369 Apr 15 04:02:34 PM PDT 24 Apr 15 04:32:24 PM PDT 24 8150400432 ps
T754 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.3786321186 Apr 15 04:05:51 PM PDT 24 Apr 15 04:13:58 PM PDT 24 5818154467 ps
T755 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.650352885 Apr 15 03:48:22 PM PDT 24 Apr 15 03:58:06 PM PDT 24 5005387194 ps
T756 /workspace/coverage/default/88.chip_sw_all_escalation_resets.1245757345 Apr 15 04:20:51 PM PDT 24 Apr 15 04:30:46 PM PDT 24 4750292602 ps
T757 /workspace/coverage/default/0.chip_sw_example_concurrency.1942073074 Apr 15 03:43:34 PM PDT 24 Apr 15 03:46:44 PM PDT 24 2462998140 ps
T470 /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.718060520 Apr 15 04:16:11 PM PDT 24 Apr 15 04:22:28 PM PDT 24 4278573880 ps
T758 /workspace/coverage/default/1.chip_sw_aes_idle.4208622296 Apr 15 03:51:03 PM PDT 24 Apr 15 03:54:05 PM PDT 24 1960192072 ps
T759 /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.2839853253 Apr 15 03:45:58 PM PDT 24 Apr 15 03:53:53 PM PDT 24 9676571520 ps
T760 /workspace/coverage/default/1.chip_sw_power_idle_load.842303399 Apr 15 04:00:35 PM PDT 24 Apr 15 04:15:48 PM PDT 24 4300772424 ps
T761 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.2951595537 Apr 15 03:53:27 PM PDT 24 Apr 15 05:02:52 PM PDT 24 17795906440 ps
T360 /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2005204360 Apr 15 03:46:01 PM PDT 24 Apr 15 03:58:35 PM PDT 24 4680535376 ps
T762 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.607988570 Apr 15 03:45:00 PM PDT 24 Apr 15 03:54:08 PM PDT 24 6760659752 ps
T149 /workspace/coverage/default/1.chip_plic_all_irqs_10.126215992 Apr 15 03:56:28 PM PDT 24 Apr 15 04:05:56 PM PDT 24 3721467812 ps
T763 /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.4236637038 Apr 15 03:48:34 PM PDT 24 Apr 15 03:53:49 PM PDT 24 2735972148 ps
T174 /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.1314518112 Apr 15 03:43:02 PM PDT 24 Apr 15 06:44:51 PM PDT 24 58687175408 ps
T236 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.2775340627 Apr 15 04:03:11 PM PDT 24 Apr 15 05:29:21 PM PDT 24 47619232072 ps
T11 /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.3832083758 Apr 15 04:02:34 PM PDT 24 Apr 15 04:11:03 PM PDT 24 4131913793 ps
T764 /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.720743775 Apr 15 04:12:33 PM PDT 24 Apr 15 04:57:21 PM PDT 24 12866186240 ps
T765 /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.1189366323 Apr 15 03:48:42 PM PDT 24 Apr 15 03:51:03 PM PDT 24 2659006985 ps
T766 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.2084995898 Apr 15 03:51:23 PM PDT 24 Apr 15 05:28:41 PM PDT 24 46661467645 ps
T767 /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.585880679 Apr 15 03:48:01 PM PDT 24 Apr 15 03:52:20 PM PDT 24 2693632836 ps
T768 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.1891829397 Apr 15 04:11:29 PM PDT 24 Apr 15 04:19:31 PM PDT 24 3912596896 ps
T769 /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2203525454 Apr 15 04:20:38 PM PDT 24 Apr 15 04:30:12 PM PDT 24 3774887988 ps
T461 /workspace/coverage/default/14.chip_sw_all_escalation_resets.2924457257 Apr 15 04:13:31 PM PDT 24 Apr 15 04:23:13 PM PDT 24 5348757838 ps
T275 /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.1370514113 Apr 15 03:57:59 PM PDT 24 Apr 15 04:02:11 PM PDT 24 2236834940 ps
T770 /workspace/coverage/default/86.chip_sw_all_escalation_resets.2264214290 Apr 15 04:20:45 PM PDT 24 Apr 15 04:32:11 PM PDT 24 5234019910 ps
T771 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3993146679 Apr 15 03:49:10 PM PDT 24 Apr 15 03:56:42 PM PDT 24 6567344540 ps
T772 /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.1021206711 Apr 15 04:06:03 PM PDT 24 Apr 15 04:42:08 PM PDT 24 24121929255 ps
T773 /workspace/coverage/default/2.chip_sw_clkmgr_jitter.1425171417 Apr 15 04:07:58 PM PDT 24 Apr 15 04:12:47 PM PDT 24 3143361091 ps
T453 /workspace/coverage/default/48.chip_sw_all_escalation_resets.580939249 Apr 15 04:19:33 PM PDT 24 Apr 15 04:30:24 PM PDT 24 5983061268 ps
T774 /workspace/coverage/default/2.chip_sw_csrng_kat_test.3576973405 Apr 15 04:04:57 PM PDT 24 Apr 15 04:10:24 PM PDT 24 3588671752 ps
T41 /workspace/coverage/default/2.chip_sw_spi_device_tpm.1264359711 Apr 15 04:00:51 PM PDT 24 Apr 15 04:07:01 PM PDT 24 3471763749 ps
T499 /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2846373444 Apr 15 04:23:02 PM PDT 24 Apr 15 04:30:00 PM PDT 24 4128356440 ps
T507 /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.555063252 Apr 15 04:21:03 PM PDT 24 Apr 15 04:28:27 PM PDT 24 3368799508 ps
T775 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.2612829225 Apr 15 04:01:24 PM PDT 24 Apr 15 04:24:21 PM PDT 24 8415888200 ps
T435 /workspace/coverage/default/21.chip_sw_all_escalation_resets.2571253992 Apr 15 04:14:16 PM PDT 24 Apr 15 04:26:42 PM PDT 24 4714437624 ps
T145 /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.1363527718 Apr 15 03:44:38 PM PDT 24 Apr 15 03:59:59 PM PDT 24 9221165351 ps
T444 /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2587852015 Apr 15 04:19:47 PM PDT 24 Apr 15 04:24:46 PM PDT 24 3481873064 ps
T776 /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.2802653712 Apr 15 04:16:25 PM PDT 24 Apr 15 04:21:55 PM PDT 24 4126470312 ps
T777 /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.3731892599 Apr 15 04:20:06 PM PDT 24 Apr 15 04:25:47 PM PDT 24 3260253224 ps
T459 /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.639939649 Apr 15 04:11:38 PM PDT 24 Apr 15 04:18:36 PM PDT 24 3321090360 ps
T391 /workspace/coverage/default/2.chip_sw_edn_boot_mode.1050500350 Apr 15 04:04:18 PM PDT 24 Apr 15 04:14:07 PM PDT 24 3178092760 ps
T34 /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.578328936 Apr 15 03:47:42 PM PDT 24 Apr 15 03:53:26 PM PDT 24 2998558130 ps
T778 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.1950251718 Apr 15 03:47:07 PM PDT 24 Apr 15 03:56:04 PM PDT 24 3738853680 ps
T779 /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.1038666030 Apr 15 04:02:48 PM PDT 24 Apr 15 04:11:47 PM PDT 24 4042749314 ps
T780 /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.125742484 Apr 15 04:10:43 PM PDT 24 Apr 15 04:15:43 PM PDT 24 2700649984 ps
T259 /workspace/coverage/default/2.chip_sw_plic_sw_irq.250584739 Apr 15 04:05:52 PM PDT 24 Apr 15 04:09:14 PM PDT 24 2574352464 ps
T781 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.1791923362 Apr 15 03:51:00 PM PDT 24 Apr 15 04:00:35 PM PDT 24 4972249660 ps
T478 /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.1304783847 Apr 15 04:13:41 PM PDT 24 Apr 15 04:19:16 PM PDT 24 3403390010 ps
T782 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.3312912060 Apr 15 04:03:27 PM PDT 24 Apr 15 04:13:25 PM PDT 24 3909427592 ps
T783 /workspace/coverage/default/9.chip_sw_all_escalation_resets.2259252137 Apr 15 04:12:47 PM PDT 24 Apr 15 04:21:06 PM PDT 24 5556454920 ps
T784 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.3457400101 Apr 15 03:45:19 PM PDT 24 Apr 15 03:54:38 PM PDT 24 7017019176 ps
T785 /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.2701479536 Apr 15 04:05:58 PM PDT 24 Apr 15 04:09:41 PM PDT 24 2342899024 ps
T786 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3767778439 Apr 15 04:05:18 PM PDT 24 Apr 15 04:13:52 PM PDT 24 3990942722 ps
T787 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.1371485766 Apr 15 03:54:26 PM PDT 24 Apr 15 04:49:59 PM PDT 24 14417089838 ps
T788 /workspace/coverage/default/1.chip_sw_csrng_kat_test.2707545070 Apr 15 03:54:03 PM PDT 24 Apr 15 03:59:43 PM PDT 24 3591844310 ps
T150 /workspace/coverage/default/2.chip_plic_all_irqs_10.1269200934 Apr 15 04:06:05 PM PDT 24 Apr 15 04:13:35 PM PDT 24 3826227750 ps
T789 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.3726823803 Apr 15 03:51:00 PM PDT 24 Apr 15 04:03:14 PM PDT 24 4669316876 ps
T383 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.693535533 Apr 15 04:08:54 PM PDT 24 Apr 15 05:10:37 PM PDT 24 24142577470 ps
T790 /workspace/coverage/default/1.chip_sw_kmac_smoketest.3104208294 Apr 15 04:00:03 PM PDT 24 Apr 15 04:03:31 PM PDT 24 2869940260 ps
T83 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2546777235 Apr 15 03:46:06 PM PDT 24 Apr 15 03:55:51 PM PDT 24 5451342600 ps
T39 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1602809651 Apr 15 03:50:34 PM PDT 24 Apr 15 03:58:33 PM PDT 24 4827155988 ps
T791 /workspace/coverage/default/3.chip_sw_uart_tx_rx.877593976 Apr 15 04:11:28 PM PDT 24 Apr 15 04:19:17 PM PDT 24 4494698690 ps
T152 /workspace/coverage/default/2.chip_sw_alert_test.3721400182 Apr 15 04:04:03 PM PDT 24 Apr 15 04:09:02 PM PDT 24 2878507836 ps
T792 /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.1200679198 Apr 15 03:51:03 PM PDT 24 Apr 15 03:59:41 PM PDT 24 3527715816 ps
T793 /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3099994485 Apr 15 04:04:21 PM PDT 24 Apr 15 04:14:01 PM PDT 24 18443666310 ps
T794 /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.370005815 Apr 15 03:44:51 PM PDT 24 Apr 15 03:58:37 PM PDT 24 5881151758 ps
T795 /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.860346219 Apr 15 03:44:38 PM PDT 24 Apr 15 03:53:15 PM PDT 24 5321920448 ps
T796 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3062666415 Apr 15 03:45:37 PM PDT 24 Apr 15 03:55:46 PM PDT 24 4205899190 ps
T490 /workspace/coverage/default/71.chip_sw_all_escalation_resets.202339258 Apr 15 04:19:10 PM PDT 24 Apr 15 04:29:30 PM PDT 24 4680790656 ps
T797 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.579535464 Apr 15 03:52:06 PM PDT 24 Apr 15 04:52:59 PM PDT 24 18189774366 ps
T449 /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1672012124 Apr 15 04:21:29 PM PDT 24 Apr 15 04:26:17 PM PDT 24 3470293344 ps
T798 /workspace/coverage/default/4.chip_tap_straps_dev.4181467333 Apr 15 04:11:28 PM PDT 24 Apr 15 04:13:48 PM PDT 24 2573815079 ps
T799 /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.1899372173 Apr 15 03:51:45 PM PDT 24 Apr 15 03:54:53 PM PDT 24 2036973812 ps
T12 /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.3137120607 Apr 15 03:47:15 PM PDT 24 Apr 15 03:57:25 PM PDT 24 4072830495 ps
T217 /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.4190334723 Apr 15 03:50:19 PM PDT 24 Apr 15 04:22:13 PM PDT 24 13900483076 ps
T800 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.68937100 Apr 15 04:10:07 PM PDT 24 Apr 15 04:13:01 PM PDT 24 2073930513 ps
T801 /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.1566947952 Apr 15 03:46:12 PM PDT 24 Apr 15 04:04:56 PM PDT 24 5558237240 ps
T502 /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1795067356 Apr 15 04:18:53 PM PDT 24 Apr 15 04:26:52 PM PDT 24 4363793840 ps
T802 /workspace/coverage/default/2.chip_sw_flash_init.451202667 Apr 15 04:00:59 PM PDT 24 Apr 15 04:30:08 PM PDT 24 18383117650 ps
T803 /workspace/coverage/default/2.chip_sw_hmac_enc_idle.1312839011 Apr 15 04:05:53 PM PDT 24 Apr 15 04:11:48 PM PDT 24 3204213828 ps
T378 /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.1469848533 Apr 15 03:59:09 PM PDT 24 Apr 15 04:02:55 PM PDT 24 2169751912 ps
T804 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3704952491 Apr 15 03:46:04 PM PDT 24 Apr 15 04:05:09 PM PDT 24 14690499200 ps
T805 /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.392139632 Apr 15 03:44:38 PM PDT 24 Apr 15 03:50:37 PM PDT 24 4066936168 ps
T806 /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.1972660131 Apr 15 03:48:06 PM PDT 24 Apr 15 04:15:48 PM PDT 24 20660872901 ps
T807 /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.884049018 Apr 15 03:47:59 PM PDT 24 Apr 15 03:50:47 PM PDT 24 2465726451 ps
T808 /workspace/coverage/default/0.chip_tap_straps_dev.1623986862 Apr 15 03:45:41 PM PDT 24 Apr 15 03:48:13 PM PDT 24 2127605984 ps
T8 /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.165641403 Apr 15 04:00:20 PM PDT 24 Apr 15 04:04:16 PM PDT 24 3528347565 ps
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