Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3726307	1			T80	19559		T81	544		T82	1850
values[2]	751564	1			T80	3225		T81	186		T82	500
values[3]	104236	1			T80	482		T81	7		T352	79
values[4]	55025	1			T80	176		T352	64		T523	312
values[5]	36766	1			T80	72		T352	32		T523	258
values[6]	27890	1			T80	42		T352	13		T523	153
values[7]	22370	1			T80	21		T352	30		T523	75
values[8]	19135	1			T80	13		T352	27		T523	44
values[9]	17024	1			T80	19		T352	23		T523	48
values[10]	15546	1			T80	23		T352	9		T523	39
values[11]	14352	1			T80	19		T352	25		T523	31
values[12]	13366	1			T80	16		T352	25		T523	14
values[13]	12632	1			T80	4		T352	25		T523	16
values[14]	12238	1			T80	14		T352	21		T523	14
values[15]	11773	1			T80	13		T352	13		T523	17
values[16]	10955	1			T80	8		T352	11		T523	28
values[17]	10738	1			T80	5		T352	9		T523	43
values[18]	10680	1			T80	13		T352	12		T523	36
values[19]	10207	1			T80	8		T352	10		T523	59
values[20]	9829	1			T80	7		T352	22		T523	37
values[21]	9700	1			T80	14		T352	21		T523	15
values[22]	9512	1			T80	8		T352	23		T523	9
values[23]	9291	1			T80	10		T352	21		T523	9
values[24]	8865	1			T80	9		T352	26		T523	12
values[25]	8371	1			T80	10		T352	7		T523	10
values[26]	7903	1			T80	6		T352	14		T523	12
values[27]	7403	1			T80	5		T352	6		T523	7
values[28]	7217	1			T80	12		T352	1		T523	9
values[29]	6776	1			T80	14		T352	3		T523	10
values[30]	6490	1			T80	8		T523	5		T399	13
values[31]	5989	1			T80	8		T523	9		T399	22
values[32]	5528	1			T80	7		T523	11		T399	16
values[33]	5066	1			T80	6		T523	9		T399	11
values[34]	4726	1			T80	6		T523	16		T399	10
values[35]	4493	1			T80	5		T523	22		T399	10
values[36]	4266	1			T80	8		T523	9		T399	13
values[37]	3841	1			T80	9		T523	9		T399	9
values[38]	3633	1			T80	15		T523	14		T399	11
values[39]	3531	1			T80	16		T523	12		T399	11
values[40]	3434	1			T80	16		T523	26		T399	21
values[41]	3304	1			T80	14		T523	17		T399	12
values[42]	3308	1			T80	9		T523	7		T399	20
values[43]	3263	1			T80	9		T523	4		T399	20
values[44]	3087	1			T80	5		T523	7		T399	13
values[45]	3126	1			T80	10		T523	6		T399	16
values[46]	2987	1			T80	18		T523	11		T399	10
values[47]	2957	1			T80	8		T523	9		T399	17
values[48]	2981	1			T80	7		T523	9		T399	19
values[49]	2828	1			T80	5		T523	5		T399	16
values[50]	2738	1			T80	4		T523	5		T399	18
values[51]	2766	1			T80	6		T523	7		T399	16
values[52]	2657	1			T80	2		T523	3		T399	12
values[53]	2674	1			T80	2		T523	5		T399	14
values[54]	2650	1			T80	5		T523	5		T399	13
values[55]	2501	1			T80	4		T523	5		T399	22
values[56]	2478	1			T80	3		T523	6		T399	27
values[57]	2378	1			T80	5		T523	6		T399	10
values[58]	2357	1			T80	8		T523	10		T399	9
values[59]	2349	1			T80	5		T523	4		T399	22
values[60]	2395	1			T80	3		T523	7		T399	18
values[61]	2659	1			T80	7		T523	5		T399	35
values[62]	3945	1			T80	21		T523	27		T399	57
values[63]	16017	1			T80	46		T523	47		T399	85
values[64]	217561	1			T80	61		T523	216		T399	111

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4776043	1			T80	24323		T81	484		T82	1661
values[2]	790712	1			T80	2743		T81	143		T82	437
values[3]	74771	1			T80	205		T81	48		T82	12
values[4]	14213	1			T80	9		T81	14		T82	1
values[5]	5622	1			T80	6		T81	3		T430	2
values[6]	3276	1			T80	4		T81	3		T399	51
values[7]	2415	1			T80	5		T81	1		T399	47
values[8]	2005	1			T80	3		T399	12		T405	1
values[9]	1903	1			T80	7		T399	9		T405	1
values[10]	1829	1			T80	4		T399	3		T528	3
values[11]	1601	1			T80	4		T399	1		T528	2
values[12]	1484	1			T80	5		T528	2		T805	2
values[13]	1230	1			T80	5		T528	2		T805	2
values[14]	1150	1			T80	5		T528	2		T805	2
values[15]	1016	1			T80	4		T528	2		T805	2
values[16]	905	1			T80	2		T528	2		T805	2
values[17]	930	1			T80	6		T528	2		T805	2
values[18]	879	1			T80	6		T528	3		T805	2
values[19]	796	1			T80	5		T528	2		T805	2
values[20]	768	1			T80	6		T528	1		T805	2
values[21]	687	1			T80	2		T528	1		T805	2
values[22]	659	1			T80	4		T528	2		T805	2
values[23]	706	1			T80	2		T528	2		T805	2
values[24]	701	1			T80	4		T528	2		T805	2
values[25]	654	1			T80	5		T528	2		T805	2
values[26]	619	1			T80	3		T528	2		T805	3
values[27]	576	1			T80	7		T528	2		T805	2
values[28]	599	1			T80	7		T528	1		T805	2
values[29]	529	1			T80	6		T528	1		T805	2
values[30]	523	1			T80	10		T528	2		T805	2
values[31]	492	1			T80	7		T528	2		T805	2
values[32]	433	1			T80	2		T528	2		T805	2
values[33]	484	1			T80	7		T528	2		T805	2
values[34]	479	1			T80	7		T528	3		T805	2
values[35]	426	1			T80	6		T528	2		T805	2
values[36]	428	1			T80	8		T528	2		T805	2
values[37]	496	1			T80	6		T528	2		T805	2
values[38]	419	1			T80	4		T528	2		T805	2
values[39]	455	1			T80	5		T528	2		T805	2
values[40]	403	1			T80	8		T528	2		T805	2
values[41]	375	1			T80	4		T528	2		T805	2
values[42]	356	1			T80	4		T528	2		T805	2
values[43]	367	1			T80	3		T528	3		T805	2
values[44]	375	1			T80	3		T528	2		T805	2
values[45]	390	1			T80	5		T528	2		T805	2
values[46]	390	1			T80	3		T528	2		T805	2
values[47]	359	1			T80	5		T528	2		T805	2
values[48]	349	1			T80	5		T528	2		T805	2
values[49]	359	1			T80	3		T528	2		T805	2
values[50]	365	1			T80	3		T528	2		T805	2
values[51]	307	1			T80	5		T528	2		T805	2
values[52]	329	1			T80	4		T528	2		T805	3
values[53]	320	1			T80	8		T528	2		T805	2
values[54]	310	1			T80	13		T528	2		T805	2
values[55]	330	1			T80	7		T528	2		T805	2
values[56]	328	1			T80	2		T528	2		T805	2
values[57]	311	1			T80	3		T528	2		T805	2
values[58]	329	1			T80	10		T528	2		T805	2
values[59]	302	1			T80	3		T528	2		T805	2
values[60]	289	1			T80	3		T528	2		T805	2
values[61]	337	1			T80	3		T528	2		T805	2
values[62]	556	1			T80	13		T528	2		T805	2
values[63]	2195	1			T80	43		T528	4		T805	19
values[64]	22277	1			T80	71		T528	81		T805	408

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	606148	1			T80	6073		T81	5		T82	15
values[2]	2711686	1			T80	14872		T81	120		T82	1624
values[3]	1090400	1			T80	2771		T81	546		T82	429
values[4]	144131	1			T80	343		T81	103		T82	1
values[5]	74279	1			T80	152		T81	6		T352	77
values[6]	48871	1			T80	85		T352	36		T523	194
values[7]	35630	1			T80	57		T352	39		T523	117
values[8]	27963	1			T80	36		T352	39		T523	84
values[9]	23398	1			T80	20		T352	20		T523	64
values[10]	20314	1			T80	23		T352	16		T523	41
values[11]	18292	1			T80	19		T352	3		T523	41
values[12]	16513	1			T80	15		T352	7		T523	21
values[13]	15295	1			T80	13		T352	15		T523	21
values[14]	14655	1			T80	7		T352	11		T523	14
values[15]	14437	1			T80	12		T352	9		T523	20
values[16]	13416	1			T80	14		T352	7		T523	18
values[17]	12536	1			T80	18		T352	10		T523	20
values[18]	12522	1			T80	22		T352	16		T523	24
values[19]	11885	1			T80	8		T352	12		T523	15
values[20]	11560	1			T80	14		T352	33		T523	9
values[21]	11205	1			T80	10		T352	34		T523	4
values[22]	10661	1			T80	7		T352	24		T523	10
values[23]	10170	1			T80	6		T352	11		T523	6
values[24]	10086	1			T80	14		T352	23		T523	19
values[25]	9820	1			T80	5		T352	5		T523	44
values[26]	9159	1			T80	10		T352	10		T523	32
values[27]	8473	1			T80	7		T352	8		T523	40
values[28]	8295	1			T80	3		T352	7		T523	22
values[29]	7528	1			T80	3		T352	3		T523	29
values[30]	7015	1			T80	2		T352	7		T523	18
values[31]	6517	1			T80	2		T352	14		T523	16
values[32]	6080	1			T80	4		T352	12		T523	12
values[33]	5682	1			T80	7		T352	6		T523	20
values[34]	5381	1			T80	13		T352	2		T523	16
values[35]	4942	1			T80	14		T352	2		T523	8
values[36]	4610	1			T80	11		T352	4		T523	11
values[37]	4329	1			T80	9		T352	1		T523	9
values[38]	4045	1			T80	2		T352	4		T523	5
values[39]	3908	1			T80	10		T352	2		T523	7
values[40]	3735	1			T80	7		T352	1		T523	5
values[41]	3578	1			T80	7		T352	1		T523	7
values[42]	3472	1			T80	2		T352	1		T523	3
values[43]	3387	1			T80	9		T352	5		T523	7
values[44]	3379	1			T80	9		T352	1		T523	5
values[45]	3378	1			T80	6		T352	5		T523	5
values[46]	3267	1			T80	5		T352	1		T523	7
values[47]	3211	1			T80	5		T352	2		T523	8
values[48]	3148	1			T80	2		T352	2		T523	11
values[49]	3130	1			T80	2		T352	2		T523	6
values[50]	3099	1			T80	3		T352	1		T523	9
values[51]	2976	1			T80	6		T352	5		T523	10
values[52]	2904	1			T80	2		T352	5		T523	14
values[53]	2961	1			T80	4		T352	5		T523	11
values[54]	2842	1			T80	4		T352	4		T523	4
values[55]	2828	1			T80	5		T352	3		T523	6
values[56]	2825	1			T80	14		T352	1		T523	10
values[57]	2765	1			T80	9		T352	4		T523	9
values[58]	2698	1			T80	3		T352	4		T523	7
values[59]	2582	1			T80	5		T352	1		T523	12
values[60]	2657	1			T80	5		T352	6		T523	10
values[61]	2693	1			T80	2		T352	2		T523	8
values[62]	3695	1			T80	10		T523	10		T399	9
values[63]	18142	1			T80	19		T523	54		T399	33
values[64]	205809	1			T80	34		T523	185		T399	131