Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1853631	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

26180787

1

T1

13186

T2

14967

T3

8255

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	18731442	1			T1	6488		T2	6976		T3	2606
values[0x0]	7853313	1			T1	6698		T2	7991		T3	5649
values[0x1]	1449663	1			T1	663		T2	1201		T3	395

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	548181	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

27486237

1

T1

13849

T2

16168

T3

8650

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12976023	1			T1	6925		T2	8085		T3	4326
valid_sources[0x01]	12975112	1			T1	6924		T2	8083		T3	4324
valid_sources[0x02]	33178	1			T85	39		T240	1		T202	1
valid_sources[0x03]	32810	1			T533	6		T145	377		T530	23
valid_sources[0x04]	33609	1			T53	2		T86	1		T240	1
valid_sources[0x05]	34060	1			T202	2		T145	363		T540	9
valid_sources[0x06]	32964	1			T240	1		T145	367		T540	5
valid_sources[0x07]	34499	1			T420	1		T533	1		T145	400
valid_sources[0x08]	33714	1			T240	2		T202	1		T533	46
valid_sources[0x09]	35048	1			T240	4		T202	2		T145	386
valid_sources[0x0a]	33570	1			T240	1		T202	1		T145	381
valid_sources[0x0b]	32652	1			T53	2		T533	5		T145	408
valid_sources[0x0c]	33615	1			T145	378		T540	16		T530	30
valid_sources[0x0d]	33005	1			T86	1		T240	2		T420	1
valid_sources[0x0e]	33481	1			T145	414		T540	10		T530	34
valid_sources[0x0f]	32934	1			T420	3		T145	414		T540	22
valid_sources[0x10]	35995	1			T202	1		T145	418		T540	7
valid_sources[0x11]	33064	1			T533	2		T145	404		T540	4
valid_sources[0x12]	34647	1			T240	2		T202	1		T145	470
valid_sources[0x13]	33069	1			T53	4		T86	4		T240	1
valid_sources[0x14]	35747	1			T53	2		T86	1		T240	2
valid_sources[0x15]	33707	1			T53	1		T240	2		T533	3
valid_sources[0x16]	34221	1			T240	1		T533	9		T145	422
valid_sources[0x17]	33312	1			T86	4		T202	1		T533	1
valid_sources[0x18]	32965	1			T53	6		T86	1		T240	3
valid_sources[0x19]	33709	1			T53	4		T202	2		T533	2
valid_sources[0x1a]	33183	1			T145	400		T540	17		T530	20
valid_sources[0x1b]	34021	1			T145	368		T540	6		T530	68
valid_sources[0x1c]	33567	1			T86	2		T145	335		T540	8
valid_sources[0x1d]	33480	1			T240	1		T533	436		T145	392
valid_sources[0x1e]	34331	1			T86	1		T240	3		T202	1
valid_sources[0x1f]	33307	1			T53	2		T202	3		T533	2
valid_sources[0x20]	36011	1			T240	1		T202	2		T533	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

18122558

1

T1

6488

T2

6976

T3

2606

values[0x0]

all_enables

biggest_size

7816188

1

T1

6698

T2

7991

T3

5649

values[0x1]

all_enables

biggest_size

242041

1

T53

20

T85

16

T86

19

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2761320	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

436326

1

T80

137

T81

91

T82

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1083213	1			T80	487		T81	262		T82	46
values[0x0]	1030018	1			T80	97		T81	232		T82	6
values[0x1]	1084415	1			T80	565		T81	243		T82	53

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2137114	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1060532

1

T80

467

T81

240

T82

41

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	49480	1			T80	13		T81	26		T82	4
valid_sources[0x01]	50317	1			T80	14		T81	15		T82	1
valid_sources[0x02]	50815	1			T80	25		T81	17		T82	3
valid_sources[0x03]	49403	1			T80	11		T81	3		T82	3
valid_sources[0x04]	50166	1			T80	20		T81	2		T82	1
valid_sources[0x05]	50764	1			T80	13		T81	25		T82	1
valid_sources[0x06]	50645	1			T80	10		T352	12		T523	33
valid_sources[0x07]	50455	1			T80	24		T81	14		T82	1
valid_sources[0x08]	50687	1			T80	17		T81	22		T82	1
valid_sources[0x09]	50794	1			T80	22		T82	1		T352	11
valid_sources[0x0a]	49240	1			T80	16		T81	5		T82	3
valid_sources[0x0b]	50818	1			T80	14		T81	21		T82	1
valid_sources[0x0c]	49544	1			T80	25		T81	2		T82	4
valid_sources[0x0d]	49673	1			T80	19		T81	20		T82	3
valid_sources[0x0e]	50312	1			T80	16		T81	10		T82	1
valid_sources[0x0f]	48897	1			T80	13		T81	25		T82	6
valid_sources[0x10]	49271	1			T80	17		T81	7		T82	2
valid_sources[0x11]	50254	1			T80	16		T81	2		T82	3
valid_sources[0x12]	49325	1			T80	25		T81	36		T82	6
valid_sources[0x13]	50306	1			T80	12		T81	22		T352	10
valid_sources[0x14]	50348	1			T80	12		T81	9		T239	3
valid_sources[0x15]	51343	1			T80	24		T81	3		T82	1
valid_sources[0x16]	48906	1			T80	20		T81	17		T82	1
valid_sources[0x17]	50418	1			T80	22		T81	5		T352	8
valid_sources[0x18]	49884	1			T80	15		T81	19		T82	2
valid_sources[0x19]	50091	1			T80	18		T81	23		T82	2
valid_sources[0x1a]	49711	1			T80	14		T82	3		T352	11
valid_sources[0x1b]	49451	1			T80	17		T81	4		T82	1
valid_sources[0x1c]	50290	1			T80	22		T81	33		T82	1
valid_sources[0x1d]	49556	1			T80	16		T82	1		T352	8
valid_sources[0x1e]	50987	1			T80	16		T81	17		T82	2
valid_sources[0x1f]	48576	1			T80	19		T82	1		T352	11
valid_sources[0x20]	49931	1			T80	16		T81	34		T82	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

45813

1

T80

41

T81

8

T82

6

values[0x0]

all_enables

biggest_size

344503

1

T80

50

T81

74

T82

3

values[0x1]

all_enables

biggest_size

46010

1

T80

46

T81

9

T82

5

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2935196	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

477197

1

T80

135

T81

102

T82

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1169063	1			T80	590		T81	228		T82	48
values[0x0]	1074671	1			T80	102		T81	219		T82	6
values[0x1]	1168659	1			T80	581		T81	249		T82	33

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2252972	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1159421

1

T80

491

T81

233

T82

29

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52678	1			T80	19		T81	15		T82	1
valid_sources[0x01]	52960	1			T80	21		T81	15		T82	2
valid_sources[0x02]	53024	1			T80	20		T81	9		T82	3
valid_sources[0x03]	53433	1			T80	21		T81	5		T352	15
valid_sources[0x04]	53798	1			T80	19		T81	8		T82	4
valid_sources[0x05]	53260	1			T80	16		T81	6		T82	2
valid_sources[0x06]	54091	1			T80	24		T81	6		T82	1
valid_sources[0x07]	53020	1			T80	28		T81	13		T82	2
valid_sources[0x08]	53044	1			T80	18		T81	18		T82	3
valid_sources[0x09]	53880	1			T80	18		T81	14		T82	2
valid_sources[0x0a]	53574	1			T80	22		T81	15		T352	12
valid_sources[0x0b]	53448	1			T80	25		T81	13		T82	4
valid_sources[0x0c]	52405	1			T80	21		T81	17		T352	15
valid_sources[0x0d]	53998	1			T80	15		T81	17		T82	2
valid_sources[0x0e]	54346	1			T80	16		T81	10		T82	2
valid_sources[0x0f]	53128	1			T80	11		T81	8		T82	2
valid_sources[0x10]	53239	1			T80	20		T81	12		T82	2
valid_sources[0x11]	53233	1			T80	17		T81	11		T82	1
valid_sources[0x12]	52551	1			T80	18		T81	12		T82	3
valid_sources[0x13]	54002	1			T80	24		T81	10		T82	2
valid_sources[0x14]	53170	1			T80	12		T81	13		T352	15
valid_sources[0x15]	53451	1			T80	24		T81	17		T82	2
valid_sources[0x16]	53535	1			T80	23		T81	2		T352	9
valid_sources[0x17]	53188	1			T80	23		T81	13		T82	1
valid_sources[0x18]	52516	1			T80	18		T81	4		T82	2
valid_sources[0x19]	54116	1			T80	17		T81	12		T82	1
valid_sources[0x1a]	51727	1			T80	26		T81	12		T82	2
valid_sources[0x1b]	53471	1			T80	15		T81	10		T82	2
valid_sources[0x1c]	53678	1			T80	12		T81	12		T352	12
valid_sources[0x1d]	53777	1			T80	17		T81	16		T352	8
valid_sources[0x1e]	54260	1			T80	18		T81	12		T352	16
valid_sources[0x1f]	52889	1			T80	31		T81	12		T82	2
valid_sources[0x20]	52945	1			T80	25		T81	16		T82	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

50256

1

T80

41

T81

6

T82

2

values[0x0]

all_enables

biggest_size

376644

1

T80

48

T81

84

T82

1

values[0x1]

all_enables

biggest_size

50297

1

T80

46

T81

12

T82

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2777526	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

438789

1

T80

114

T81

103

T82

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1089952	1			T80	511		T81	251		T82	49
values[0x0]	1036217	1			T80	109		T81	247		T82	12
values[0x1]	1090146	1			T80	502		T81	282		T82	44

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2150546	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1065769

1

T80

430

T81

259

T82

32

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	49972	1			T80	18		T81	1		T82	2
valid_sources[0x01]	50286	1			T80	10		T81	13		T82	3
valid_sources[0x02]	49541	1			T80	25		T81	5		T82	2
valid_sources[0x03]	50168	1			T80	21		T81	14		T82	1
valid_sources[0x04]	50669	1			T80	11		T81	8		T239	3
valid_sources[0x05]	50567	1			T80	10		T81	5		T82	4
valid_sources[0x06]	50236	1			T80	14		T81	6		T239	15
valid_sources[0x07]	50947	1			T80	23		T81	5		T82	2
valid_sources[0x08]	50869	1			T80	15		T81	20		T82	1
valid_sources[0x09]	51192	1			T80	14		T81	25		T82	1
valid_sources[0x0a]	49984	1			T80	14		T81	10		T82	1
valid_sources[0x0b]	50669	1			T80	15		T81	15		T239	2
valid_sources[0x0c]	50037	1			T80	13		T81	17		T82	2
valid_sources[0x0d]	50622	1			T80	9		T81	5		T82	1
valid_sources[0x0e]	51333	1			T80	22		T81	19		T82	1
valid_sources[0x0f]	50358	1			T80	14		T81	18		T82	3
valid_sources[0x10]	50197	1			T80	17		T81	3		T82	3
valid_sources[0x11]	50441	1			T80	17		T81	1		T82	2
valid_sources[0x12]	50091	1			T80	18		T81	27		T82	1
valid_sources[0x13]	50455	1			T80	23		T81	10		T82	3
valid_sources[0x14]	50584	1			T80	15		T81	11		T239	1
valid_sources[0x15]	50851	1			T80	13		T81	19		T82	2
valid_sources[0x16]	48890	1			T80	20		T81	17		T82	2
valid_sources[0x17]	50189	1			T80	20		T81	10		T239	11
valid_sources[0x18]	50449	1			T80	17		T81	8		T82	2
valid_sources[0x19]	51092	1			T80	26		T81	3		T82	2
valid_sources[0x1a]	50119	1			T80	21		T81	9		T82	1
valid_sources[0x1b]	49222	1			T80	14		T81	10		T82	2
valid_sources[0x1c]	49983	1			T80	14		T81	12		T82	1
valid_sources[0x1d]	50326	1			T80	16		T81	7		T82	1
valid_sources[0x1e]	49937	1			T80	8		T81	10		T82	2
valid_sources[0x1f]	50524	1			T80	24		T81	12		T82	2
valid_sources[0x20]	49957	1			T80	16		T81	15		T82	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

46497

1

T80

29

T81

6

T239

2

values[0x0]

all_enables

biggest_size

346291

1

T80

50

T81

87

T82

6

values[0x1]

all_enables

biggest_size

46001

1

T80

35

T81

10

T82

1