Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.46	92.83		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.46	92.83		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.46	92.83		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.46	92.83		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	39	39	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T34	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T5,T191,T48	Yes	T5,T191,T48	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T5,T191,T48	Yes	T5,T191,T48	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T53,*T83,*T84	Yes	T53,T83,T84	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T53,T85,T86	Yes	T53,T85,T86	INPUT
tl_i.a_valid	Yes	Yes	T5,T191,T48	Yes	T5,T191,T48	INPUT
tl_o.a_ready	Yes	Yes	T5,T191,T48	Yes	T5,T191,T48	OUTPUT
tl_o.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T5,T191,T198	Yes	T5,T191,T198	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T5,T191,T152	Yes	T5,T191,T48	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T5,T191,T152	Yes	T5,T191,T48	OUTPUT
tl_o.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T86,*T202,*T80	Yes	T86,T202,T80	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T5,*T191,*T198	Yes	T5,T191,T198	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T5,T191,T48	Yes	T5,T191,T48	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T152,T64,T100	Yes	T152,T64,T100	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T88,T89,T159	Yes	T88,T89,T159	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T88,T89,T159	Yes	T88,T89,T159	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T152,T64,T100	Yes	T152,T64,T100	OUTPUT
cio_rx_i	Yes	Yes	T2,T3,T34	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T5,T191,T198	Yes	T5,T191,T198	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T5,T191,T198	Yes	T5,T191,T198	OUTPUT
intr_rx_watermark_o	Yes	Yes	T5,T191,T198	Yes	T5,T191,T198	OUTPUT
intr_tx_empty_o	Yes	Yes	T5,T191,T198	Yes	T5,T191,T198	OUTPUT
intr_rx_overflow_o	Yes	Yes	T5,T191,T198	Yes	T5,T191,T198	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T298,T303,T309	Yes	T298,T303,T309	OUTPUT
intr_rx_break_err_o	Yes	Yes	T298,T303,T309	Yes	T298,T303,T309	OUTPUT
intr_rx_timeout_o	Yes	Yes	T298,T303,T309	Yes	T298,T303,T309	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T298,T303,T309	Yes	T298,T303,T309	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	302	302	100.00
Total Bits 0->1	151	151	100.00
Total Bits 1->0	151	151	100.00

Ports	39	39	100.00
Port Bits	302	302	100.00
Port Bits 0->1	151	151	100.00
Port Bits 1->0	151	151	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T34	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T48,T49,T198	Yes	T48,T49,T198	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T48,T49,T198	Yes	T48,T49,T198	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T53,*T83,*T84	Yes	T53,T83,T84	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T53,T85,T86	Yes	T53,T85,T86	INPUT
tl_i.a_valid	Yes	Yes	T48,T152,T49	Yes	T48,T152,T49	INPUT
tl_o.a_ready	Yes	Yes	T48,T152,T49	Yes	T48,T152,T49	OUTPUT
tl_o.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T198,T199,T45	Yes	T198,T199,T45	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T152,T198,T199	Yes	T48,T152,T49	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T152,T198,T199	Yes	T48,T152,T49	OUTPUT
tl_o.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T86,*T202,*T80	Yes	T86,T202,T80	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T198,*T199,*T45	Yes	T198,T199,T45	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T48,T152,T49	Yes	T48,T152,T49	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T152,T64,T100	Yes	T152,T64,T100	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T88,T89,T90	Yes	T88,T89,T90	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T88,T89,T90	Yes	T88,T89,T90	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T152,T64,T100	Yes	T152,T64,T100	OUTPUT
cio_rx_i	Yes	Yes	T2,T3,T34	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T198,T199,T45	Yes	T198,T199,T45	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T198,T199,T200	Yes	T198,T199,T200	OUTPUT
intr_rx_watermark_o	Yes	Yes	T198,T199,T200	Yes	T198,T199,T200	OUTPUT
intr_tx_empty_o	Yes	Yes	T198,T199,T200	Yes	T198,T199,T200	OUTPUT
intr_rx_overflow_o	Yes	Yes	T198,T199,T200	Yes	T198,T199,T200	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T298,T303,T309	Yes	T298,T303,T309	OUTPUT
intr_rx_break_err_o	Yes	Yes	T298,T303,T309	Yes	T298,T303,T309	OUTPUT
intr_rx_timeout_o	Yes	Yes	T298,T303,T309	Yes	T298,T303,T309	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T298,T303,T309	Yes	T298,T303,T309	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	39	39	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T34	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T191,T104,T192	Yes	T191,T104,T192	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T191,T104,T192	Yes	T191,T104,T192	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T53,*T83,*T84	Yes	T53,T83,T84	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T53,T85,T86	Yes	T53,T85,T86	INPUT
tl_i.a_valid	Yes	Yes	T191,T152,T64	Yes	T191,T152,T64	INPUT
tl_o.a_ready	Yes	Yes	T191,T152,T64	Yes	T191,T152,T64	OUTPUT
tl_o.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T191,T104,T192	Yes	T191,T104,T192	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T191,T152,T104	Yes	T191,T152,T64	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T191,T152,T104	Yes	T191,T152,T64	OUTPUT
tl_o.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T86,*T202,*T80	Yes	T86,T202,T80	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T191,*T104,*T192	Yes	T191,T104,T192	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T191,T152,T64	Yes	T191,T152,T64	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T152,T64,T332	Yes	T152,T64,T332	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T88,T89,T159	Yes	T88,T89,T159	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T88,T89,T159	Yes	T88,T89,T159	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T152,T64,T332	Yes	T152,T64,T332	OUTPUT
cio_rx_i	Yes	Yes	T191,T104,T192	Yes	T191,T104,T192	INPUT
cio_tx_o	Yes	Yes	T191,T104,T192	Yes	T191,T104,T192	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T191,T104,T192	Yes	T191,T104,T192	OUTPUT
intr_rx_watermark_o	Yes	Yes	T191,T104,T192	Yes	T191,T104,T192	OUTPUT
intr_tx_empty_o	Yes	Yes	T191,T104,T192	Yes	T191,T104,T192	OUTPUT
intr_rx_overflow_o	Yes	Yes	T191,T104,T192	Yes	T191,T104,T192	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T298,T303,T309	Yes	T298,T303,T309	OUTPUT
intr_rx_break_err_o	Yes	Yes	T298,T303,T309	Yes	T298,T303,T309	OUTPUT
intr_rx_timeout_o	Yes	Yes	T298,T303,T309	Yes	T298,T303,T309	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T298,T303,T309	Yes	T298,T303,T309	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	39	39	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T34	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T5,T187,T306	Yes	T5,T187,T306	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T5,T187,T306	Yes	T5,T187,T306	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T53,*T83,*T84	Yes	T53,T83,T84	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T53,T85,T86	Yes	T53,T85,T86	INPUT
tl_i.a_valid	Yes	Yes	T5,T152,T64	Yes	T5,T152,T64	INPUT
tl_o.a_ready	Yes	Yes	T5,T152,T64	Yes	T5,T152,T64	OUTPUT
tl_o.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T5,T187,T306	Yes	T5,T187,T306	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T5,T152,T187	Yes	T5,T152,T64	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T5,T152,T187	Yes	T5,T152,T64	OUTPUT
tl_o.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T5,*T187,*T306	Yes	T5,T187,T306	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T5,T152,T64	Yes	T5,T152,T64	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T152,T64,T65	Yes	T152,T64,T65	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T88,T89,T90	Yes	T88,T89,T90	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T88,T89,T90	Yes	T88,T89,T90	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T152,T64,T65	Yes	T152,T64,T65	OUTPUT
cio_rx_i	Yes	Yes	T5,T187,T306	Yes	T5,T187,T306	INPUT
cio_tx_o	Yes	Yes	T5,T187,T306	Yes	T5,T187,T306	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T5,T187,T306	Yes	T5,T187,T306	OUTPUT
intr_rx_watermark_o	Yes	Yes	T5,T187,T306	Yes	T5,T187,T306	OUTPUT
intr_tx_empty_o	Yes	Yes	T5,T187,T306	Yes	T5,T187,T306	OUTPUT
intr_rx_overflow_o	Yes	Yes	T5,T187,T306	Yes	T5,T187,T306	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T298,T303,T309	Yes	T298,T303,T309	OUTPUT
intr_rx_break_err_o	Yes	Yes	T298,T303,T309	Yes	T298,T303,T309	OUTPUT
intr_rx_timeout_o	Yes	Yes	T298,T303,T309	Yes	T298,T303,T309	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T298,T303,T309	Yes	T298,T303,T309	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	39	39	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T34	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T14,T15,T299	Yes	T14,T15,T299	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T14,T15,T299	Yes	T14,T15,T299	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T53,*T83,*T84	Yes	T53,T83,T84	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T53,T85,T86	Yes	T53,T85,T86	INPUT
tl_i.a_valid	Yes	Yes	T152,T64,T14	Yes	T152,T64,T14	INPUT
tl_o.a_ready	Yes	Yes	T152,T64,T14	Yes	T152,T64,T14	OUTPUT
tl_o.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T14,T15,T299	Yes	T14,T15,T299	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T152,T14,T15	Yes	T152,T64,T14	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T152,T14,T15	Yes	T152,T64,T14	OUTPUT
tl_o.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T14,*T15,*T299	Yes	T14,T15,T299	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T152,T64,T14	Yes	T152,T64,T14	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T152,T64,T65	Yes	T152,T64,T65	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T88,T89,T90	Yes	T88,T89,T90	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T88,T89,T90	Yes	T88,T89,T90	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T152,T64,T65	Yes	T152,T64,T65	OUTPUT
cio_rx_i	Yes	Yes	T14,T15,T299	Yes	T14,T15,T299	INPUT
cio_tx_o	Yes	Yes	T14,T15,T299	Yes	T14,T15,T299	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T14,T15,T299	Yes	T14,T15,T299	OUTPUT
intr_rx_watermark_o	Yes	Yes	T14,T15,T299	Yes	T14,T15,T299	OUTPUT
intr_tx_empty_o	Yes	Yes	T14,T15,T299	Yes	T14,T15,T299	OUTPUT
intr_rx_overflow_o	Yes	Yes	T14,T15,T299	Yes	T14,T15,T299	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T298,T303,T309	Yes	T298,T303,T309	OUTPUT
intr_rx_break_err_o	Yes	Yes	T298,T303,T309	Yes	T298,T303,T309	OUTPUT
intr_rx_timeout_o	Yes	Yes	T298,T303,T309	Yes	T298,T303,T309	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T298,T303,T309	Yes	T298,T303,T309	OUTPUT

*Tests covering at least one bit in the range