Unified Coverage Report :: Module :: rv_core_ibex

Module : rv_core_ibex

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.54	96.47	89.29	98.77		100.00	68.18

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex	90.79	96.47	89.29	100.00		100.00	68.18

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.79	96.47	89.29	100.00		100.00	68.18

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.35	97.52	95.25	98.69		98.13	92.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.46	92.83		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
fifo_d	100.00	100.00	100.00			100.00	100.00
fifo_i	93.75	75.00	100.00			100.00	100.00
gen_alert_senders[0].u_alert_sender	100.00			100.00
gen_alert_senders[1].u_alert_sender	100.00			100.00
gen_alert_senders[2].u_alert_sender	100.00			100.00
gen_alert_senders[3].u_alert_sender	75.00			75.00
tl_adapter_host_d_ibex	91.79	95.35	81.82			90.00	100.00
tl_adapter_host_i_ibex	87.90	90.48	72.22			88.89	100.00
u_alert_nmi_sync	100.00	100.00				100.00
u_core	96.63			96.63
u_core_sleeping_buf	100.00	100.00
u_dbus_trans	96.36	100.00	92.59			100.00	92.86
u_edn_if	89.08	100.00	86.44			94.87	75.00
u_ibus_trans	96.36	100.00	92.59			100.00	92.86
u_intr_timer_sync	100.00	100.00				100.00
u_lc_sync	100.00	100.00				100.00	100.00
u_prim_buf_irq	100.00	100.00
u_prim_esc_receiver	100.00			100.00
u_prim_lc_sender	100.00	100.00				100.00
u_prim_sync_reqack_data	91.67	100.00	66.67			100.00	100.00
u_pwrmgr_sync	100.00	100.00				100.00	100.00
u_reg_cfg	99.20	98.69	98.55			99.58	100.00
u_sim_win_rsp	80.88	77.55	68.18			77.78	100.00
u_tlul_req_buf	100.00	100.00
u_tlul_rsp_buf	100.00	100.00
u_wdog_nmi_sync	100.00	100.00				100.00

Line Coverage for Module : rv_core_ibex

	Line No.	Total	Covered	Percent
TOTAL		85	82	96.47
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
ALWAYS	488	3	3	100.00
CONT_ASSIGN	508	1	1	100.00
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	510	1	1	100.00
CONT_ASSIGN	511	1	1	100.00
ALWAYS	514	8	8	100.00
CONT_ASSIGN	698	1	1	100.00
CONT_ASSIGN	698	1	1	100.00
CONT_ASSIGN	699	1	1	100.00
CONT_ASSIGN	699	1	1	100.00
CONT_ASSIGN	700	1	1	100.00
CONT_ASSIGN	700	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	705	1	1	100.00
CONT_ASSIGN	705	1	1	100.00
CONT_ASSIGN	706	1	1	100.00
CONT_ASSIGN	706	1	1	100.00
CONT_ASSIGN	713	1	1	100.00
CONT_ASSIGN	714	1	1	100.00
CONT_ASSIGN	715	1	1	100.00
CONT_ASSIGN	718	1	1	100.00
CONT_ASSIGN	720	1	1	100.00
CONT_ASSIGN	722	1	1	100.00
CONT_ASSIGN	724	1	1	100.00
CONT_ASSIGN	731	1	1	100.00
CONT_ASSIGN	733	1	1	100.00
CONT_ASSIGN	735	1	1	100.00
CONT_ASSIGN	737	1	1	100.00
CONT_ASSIGN	747	1	1	100.00
CONT_ASSIGN	748	1	1	100.00
CONT_ASSIGN	749	1	1	100.00
CONT_ASSIGN	750	1	1	100.00
CONT_ASSIGN	753	1	1	100.00
CONT_ASSIGN	756	1	1	100.00
ALWAYS	788	11	11	100.00
ALWAYS	804	7	7	100.00
CONT_ASSIGN	815	1	1	100.00
CONT_ASSIGN	834	1	1	100.00
CONT_ASSIGN	835	1	1	100.00
CONT_ASSIGN	836	1	1	100.00
CONT_ASSIGN	839	1	0	0.00
CONT_ASSIGN	843	0	0
CONT_ASSIGN	882	1	1	100.00
ALWAYS	941	0	0
CONT_ASSIGN	982	1	0	0.00
CONT_ASSIGN	984	1	0	0.00
CONT_ASSIGN	986	1	1	100.00
CONT_ASSIGN	988	1	1	100.00
CONT_ASSIGN	990	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
202	1	1
203	1	1
216	1	1
217	1	1
218	1	1
225	1	1
263	1	1
265	1	1
268	1	1
342	1	1
348	1	1
363	1	1
488	1	1
489	1	1
491	1	1
508	1	1
509	1	1
510	1	1
511	1	1
514	1	1
515	1	1
516	1	1
517	1	1
518	1	1
519	1	1
520	1	1
521	1	1
			MISSING_ELSE
698	2	2
699	2	2
700	2	2
704	2	2
705	2	2
706	2	2
713	1	1
714	1	1
715	1	1
718	1	1
720	1	1
722	1	1
724	1	1
731	1	1
733	1	1
735	1	1
737	1	1
747	1	1
748	1	1
749	1	1
750	1	1
753	1	1
756	1	1
788	1	1
789	1	1
790	1	1
792	1	1
793	1	1
794	1	1
795	1	1
796	1	1
797	1	1
798	1	1
799	1	1
			MISSING_ELSE
804	1	1
805	1	1
806	1	1
807	1	1
809	1	1
810	1	1
811	1	1
815	1	1
834	1	1
835	1	1
836	1	1
839	0	1
843		unreachable
882	1	1
941		unreachable
942		unreachable
943		unreachable
944		unreachable
			==> MISSING_ELSE
982	0	1
984	0	1
986	1	1
988	1	1
990	1	1

---

Cond Coverage for Module : rv_core_ibex

	Total	Covered	Percent
Conditions	28	25	89.29
Logical	28	25	89.29
Non-Logical	0	0
Event	0	0

 LINE       216
 EXPRESSION (ibus_intg_err | dbus_intg_err | alert_major_bus)
             ------1------   ------2------   -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T91,T178,T233
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       217
 EXPRESSION (alert_major_internal | double_fault)
             ----------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T102,T234,T235
1	0	Covered	T3,T6,T152

 LINE       348
 EXPRESSION (fatal_core_err ? Off : local_fetch_enable_q)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T6,T152

 LINE       731
 EXPRESSION (reg2hw.alert_test.fatal_sw_err.q & reg2hw.alert_test.fatal_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T152,T53,T64
1	0	Covered	T1,T2,T3
1	1	Covered	T53,T64,T65

 LINE       733
 EXPRESSION (reg2hw.alert_test.recov_sw_err.q & reg2hw.alert_test.recov_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T53,T64,T65
1	0	Covered	T1,T2,T3
1	1	Covered	T152,T64,T65

 LINE       735
 EXPRESSION (reg2hw.alert_test.fatal_hw_err.q & reg2hw.alert_test.fatal_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T152,T53,T64
1	0	Covered	T1,T2,T3
1	1	Covered	T64,T65,T66

 LINE       737
 EXPRESSION (reg2hw.alert_test.recov_hw_err.q & reg2hw.alert_test.recov_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T152,T53,T64
1	0	Covered	T1,T2,T3
1	1	Covered	T53,T64,T65

 LINE       749
 EXPRESSION (intg_err | fatal_intg_err | fatal_core_err)
             ----1---   -------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T3,T6,T152
0	1	0	Covered	T91,T178,T233
1	0	0	Covered	T236,T237,T238

 LINE       796
 EXPRESSION (edn_req && edn_ack)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Toggle Coverage for Module : rv_core_ibex

	Total	Covered	Percent
Totals	121	117	96.69
Total Bits	1624	1604	98.77
Total Bits 0->1	812	802	98.77
Total Bits 1->0	812	802	98.77

Ports	121	117	96.69
Port Bits	1624	1604	98.77
Port Bits 0->1	812	802	98.77
Port Bits 1->0	812	802	98.77

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T34	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T2,T3,T34	Yes	T1,T2,T3	INPUT
clk_esc_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_esc_ni	Yes	Yes	T2,T3,T34	Yes	T1,T2,T3	INPUT
rst_cpu_n_o	Yes	Yes	T2,T3,T34	Yes	T1,T2,T3	OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
hart_id_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
boot_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_o.d_ready	Yes	Yes	T80,T81,T239	Yes	T80,T81,T82	OUTPUT
corei_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
corei_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
corei_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_data[31:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
corei_tl_h_o.a_mask[3:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
corei_tl_h_o.a_address[31:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
corei_tl_h_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
corei_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
corei_tl_h_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_error	Yes	Yes	T2,T206,T87	Yes	T2,T206,T87	INPUT
corei_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T206,T233	Yes	T2,T206,T233	INPUT
corei_tl_h_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
corei_tl_h_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
corei_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_o.d_ready	Yes	Yes	T53,T85,T86	Yes	T53,T85,T86	OUTPUT
cored_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T85,T86,T240	Yes	T85,T86,T240	OUTPUT
cored_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_address[31:0]	Yes	Yes	T85,T86,T240	Yes	T85,T86,T240	OUTPUT
cored_tl_h_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_size[1:0]	Yes	Yes	T85,T86,T240	Yes	T85,T86,T240	OUTPUT
cored_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_error	Yes	Yes	T2,T34,T71	Yes	T2,T34,T71	INPUT
cored_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
cored_tl_h_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
cored_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
irq_software_i	Yes	Yes	T115,T201,T241	Yes	T115,T201,T241	INPUT
irq_timer_i	Yes	Yes	T1,T242,T243	Yes	T1,T242,T243	INPUT
irq_external_i	Yes	Yes	T1,T2,T34	Yes	T1,T2,T34	INPUT
esc_tx_i.esc_n	Yes	Yes	T2,T34,T71	Yes	T2,T34,T71	INPUT
esc_tx_i.esc_p	Yes	Yes	T2,T34,T71	Yes	T2,T34,T71	INPUT
esc_rx_o.resp_n	Yes	Yes	T2,T34,T71	Yes	T2,T34,T71	OUTPUT
esc_rx_o.resp_p	Yes	Yes	T2,T34,T71	Yes	T2,T34,T71	OUTPUT
nmi_wdog_i	Yes	Yes	T4,T127,T71	Yes	T4,T127,T71	INPUT
debug_req_i	Yes	Yes	T83,T84,T244	Yes	T83,T84,T244	INPUT
crash_dump_o.current.exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.last_data_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.next_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.current_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_valid	Unreachable	Unreachable		Unreachable		OUTPUT
lc_cpu_en_i[3:0]	Yes	Yes	T2,T3,T34	Yes	T1,T2,T3	INPUT
pwrmgr_cpu_en_i[3:0]	Yes	Yes	T2,T3,T34	Yes	T1,T2,T3	INPUT
pwrmgr_o.core_sleeping	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[7:0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	INPUT
cfg_tl_d_i.a_address[15:8]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[20:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[24]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_source[5:0]	Yes	Yes	*T53,*T80,*T81	Yes	T53,T80,T81	INPUT
cfg_tl_d_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
cfg_tl_d_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
cfg_tl_d_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_error	Yes	Yes	T53,T80,T81	Yes	T53,T80,T81	OUTPUT
cfg_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T34	Yes	T1,T2,T34	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_data[31:0]	Yes	Yes	T1,T2,T34	Yes	T1,T2,T34	OUTPUT
cfg_tl_d_o.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
cfg_tl_d_o.d_source[5:0]	Yes	Yes	*T53,*T80,*T81	Yes	T53,T80,T81	OUTPUT
cfg_tl_d_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
cfg_tl_d_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o.edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
edn_i.edn_fips	Yes	Yes	T116,T106,T245	Yes	T116,T106,T245	INPUT
edn_i.edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_otp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_otp_ni	Yes	Yes	T2,T3,T34	Yes	T1,T2,T3	INPUT
icache_otp_key_o.req	Yes	Yes	T175,T176,T177	Yes	T175,T176,T177	OUTPUT
icache_otp_key_i.seed_valid	Yes	Yes	T2,T3,T34	Yes	T1,T2,T3	INPUT
icache_otp_key_i.nonce[127:0]	Yes	Yes	T2,T3,T34	Yes	T1,T2,T3	INPUT
icache_otp_key_i.key[127:0]	Yes	Yes	T1,T3,T34	Yes	T3,T34,T4	INPUT
icache_otp_key_i.ack	Yes	Yes	T175,T176,T177	Yes	T175,T176,T177	INPUT
fpga_info_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T53,T64,T65	Yes	T53,T64,T65	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T88,T89,T90	Yes	T88,T89,T90	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T88,T89,T90	Yes	T88,T89,T90	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T152,T53,T64	Yes	T152,T53,T64	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T88,T89,T159	Yes	T88,T89,T159	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T88,T89,T159	Yes	T88,T89,T159	INPUT
alert_rx_i[2].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T91,T178,T64	Yes	T91,T178,T64	INPUT
alert_rx_i[2].ping_n	Yes	Yes	T88,T89,T159	Yes	T89,T159,T90	INPUT
alert_rx_i[2].ping_p	Yes	Yes	T89,T159,T90	Yes	T88,T89,T159	INPUT
alert_rx_i[3].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T53,T64,T65	Yes	T53,T64,T65	INPUT
alert_rx_i[3].ping_n	Yes	Yes	T88,T89,T90	Yes	T88,T90,T157	INPUT
alert_rx_i[3].ping_p	Yes	Yes	T88,T90,T157	Yes	T88,T89,T90	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T53,T64,T65	Yes	T53,T64,T65	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T152,T53,T64	Yes	T152,T53,T64	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T91,T178,T64	Yes	T91,T178,T64	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T53,T64,T65	Yes	T53,T64,T65	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : rv_core_ibex

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	348	2	2	100.00
IF	488	2	2	100.00
IF	514	3	3	100.00
IF	792	3	3	100.00
IF	804	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	348	(fatal_core_err) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T152
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	488	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	514	if ((!rst_ni))
-2-:	518	if (double_fault)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T102,T234,T235
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	792	if (reg2hw.rnd_data.re)
-2-:	796	if ((edn_req && edn_ack))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T34
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	804	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : rv_core_ibex

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	15	68.18
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	15	68.18

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FpvSecCmIbexFetchEnable0_A	430652425	8	0	0
FpvSecCmIbexFetchEnable1_A	430652425	23811499	0	96
FpvSecCmIbexFetchEnable2_A	430652425	62067097	0	80
FpvSecCmIbexFetchEnable3Rev_A	430652425	363765138	0	1880
FpvSecCmIbexFetchEnable3_A	430652425	363766900	0	1773
FpvSecCmIbexInstrIntgErrCheck_A	430652425	76	0	0
FpvSecCmIbexLoadRespIntgErrCheck_A	430652425	593	0	0
FpvSecCmIbexLockstepResetCountAlertCheck_A	430652425	0	0	0
FpvSecCmIbexPcMismatchCheck_A	430652425	0	0	0
FpvSecCmIbexRfEccErrCheck_A	430652425	0	0	0
FpvSecCmIbexStoreRespIntgErrCheck_A	430652425	0	0	0
FpvSecCmRegWeOnehotCheck_A	430652425	6	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A	430652425	0	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A	430652425	0	0	0
FpvSecCmRvCoreRegWeOnehotCheck_A	430652425	0	0	0
g_instr_intg_err_assert_signals.AssertConnected_A	949	949	0	0
g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A	949	949	0	0
g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A	949	949	0	0
g_pc_mismatch_alert_o_assert_signals.AssertConnected_A	949	949	0	0
g_rf_ecc_err_comb_assert_signals.AssertConnected_A	949	949	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A	430652425	80	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A	430652425	182	0	0

FpvSecCmIbexFetchEnable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430652425	8	0	0
T13	92667	0	0	0
T102	283737	1	0	0
T103	644645	0	0	0
T104	210905	0	0	0
T105	289789	0	0	0
T106	354409	0	0	0
T110	137149	0	0	0
T111	180491	0	0	0
T112	446816	0	0	0
T113	131950	0	0	0
T234	0	1	0	0
T235	0	1	0	0
T246	0	1	0	0
T247	0	1	0	0
T248	0	1	0	0
T249	0	1	0	0
T250	0	1	0	0

FpvSecCmIbexFetchEnable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430652425	23811499	0	96
T1	190937	9931	0	0
T2	290149	80629	0	0
T3	194599	19854	0	0
T4	164741	158876	0	0
T5	741157	19846	0	0
T34	226353	40598	0	0
T46	0	0	0	2
T47	0	0	0	2
T51	0	0	0	2
T53	0	0	0	2
T67	206813	9927	0	0
T70	0	0	0	2
T91	165209	19854	0	0
T92	65993	9923	0	0
T93	190774	9931	0	0
T162	0	0	0	2
T251	0	0	0	2
T252	0	0	0	2
T253	0	0	0	2
T254	0	0	0	2

FpvSecCmIbexFetchEnable2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430652425	62067097	0	80
T1	190937	34775	0	0
T2	290149	69554	0	0
T3	194599	69554	0	0
T4	164741	561505	0	0
T5	741157	69550	0	0
T8	0	0	0	2
T34	226353	69554	0	0
T46	0	0	0	2
T47	0	0	0	2
T51	0	0	0	2
T53	0	0	0	2
T67	206813	36786	0	0
T91	165209	69555	0	0
T92	65993	34775	0	0
T93	190774	36293	0	0
T253	0	0	0	2
T254	0	0	0	2
T255	0	0	0	2
T256	0	0	0	2
T257	0	0	0	2

FpvSecCmIbexFetchEnable3Rev_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430652425	363765138	0	1880
T1	190937	156097	0	2
T2	290149	159706	0	2
T3	194599	124923	0	2
T4	164741	108515	0	2
T5	741157	734191	0	2
T34	226353	135936	0	2
T67	206813	169961	0	2
T91	165209	95532	0	2
T92	65993	31160	0	2
T93	190774	154419	0	2

FpvSecCmIbexFetchEnable3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430652425	363766900	0	1773
T1	190937	156098	0	2
T2	290149	159708	0	2
T3	194599	124925	0	2
T4	164741	108516	0	2
T5	741157	734191	0	2
T34	226353	135938	0	2
T67	206813	169963	0	2
T91	165209	95534	0	2
T92	65993	31161	0	2
T93	190774	154421	0	2

FpvSecCmIbexInstrIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430652425	76	0	0
T258	295391	76	0	0
T259	700208	0	0	0
T260	157280	0	0	0
T261	79312	0	0	0
T262	42221	0	0	0
T263	380857	0	0	0
T264	287409	0	0	0
T265	346627	0	0	0
T266	420639	0	0	0
T267	192319	0	0	0

FpvSecCmIbexLoadRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430652425	593	0	0
T6	603083	0	0	0
T67	206813	0	0	0
T71	155760	0	0	0
T91	165209	32	0	0
T92	65993	0	0	0
T93	190774	0	0	0
T121	0	32	0	0
T127	380248	0	0	0
T174	0	32	0	0
T178	0	98	0	0
T186	263574	0	0	0
T191	623601	0	0	0
T233	0	1	0	0
T268	0	1	0	0
T269	0	1	0	0
T270	0	100	0	0
T271	0	100	0	0
T272	0	31	0	0
T273	272897	0	0	0

FpvSecCmIbexLockstepResetCountAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430652425	0	0	0

FpvSecCmIbexPcMismatchCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430652425	0	0	0

FpvSecCmIbexRfEccErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430652425	0	0	0

FpvSecCmIbexStoreRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430652425	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430652425	6	0	0
T46	125660	0	0	0
T171	968174	0	0	0
T209	219936	0	0	0
T236	139082	1	0	0
T237	148334	1	0	0
T238	0	1	0	0
T242	97778	0	0	0
T243	77356	0	0	0
T274	0	1	0	0
T275	0	1	0	0
T276	0	1	0	0
T277	482456	0	0	0
T278	230416	0	0	0
T279	191888	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430652425	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430652425	0	0	0

FpvSecCmRvCoreRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430652425	0	0	0

g_instr_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	949	949	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T34	1	1	0	0
T67	1	1	0	0
T91	1	1	0	0
T92	1	1	0	0
T93	1	1	0	0

g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	949	949	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T34	1	1	0	0
T67	1	1	0	0
T91	1	1	0	0
T92	1	1	0	0
T93	1	1	0	0

g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	949	949	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T34	1	1	0	0
T67	1	1	0	0
T91	1	1	0	0
T92	1	1	0	0
T93	1	1	0	0

g_pc_mismatch_alert_o_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	949	949	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T34	1	1	0	0
T67	1	1	0	0
T91	1	1	0	0
T92	1	1	0	0
T93	1	1	0	0

g_rf_ecc_err_comb_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	949	949	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T34	1	1	0	0
T67	1	1	0	0
T91	1	1	0	0
T92	1	1	0	0
T93	1	1	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430652425	80	0	0
T175	71792	8	0	0
T176	0	12	0	0
T177	0	16	0	0
T192	238140	0	0	0
T245	110160	0	0	0
T280	0	16	0	0
T281	0	12	0	0
T282	0	16	0	0
T283	279215	0	0	0
T284	321510	0	0	0
T285	209151	0	0	0
T286	131746	0	0	0
T287	225439	0	0	0
T288	214204	0	0	0
T289	111390	0	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430652425	182	0	0
T175	71792	2	0	0
T176	0	3	0	0
T177	0	42	0	0
T183	0	16	0	0
T184	0	16	0	0
T185	0	16	0	0
T192	238140	0	0	0
T245	110160	0	0	0
T280	0	42	0	0
T281	0	3	0	0
T282	0	42	0	0
T283	279215	0	0	0
T284	321510	0	0	0
T285	209151	0	0	0
T286	131746	0	0	0
T287	225439	0	0	0
T288	214204	0	0	0
T289	111390	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Line No.	Total	Covered	Percent
TOTAL		85	82	96.47
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
ALWAYS	488	3	3	100.00
CONT_ASSIGN	508	1	1	100.00
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	510	1	1	100.00
CONT_ASSIGN	511	1	1	100.00
ALWAYS	514	8	8	100.00
CONT_ASSIGN	698	1	1	100.00
CONT_ASSIGN	698	1	1	100.00
CONT_ASSIGN	699	1	1	100.00
CONT_ASSIGN	699	1	1	100.00
CONT_ASSIGN	700	1	1	100.00
CONT_ASSIGN	700	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	705	1	1	100.00
CONT_ASSIGN	705	1	1	100.00
CONT_ASSIGN	706	1	1	100.00
CONT_ASSIGN	706	1	1	100.00
CONT_ASSIGN	713	1	1	100.00
CONT_ASSIGN	714	1	1	100.00
CONT_ASSIGN	715	1	1	100.00
CONT_ASSIGN	718	1	1	100.00
CONT_ASSIGN	720	1	1	100.00
CONT_ASSIGN	722	1	1	100.00
CONT_ASSIGN	724	1	1	100.00
CONT_ASSIGN	731	1	1	100.00
CONT_ASSIGN	733	1	1	100.00
CONT_ASSIGN	735	1	1	100.00
CONT_ASSIGN	737	1	1	100.00
CONT_ASSIGN	747	1	1	100.00
CONT_ASSIGN	748	1	1	100.00
CONT_ASSIGN	749	1	1	100.00
CONT_ASSIGN	750	1	1	100.00
CONT_ASSIGN	753	1	1	100.00
CONT_ASSIGN	756	1	1	100.00
ALWAYS	788	11	11	100.00
ALWAYS	804	7	7	100.00
CONT_ASSIGN	815	1	1	100.00
CONT_ASSIGN	834	1	1	100.00
CONT_ASSIGN	835	1	1	100.00
CONT_ASSIGN	836	1	1	100.00
CONT_ASSIGN	839	1	0	0.00
CONT_ASSIGN	843	0	0
CONT_ASSIGN	882	1	1	100.00
ALWAYS	941	0	0
CONT_ASSIGN	982	1	0	0.00
CONT_ASSIGN	984	1	0	0.00
CONT_ASSIGN	986	1	1	100.00
CONT_ASSIGN	988	1	1	100.00
CONT_ASSIGN	990	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
202	1	1
203	1	1
216	1	1
217	1	1
218	1	1
225	1	1
263	1	1
265	1	1
268	1	1
342	1	1
348	1	1
363	1	1
488	1	1
489	1	1
491	1	1
508	1	1
509	1	1
510	1	1
511	1	1
514	1	1
515	1	1
516	1	1
517	1	1
518	1	1
519	1	1
520	1	1
521	1	1
			MISSING_ELSE
698	2	2
699	2	2
700	2	2
704	2	2
705	2	2
706	2	2
713	1	1
714	1	1
715	1	1
718	1	1
720	1	1
722	1	1
724	1	1
731	1	1
733	1	1
735	1	1
737	1	1
747	1	1
748	1	1
749	1	1
750	1	1
753	1	1
756	1	1
788	1	1
789	1	1
790	1	1
792	1	1
793	1	1
794	1	1
795	1	1
796	1	1
797	1	1
798	1	1
799	1	1
			MISSING_ELSE
804	1	1
805	1	1
806	1	1
807	1	1
809	1	1
810	1	1
811	1	1
815	1	1
834	1	1
835	1	1
836	1	1
839	0	1
843		unreachable
882	1	1
941		unreachable
942		unreachable
943		unreachable
944		unreachable
			==> MISSING_ELSE
982	0	1
984	0	1
986	1	1
988	1	1
990	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Covered	Percent
Conditions	28	25	89.29
Logical	28	25	89.29
Non-Logical	0	0
Event	0	0

 LINE       216
 EXPRESSION (ibus_intg_err | dbus_intg_err | alert_major_bus)
             ------1------   ------2------   -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T91,T178,T233
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       217
 EXPRESSION (alert_major_internal | double_fault)
             ----------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T102,T234,T235
1	0	Covered	T3,T6,T152

 LINE       348
 EXPRESSION (fatal_core_err ? Off : local_fetch_enable_q)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T6,T152

 LINE       731
 EXPRESSION (reg2hw.alert_test.fatal_sw_err.q & reg2hw.alert_test.fatal_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T152,T53,T64
1	0	Covered	T1,T2,T3
1	1	Covered	T53,T64,T65

 LINE       733
 EXPRESSION (reg2hw.alert_test.recov_sw_err.q & reg2hw.alert_test.recov_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T53,T64,T65
1	0	Covered	T1,T2,T3
1	1	Covered	T152,T64,T65

 LINE       735
 EXPRESSION (reg2hw.alert_test.fatal_hw_err.q & reg2hw.alert_test.fatal_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T152,T53,T64
1	0	Covered	T1,T2,T3
1	1	Covered	T64,T65,T66

 LINE       737
 EXPRESSION (reg2hw.alert_test.recov_hw_err.q & reg2hw.alert_test.recov_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T152,T53,T64
1	0	Covered	T1,T2,T3
1	1	Covered	T53,T64,T65

 LINE       749
 EXPRESSION (intg_err | fatal_intg_err | fatal_core_err)
             ----1---   -------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T3,T6,T152
0	1	0	Covered	T91,T178,T233
1	0	0	Covered	T236,T237,T238

 LINE       796
 EXPRESSION (edn_req && edn_ack)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Covered	Percent
Totals	117	117	100.00
Total Bits	1604	1604	100.00
Total Bits 0->1	802	802	100.00
Total Bits 1->0	802	802	100.00

Ports	117	117	100.00
Port Bits	1604	1604	100.00
Port Bits 0->1	802	802	100.00
Port Bits 1->0	802	802	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T34	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T2,T3,T34	Yes	T1,T2,T3	INPUT
clk_esc_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_esc_ni	Yes	Yes	T2,T3,T34	Yes	T1,T2,T3	INPUT
rst_cpu_n_o	Yes	Yes	T2,T3,T34	Yes	T1,T2,T3	OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.rf_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
hart_id_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
boot_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_o.d_ready	Yes	Yes	T80,T81,T239	Yes	T80,T81,T82	OUTPUT
corei_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
corei_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
corei_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_data[31:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
corei_tl_h_o.a_mask[3:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
corei_tl_h_o.a_address[31:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
corei_tl_h_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
corei_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
corei_tl_h_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_error	Yes	Yes	T2,T206,T87	Yes	T2,T206,T87	INPUT
corei_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T206,T233	Yes	T2,T206,T233	INPUT
corei_tl_h_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
corei_tl_h_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
corei_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_o.d_ready	Yes	Yes	T53,T85,T86	Yes	T53,T85,T86	OUTPUT
cored_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T85,T86,T240	Yes	T85,T86,T240	OUTPUT
cored_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_address[31:0]	Yes	Yes	T85,T86,T240	Yes	T85,T86,T240	OUTPUT
cored_tl_h_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_size[1:0]	Yes	Yes	T85,T86,T240	Yes	T85,T86,T240	OUTPUT
cored_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_error	Yes	Yes	T2,T34,T71	Yes	T2,T34,T71	INPUT
cored_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
cored_tl_h_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
cored_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
irq_software_i	Yes	Yes	T115,T201,T241	Yes	T115,T201,T241	INPUT
irq_timer_i	Yes	Yes	T1,T242,T243	Yes	T1,T242,T243	INPUT
irq_external_i	Yes	Yes	T1,T2,T34	Yes	T1,T2,T34	INPUT
esc_tx_i.esc_n	Yes	Yes	T2,T34,T71	Yes	T2,T34,T71	INPUT
esc_tx_i.esc_p	Yes	Yes	T2,T34,T71	Yes	T2,T34,T71	INPUT
esc_rx_o.resp_n	Yes	Yes	T2,T34,T71	Yes	T2,T34,T71	OUTPUT
esc_rx_o.resp_p	Yes	Yes	T2,T34,T71	Yes	T2,T34,T71	OUTPUT
nmi_wdog_i	Yes	Yes	T4,T127,T71	Yes	T4,T127,T71	INPUT
debug_req_i	Yes	Yes	T83,T84,T244	Yes	T83,T84,T244	INPUT
crash_dump_o.current.exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.last_data_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.next_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.current_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_valid	Unreachable	Unreachable		Unreachable		OUTPUT
lc_cpu_en_i[3:0]	Yes	Yes	T2,T3,T34	Yes	T1,T2,T3	INPUT
pwrmgr_cpu_en_i[3:0]	Yes	Yes	T2,T3,T34	Yes	T1,T2,T3	INPUT
pwrmgr_o.core_sleeping	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[7:0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	INPUT
cfg_tl_d_i.a_address[15:8]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[20:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[24]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_source[5:0]	Yes	Yes	*T53,*T80,*T81	Yes	T53,T80,T81	INPUT
cfg_tl_d_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
cfg_tl_d_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
cfg_tl_d_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_error	Yes	Yes	T53,T80,T81	Yes	T53,T80,T81	OUTPUT
cfg_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T34	Yes	T1,T2,T34	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_data[31:0]	Yes	Yes	T1,T2,T34	Yes	T1,T2,T34	OUTPUT
cfg_tl_d_o.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
cfg_tl_d_o.d_source[5:0]	Yes	Yes	*T53,*T80,*T81	Yes	T53,T80,T81	OUTPUT
cfg_tl_d_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
cfg_tl_d_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o.edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
edn_i.edn_fips	Yes	Yes	T116,T106,T245	Yes	T116,T106,T245	INPUT
edn_i.edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_otp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_otp_ni	Yes	Yes	T2,T3,T34	Yes	T1,T2,T3	INPUT
icache_otp_key_o.req	Yes	Yes	T175,T176,T177	Yes	T175,T176,T177	OUTPUT
icache_otp_key_i.seed_valid	Yes	Yes	T2,T3,T34	Yes	T1,T2,T3	INPUT
icache_otp_key_i.nonce[127:0]	Yes	Yes	T2,T3,T34	Yes	T1,T2,T3	INPUT
icache_otp_key_i.key[127:0]	Yes	Yes	T1,T3,T34	Yes	T3,T34,T4	INPUT
icache_otp_key_i.ack	Yes	Yes	T175,T176,T177	Yes	T175,T176,T177	INPUT
fpga_info_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T53,T64,T65	Yes	T53,T64,T65	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T88,T89,T90	Yes	T88,T89,T90	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T88,T89,T90	Yes	T88,T89,T90	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T152,T53,T64	Yes	T152,T53,T64	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T88,T89,T159	Yes	T88,T89,T159	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T88,T89,T159	Yes	T88,T89,T159	INPUT
alert_rx_i[2].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T91,T178,T64	Yes	T91,T178,T64	INPUT
alert_rx_i[2].ping_n	Yes	Yes	T88,T89,T159	Yes	T89,T159,T90	INPUT
alert_rx_i[2].ping_p	Yes	Yes	T89,T159,T90	Yes	T88,T89,T159	INPUT
alert_rx_i[3].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T53,T64,T65	Yes	T53,T64,T65	INPUT
alert_rx_i[3].ping_n	Yes	Yes	T88,T89,T90	Yes	T88,T90,T157	INPUT
alert_rx_i[3].ping_p	Yes	Yes	T88,T90,T157	Yes	T88,T89,T90	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T53,T64,T65	Yes	T53,T64,T65	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T152,T53,T64	Yes	T152,T53,T64	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T91,T178,T64	Yes	T91,T178,T64	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T53,T64,T65	Yes	T53,T64,T65	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	348	2	2	100.00
IF	488	2	2	100.00
IF	514	3	3	100.00
IF	792	3	3	100.00
IF	804	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	348	(fatal_core_err) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T152
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	488	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	514	if ((!rst_ni))
-2-:	518	if (double_fault)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T102,T234,T235
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	792	if (reg2hw.rnd_data.re)
-2-:	796	if ((edn_req && edn_ack))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T34
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	804	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	15	68.18
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	15	68.18

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FpvSecCmIbexFetchEnable0_A	430652425	8	0	0
FpvSecCmIbexFetchEnable1_A	430652425	23811499	0	96
FpvSecCmIbexFetchEnable2_A	430652425	62067097	0	80
FpvSecCmIbexFetchEnable3Rev_A	430652425	363765138	0	1880
FpvSecCmIbexFetchEnable3_A	430652425	363766900	0	1773
FpvSecCmIbexInstrIntgErrCheck_A	430652425	76	0	0
FpvSecCmIbexLoadRespIntgErrCheck_A	430652425	593	0	0
FpvSecCmIbexLockstepResetCountAlertCheck_A	430652425	0	0	0
FpvSecCmIbexPcMismatchCheck_A	430652425	0	0	0
FpvSecCmIbexRfEccErrCheck_A	430652425	0	0	0
FpvSecCmIbexStoreRespIntgErrCheck_A	430652425	0	0	0
FpvSecCmRegWeOnehotCheck_A	430652425	6	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A	430652425	0	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A	430652425	0	0	0
FpvSecCmRvCoreRegWeOnehotCheck_A	430652425	0	0	0
g_instr_intg_err_assert_signals.AssertConnected_A	949	949	0	0
g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A	949	949	0	0
g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A	949	949	0	0
g_pc_mismatch_alert_o_assert_signals.AssertConnected_A	949	949	0	0
g_rf_ecc_err_comb_assert_signals.AssertConnected_A	949	949	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A	430652425	80	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A	430652425	182	0	0

FpvSecCmIbexFetchEnable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430652425	8	0	0
T13	92667	0	0	0
T102	283737	1	0	0
T103	644645	0	0	0
T104	210905	0	0	0
T105	289789	0	0	0
T106	354409	0	0	0
T110	137149	0	0	0
T111	180491	0	0	0
T112	446816	0	0	0
T113	131950	0	0	0
T234	0	1	0	0
T235	0	1	0	0
T246	0	1	0	0
T247	0	1	0	0
T248	0	1	0	0
T249	0	1	0	0
T250	0	1	0	0

FpvSecCmIbexFetchEnable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430652425	23811499	0	96
T1	190937	9931	0	0
T2	290149	80629	0	0
T3	194599	19854	0	0
T4	164741	158876	0	0
T5	741157	19846	0	0
T34	226353	40598	0	0
T46	0	0	0	2
T47	0	0	0	2
T51	0	0	0	2
T53	0	0	0	2
T67	206813	9927	0	0
T70	0	0	0	2
T91	165209	19854	0	0
T92	65993	9923	0	0
T93	190774	9931	0	0
T162	0	0	0	2
T251	0	0	0	2
T252	0	0	0	2
T253	0	0	0	2
T254	0	0	0	2

FpvSecCmIbexFetchEnable2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430652425	62067097	0	80
T1	190937	34775	0	0
T2	290149	69554	0	0
T3	194599	69554	0	0
T4	164741	561505	0	0
T5	741157	69550	0	0
T8	0	0	0	2
T34	226353	69554	0	0
T46	0	0	0	2
T47	0	0	0	2
T51	0	0	0	2
T53	0	0	0	2
T67	206813	36786	0	0
T91	165209	69555	0	0
T92	65993	34775	0	0
T93	190774	36293	0	0
T253	0	0	0	2
T254	0	0	0	2
T255	0	0	0	2
T256	0	0	0	2
T257	0	0	0	2

FpvSecCmIbexFetchEnable3Rev_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430652425	363765138	0	1880
T1	190937	156097	0	2
T2	290149	159706	0	2
T3	194599	124923	0	2
T4	164741	108515	0	2
T5	741157	734191	0	2
T34	226353	135936	0	2
T67	206813	169961	0	2
T91	165209	95532	0	2
T92	65993	31160	0	2
T93	190774	154419	0	2

FpvSecCmIbexFetchEnable3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430652425	363766900	0	1773
T1	190937	156098	0	2
T2	290149	159708	0	2
T3	194599	124925	0	2
T4	164741	108516	0	2
T5	741157	734191	0	2
T34	226353	135938	0	2
T67	206813	169963	0	2
T91	165209	95534	0	2
T92	65993	31161	0	2
T93	190774	154421	0	2

FpvSecCmIbexInstrIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430652425	76	0	0
T258	295391	76	0	0
T259	700208	0	0	0
T260	157280	0	0	0
T261	79312	0	0	0
T262	42221	0	0	0
T263	380857	0	0	0
T264	287409	0	0	0
T265	346627	0	0	0
T266	420639	0	0	0
T267	192319	0	0	0

FpvSecCmIbexLoadRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430652425	593	0	0
T6	603083	0	0	0
T67	206813	0	0	0
T71	155760	0	0	0
T91	165209	32	0	0
T92	65993	0	0	0
T93	190774	0	0	0
T121	0	32	0	0
T127	380248	0	0	0
T174	0	32	0	0
T178	0	98	0	0
T186	263574	0	0	0
T191	623601	0	0	0
T233	0	1	0	0
T268	0	1	0	0
T269	0	1	0	0
T270	0	100	0	0
T271	0	100	0	0
T272	0	31	0	0
T273	272897	0	0	0

FpvSecCmIbexLockstepResetCountAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430652425	0	0	0

FpvSecCmIbexPcMismatchCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430652425	0	0	0

FpvSecCmIbexRfEccErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430652425	0	0	0

FpvSecCmIbexStoreRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430652425	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430652425	6	0	0
T46	125660	0	0	0
T171	968174	0	0	0
T209	219936	0	0	0
T236	139082	1	0	0
T237	148334	1	0	0
T238	0	1	0	0
T242	97778	0	0	0
T243	77356	0	0	0
T274	0	1	0	0
T275	0	1	0	0
T276	0	1	0	0
T277	482456	0	0	0
T278	230416	0	0	0
T279	191888	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430652425	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430652425	0	0	0

FpvSecCmRvCoreRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430652425	0	0	0

g_instr_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	949	949	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T34	1	1	0	0
T67	1	1	0	0
T91	1	1	0	0
T92	1	1	0	0
T93	1	1	0	0

g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	949	949	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T34	1	1	0	0
T67	1	1	0	0
T91	1	1	0	0
T92	1	1	0	0
T93	1	1	0	0

g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	949	949	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T34	1	1	0	0
T67	1	1	0	0
T91	1	1	0	0
T92	1	1	0	0
T93	1	1	0	0

g_pc_mismatch_alert_o_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	949	949	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T34	1	1	0	0
T67	1	1	0	0
T91	1	1	0	0
T92	1	1	0	0
T93	1	1	0	0

g_rf_ecc_err_comb_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	949	949	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T34	1	1	0	0
T67	1	1	0	0
T91	1	1	0	0
T92	1	1	0	0
T93	1	1	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430652425	80	0	0
T175	71792	8	0	0
T176	0	12	0	0
T177	0	16	0	0
T192	238140	0	0	0
T245	110160	0	0	0
T280	0	16	0	0
T281	0	12	0	0
T282	0	16	0	0
T283	279215	0	0	0
T284	321510	0	0	0
T285	209151	0	0	0
T286	131746	0	0	0
T287	225439	0	0	0
T288	214204	0	0	0
T289	111390	0	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430652425	182	0	0
T175	71792	2	0	0
T176	0	3	0	0
T177	0	42	0	0
T183	0	16	0	0
T184	0	16	0	0
T185	0	16	0	0
T192	238140	0	0	0
T245	110160	0	0	0
T280	0	42	0	0
T281	0	3	0	0
T282	0	42	0	0
T283	279215	0	0	0
T284	321510	0	0	0
T285	209151	0	0	0
T286	131746	0	0	0
T287	225439	0	0	0
T288	214204	0	0	0
T289	111390	0	0	0