Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.46	92.83		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T2,T3,T34	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T2,T3,T34	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T2,T3,T34	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T2,T3,T34	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T2,T3,T34	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T80,T81,T239	Yes	T80,T81,T82	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T2,T206,T87	Yes	T2,T206,T87	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T2,T206,T233	Yes	T2,T206,T233	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T53,T85,T86	Yes	T53,T85,T86	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T85,T86,T240	Yes	T85,T86,T240	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T85,T86,T240	Yes	T85,T86,T240	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T2,T34,T71	Yes	T2,T34,T71	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T2,T3,T34	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T53,T76,T72	Yes	T53,T76,T72	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T34	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T34	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T53,T76,T72	Yes	T53,T76,T72	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T2,T3,T34	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T53,T76,T72	Yes	T53,T76,T72	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T2,T3,T34	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T53,T76,T72	Yes	T53,T76,T72	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T53,T76,T72	Yes	T53,T76,T72	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T53,T76,T72	Yes	T53,T76,T72	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T53,*T76,*T72	Yes	T53,T76,T72	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T53,T76,T72	Yes	T53,T76,T72	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T2,T3,T34	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T53,T80,T81	Yes	T53,T80,T81	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T53,T80,T81	Yes	T53,T80,T81	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T53,T80,T81	Yes	T53,T80,T81	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T53,T80,T81	Yes	T53,T80,T81	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T53,T80,T81	Yes	T53,T80,T81	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	*T53,T80,T81	Yes	T53,T80,T81	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T53,T80,T81	Yes	T53,T80,T81	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T53,T80,T81	Yes	T53,T80,T81	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T53,T80,T81	Yes	T53,T80,T81	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T53,T80,T81	Yes	T53,T80,T81	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T53,T80,T81	Yes	T53,T80,T81	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	*T53,T80,T81	Yes	T53,T80,T81	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T53,*T80,*T81	Yes	T53,T80,T81	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T53,T80,T81	Yes	T53,T80,T81	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T2,T3,T34	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T53,T83,T84	Yes	T53,T83,T84	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T53,T83,T84	Yes	T53,T83,T84	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T53,T83,T84	Yes	T53,T83,T84	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T53,T83,T84	Yes	T53,T83,T84	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T53,T83,T84	Yes	T53,T83,T84	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T83,*T84,*T244	Yes	T83,T84,T244	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T53,T83,T84	Yes	T53,T83,T84	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T2,T3,T34	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T83,T84,T244	Yes	T83,T84,T244	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T53,T83,T84	Yes	T53,T83,T84	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T34	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T83,*T84,*T244	Yes	T83,T84,T244	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T34	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T53,T83,T84	Yes	T53,T83,T84	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T48,T49,T50	Yes	T48,T49,T50	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T2,T3,T34	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T53,T64,T65	Yes	T53,T64,T65	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T53,T64,T406	Yes	T53,T64,T406	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T53,T64,T406	Yes	T53,T64,T406	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T53,T64,T65	Yes	T53,T64,T65	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T53,T64,T406	Yes	T53,T64,T406	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T53,*T80,*T81	Yes	T53,T80,T81	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T53,T64,T406	Yes	T53,T64,T406	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T53,T64,T406	Yes	T53,T64,T406	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T407,T408,T255	Yes	T407,T408,T255	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T53,T80,T81	Yes	T53,T64,T65	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T53,T407,T408	Yes	T53,T64,T65	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	*T53,*T80,*T81	Yes	T53,T80,T81	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T53,*T406,*T409	Yes	T53,T406,T409	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T53,T64,T406	Yes	T53,T64,T406	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T53,*T83,*T84	Yes	T53,T83,T84	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T53,T85,T86	Yes	T53,T85,T86	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	Yes	Yes	T34,T273,T206	Yes	T34,T273,T206	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T53,*T83,*T84	Yes	T53,T83,T84	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T1,T152,T64	Yes	T1,T152,T64	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T1,T152,T64	Yes	T1,T152,T64	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T152,T64	Yes	T1,T152,T64	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T152,T64	Yes	T1,T152,T64	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T1,T152,T64	Yes	T1,T152,T64	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T1,T152,T64	Yes	T1,T152,T64	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T86,*T202,*T80	Yes	T86,T202,T80	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T10,T11,T80	Yes	T10,T11,T80	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T1,T152,T64	Yes	T1,T152,T64	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T1,T152,T64	Yes	T1,T152,T64	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T1,T10,T11	Yes	T1,T10,T11	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T152,T10	Yes	T1,T152,T64	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T1,T10,T11	Yes	T1,T10,T11	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T86,*T202,*T80	Yes	T86,T202,T80	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T1,*T10,*T11	Yes	T1,T10,T11	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T1,T152,T64	Yes	T1,T152,T64	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T1,T64,T65	Yes	T1,T64,T65	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T1,T64,T65	Yes	T1,T64,T65	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T64,T65	Yes	T1,T64,T65	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T64,T65	Yes	T1,T64,T65	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T1,T64,T65	Yes	T1,T64,T65	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T1,T64,T65	Yes	T1,T64,T65	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T86,*T202,*T80	Yes	T86,T202,T80	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T1,T64,T65	Yes	T1,T64,T65	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T1,T64,T65	Yes	T1,T64,T65	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T1,T35,T153	Yes	T1,T35,T153	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T35,T382	Yes	T1,T64,T65	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T1,T35,T153	Yes	T1,T35,T153	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T86,*T202,*T80	Yes	T86,T202,T80	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T1,*T35,*T382	Yes	T1,T35,T382	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T1,T64,T65	Yes	T1,T64,T65	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T64,T16,T65	Yes	T64,T16,T65	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T64,T16,T65	Yes	T64,T16,T65	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T64,T16,T65	Yes	T64,T16,T65	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T64,T16,T65	Yes	T64,T16,T65	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T64,T16,T65	Yes	T64,T16,T65	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T64,T16,T65	Yes	T64,T16,T65	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T64,T16,T65	Yes	T64,T16,T65	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T64,T16,T65	Yes	T64,T16,T65	INPUT
tl_usbdev_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T378,T23,T24	Yes	T378,T23,T24	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T17,T378,T23	Yes	T17,T378,T23	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T64,T16,T65	Yes	T16,T18,T378	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T64,*T16,*T65	Yes	T16,T18,T378	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T64,T16,T65	Yes	T64,T16,T65	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T202,*T80,*T81	Yes	T202,T80,T81	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T2,T3,T34	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T34	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T202,*T80,*T81	Yes	T202,T80,T81	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T2,T3,T34	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T202,T80,T81	Yes	T202,T80,T81	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T202,T80,T81	Yes	T202,T80,T81	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T202,T80,T81	Yes	T202,T80,T81	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T202,T80,T81	Yes	T202,T80,T81	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T202,T80,T81	Yes	T202,T80,T81	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T202,T80,T81	Yes	T202,T80,T81	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T202,T80,T81	Yes	T202,T80,T81	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T202,T80,T81	Yes	T202,T80,T81	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T202,T80,T81	Yes	T202,T80,T81	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T202,T80,T81	Yes	T202,T80,T81	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T202,T80,T81	Yes	T202,T80,T81	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T202,*T80,*T81	Yes	T202,T80,T81	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T202,T80,T81	Yes	T202,T80,T81	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T2,T3,T34	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_hmac_o.d_ready	Yes	Yes	T2,T3,T34	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T366,T48,T387	Yes	T366,T48,T387	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T366,T48,T387	Yes	T366,T48,T387	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T3,T366,T48	Yes	T3,T366,T48	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T366,T48,T387	Yes	T366,T48,T387	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T3,T366,T48	Yes	T3,T366,T48	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T202,*T80,*T81	Yes	T202,T80,T81	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T366,T387,T703	Yes	T366,T387,T703	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T3,T366,T48	Yes	T3,T366,T48	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T3,T366,T48	Yes	T3,T366,T48	INPUT
tl_hmac_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T366,T48,T387	Yes	T366,T48,T387	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T366,T48,T387	Yes	T366,T48,T387	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T366,T48,T387	Yes	T366,T48,T387	INPUT
tl_hmac_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T202,*T80,*T81	Yes	T202,T80,T81	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T366,*T48,*T387	Yes	T366,T48,T387	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T366,T48,T387	Yes	T366,T48,T387	INPUT
tl_kmac_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T1,T368,T64	Yes	T1,T368,T64	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T3,T34	Yes	T1,T3,T34	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T1,T3,T34	Yes	T1,T3,T34	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T1,T368,T64	Yes	T1,T368,T64	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T1,T3,T34	Yes	T1,T3,T34	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T202,*T80,*T81	Yes	T202,T80,T81	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T368,T341,T101	Yes	T368,T341,T101	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T1,T3,T34	Yes	T1,T3,T34	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T1,T3,T34	Yes	T1,T3,T34	INPUT
tl_kmac_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T368	Yes	T1,T3,T34	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T3,T34	Yes	T1,T3,T34	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T1,T34,T368	Yes	T1,T34,T368	INPUT
tl_kmac_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T202,*T80,*T81	Yes	T202,T80,T81	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T1,*T368,*T64	Yes	T1,T368,T341	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T1,T3,T34	Yes	T1,T3,T34	INPUT
tl_aes_o.d_ready	Yes	Yes	T2,T3,T34	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T386,T120,T64	Yes	T386,T120,T64	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T386,T120,T64	Yes	T386,T120,T64	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T3,T386,T120	Yes	T3,T386,T120	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T386,T120,T64	Yes	T386,T120,T64	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T3,T386,T120	Yes	T3,T386,T120	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T86,*T80,*T81	Yes	T86,T80,T81	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T3,T386,T120	Yes	T3,T386,T120	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T3,T386,T120	Yes	T3,T386,T120	INPUT
tl_aes_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T3,T386,T120	Yes	T3,T386,T120	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T386,T120,T106	Yes	T386,T120,T64	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T3,T386,T120	Yes	T3,T386,T120	INPUT
tl_aes_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T86,*T80,*T81	Yes	T86,T80,T81	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T3,*T386,*T120	Yes	T3,T386,T120	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T3,T386,T120	Yes	T3,T386,T120	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T202,*T80,*T81	Yes	T202,T80,T81	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T128,T116,T106	Yes	T128,T116,T106	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T34	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T2,T3,T34	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T202,*T80,*T81	Yes	T202,T80,T81	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T128,*T116,*T106	Yes	T48,T128,T49	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T128,T386,T116	Yes	T128,T386,T116	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T86,*T202,*T80	Yes	T86,T202,T80	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T128,T386,T116	Yes	T128,T386,T116	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T34	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T2,T3,T34	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T86,*T202,*T80	Yes	T86,T202,T80	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T128,*T386,*T116	Yes	T128,T386,T116	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T128,T386,T116	Yes	T128,T386,T116	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T128,T386,T116	Yes	T128,T386,T116	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T202,*T80,*T81	Yes	T202,T80,T81	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T128,T386,T116	Yes	T128,T386,T116	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T34	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T2,T3,T34	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T202,*T80,*T81	Yes	T202,T80,T81	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T128,*T386,*T116	Yes	T128,T386,T116	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_o.d_ready	Yes	Yes	T2,T3,T34	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T128,T116,T64	Yes	T128,T116,T64	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T128,T116,T64	Yes	T128,T116,T64	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T128,T116,T64	Yes	T128,T116,T64	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T128,T116,T64	Yes	T128,T116,T64	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T128,T116,T64	Yes	T128,T116,T64	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T202,*T80,*T81	Yes	T202,T80,T81	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T128,T116,T64	Yes	T128,T116,T64	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T128,T116,T64	Yes	T128,T116,T64	INPUT
tl_edn1_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T128,T116,T106	Yes	T128,T116,T106	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T128,T116,T106	Yes	T128,T116,T64	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T128,T116,T106	Yes	T128,T116,T64	INPUT
tl_edn1_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T202,*T80,*T81	Yes	T202,T80,T81	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T128,*T116,*T106	Yes	T128,T116,T106	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T128,T116,T64	Yes	T128,T116,T64	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T34	Yes	T1,T2,T34	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T34	Yes	T1,T2,T34	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T34	Yes	T1,T2,T34	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T1,T2,T34	Yes	T1,T2,T34	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T1,T2,T34	Yes	T1,T2,T34	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T86,*T202,*T80	Yes	T86,T202,T80	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T1,T2,T34	Yes	T1,T2,T34	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T1,T2,T34	Yes	T1,T2,T34	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T80,T82,T239	Yes	T80,T82,T352	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T34	Yes	T1,T2,T34	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T34	Yes	T1,T2,T34	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T1,T2,T34	Yes	T1,T2,T34	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T86,*T202,*T80	Yes	T86,T202,T80	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T34	Yes	T1,T2,T34	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T1,T2,T34	Yes	T1,T2,T34	INPUT
tl_otbn_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T1,T48,T128	Yes	T1,T48,T128	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T3,T48	Yes	T1,T3,T48	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T1,T3,T48	Yes	T1,T3,T48	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T1,T48,T128	Yes	T1,T48,T128	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T1,T3,T48	Yes	T1,T3,T48	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T85,*T240,*T420	Yes	T85,T240,T420	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T1,T3,T48	Yes	T1,T3,T48	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T1,T3,T48	Yes	T1,T3,T48	INPUT
tl_otbn_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T1,T48,T128	Yes	T1,T48,T128	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T3,T48	Yes	T1,T3,T48	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T1,T3,T48	Yes	T1,T3,T48	INPUT
tl_otbn_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T85,*T240,*T420	Yes	T85,T240,T420	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T1,*T48,*T128	Yes	T1,T48,T128	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T1,T3,T48	Yes	T1,T3,T48	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T1,T48,T49	Yes	T1,T48,T49	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T48,T49	Yes	T1,T48,T49	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T1,T48,T49	Yes	T1,T48,T49	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T1,T64,T110	Yes	T1,T64,T110	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T1,T48,T49	Yes	T1,T48,T49	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T202,*T80,*T81	Yes	T202,T80,T81	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T1,T48,T49	Yes	T1,T48,T49	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T1,T48,T49	Yes	T1,T48,T49	INPUT
tl_keymgr_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T1,T110,T170	Yes	T1,T110,T170	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T48,T49	Yes	T1,T48,T49	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T48,T49,T50	Yes	T1,T48,T49	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T202,*T80,*T81	Yes	T202,T80,T81	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T1,*T48,*T49	Yes	T1,T48,T49	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T1,T48,T49	Yes	T1,T48,T49	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T53,*T80,*T81	Yes	T53,T80,T81	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T53,T80,T81	Yes	T53,T80,T81	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T34	Yes	T1,T2,T34	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T1,T2,T34	Yes	T1,T2,T34	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T53,*T80,*T81	Yes	T53,T80,T81	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T2,T3,T34	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T91,T48,T49	Yes	T91,T48,T49	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T91,T48,T49	Yes	T91,T48,T49	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T91,T48,T49	Yes	T91,T48,T49	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T91,T48,T49	Yes	T91,T48,T49	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T91,T48,T49	Yes	T91,T48,T49	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T86,*T202,*T80	Yes	T86,T202,T80	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T91,T48,T49	Yes	T91,T48,T49	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T91,T48,T49	Yes	T91,T48,T49	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T183,T184,T86	Yes	T183,T184,T86	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T91,T121,T174	Yes	T91,T48,T49	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T91,T121,T174	Yes	T91,T48,T49	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T86,*T202,*T80	Yes	T86,T202,T80	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T91,*T121,*T174	Yes	T91,T121,T174	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T91,T48,T49	Yes	T91,T48,T49	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T2,T3,T34	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range