Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1995899	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

27251889

1

T1

273658

T2

12475

T3

11707

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	19505813	1			T1	165971		T2	4855		T3	5073
values[0x0]	8244500	1			T1	107687		T2	7620		T3	6634
values[0x1]	1497475	1			T1	12910		T2	797		T3	889

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	621804	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

28625984

1

T1

286568

T2

13272

T3

12596

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	13471356	1			T1	143284		T2	6637		T3	6299
valid_sources[0x01]	13470394	1			T1	143284		T2	6635		T3	6297
valid_sources[0x02]	37001	1			T78	2		T79	1		T434	7
valid_sources[0x03]	36993	1			T79	1		T435	1		T524	25
valid_sources[0x04]	37482	1			T78	2		T435	1		T60	2
valid_sources[0x05]	37865	1			T77	1		T79	1		T434	9
valid_sources[0x06]	36426	1			T524	29		T72	170		T535	26
valid_sources[0x07]	37043	1			T78	1		T435	1		T524	35
valid_sources[0x08]	37803	1			T77	1		T435	1		T60	3
valid_sources[0x09]	36451	1			T77	1		T435	1		T524	28
valid_sources[0x0a]	37308	1			T524	30		T72	170		T535	27
valid_sources[0x0b]	36569	1			T78	1		T79	1		T434	4
valid_sources[0x0c]	37904	1			T78	1		T79	1		T435	1
valid_sources[0x0d]	37190	1			T79	1		T524	28		T72	156
valid_sources[0x0e]	36740	1			T79	1		T524	33		T72	152
valid_sources[0x0f]	36746	1			T77	2		T524	27		T72	162
valid_sources[0x10]	37016	1			T77	1		T78	1		T435	2
valid_sources[0x11]	37174	1			T77	4		T78	1		T434	2
valid_sources[0x12]	40881	1			T77	1		T78	1		T524	29
valid_sources[0x13]	37996	1			T78	2		T79	2		T435	1
valid_sources[0x14]	36890	1			T79	2		T435	1		T524	30
valid_sources[0x15]	37682	1			T435	4		T524	33		T72	163
valid_sources[0x16]	37195	1			T77	1		T79	3		T524	26
valid_sources[0x17]	38027	1			T78	1		T434	3		T524	38
valid_sources[0x18]	37231	1			T77	1		T435	1		T60	13
valid_sources[0x19]	36924	1			T78	1		T79	1		T434	1
valid_sources[0x1a]	36823	1			T77	1		T524	28		T72	144
valid_sources[0x1b]	36680	1			T435	1		T524	18		T72	163
valid_sources[0x1c]	36843	1			T524	18		T72	166		T535	37
valid_sources[0x1d]	37046	1			T77	2		T79	1		T435	1
valid_sources[0x1e]	36164	1			T77	2		T78	1		T79	2
valid_sources[0x1f]	36751	1			T77	3		T78	2		T79	1
valid_sources[0x20]	36707	1			T77	1		T79	1		T524	27

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

18804885

1

T1

165971

T2

4855

T3

5073

values[0x0]

all_enables

biggest_size

8201511

1

T1

107687

T2

7620

T3

6634

values[0x1]

all_enables

biggest_size

245493

1

T77

25

T78

21

T79

22

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2770651	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

438856

1

T73

117

T74

154

T75

50

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1085445	1			T73	315		T74	366		T75	121
values[0x0]	1036313	1			T73	279		T74	354		T75	108
values[0x1]	1087749	1			T73	310		T74	360		T75	128

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2144600	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1064907

1

T73

310

T74

357

T75

127

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	49810	1			T73	10		T74	20		T75	13
valid_sources[0x01]	50334	1			T74	13		T75	8		T80	34
valid_sources[0x02]	49749	1			T73	20		T74	18		T75	34
valid_sources[0x03]	50088	1			T73	16		T74	22		T80	37
valid_sources[0x04]	49615	1			T73	11		T74	16		T80	33
valid_sources[0x05]	49607	1			T73	14		T74	16		T75	1
valid_sources[0x06]	51083	1			T73	14		T74	18		T80	43
valid_sources[0x07]	49815	1			T73	5		T74	20		T80	51
valid_sources[0x08]	49994	1			T73	8		T74	16		T80	35
valid_sources[0x09]	50577	1			T73	27		T74	9		T75	20
valid_sources[0x0a]	50147	1			T73	37		T74	19		T75	1
valid_sources[0x0b]	49725	1			T73	16		T74	17		T80	30
valid_sources[0x0c]	50897	1			T73	43		T74	14		T75	18
valid_sources[0x0d]	50537	1			T73	5		T74	16		T75	2
valid_sources[0x0e]	50430	1			T73	32		T74	12		T75	8
valid_sources[0x0f]	50670	1			T74	20		T75	1		T80	34
valid_sources[0x10]	50307	1			T73	32		T74	15		T75	8
valid_sources[0x11]	49298	1			T74	19		T75	2		T80	36
valid_sources[0x12]	50295	1			T73	12		T74	32		T75	5
valid_sources[0x13]	51788	1			T74	17		T80	36		T129	2
valid_sources[0x14]	49124	1			T73	13		T74	17		T75	12
valid_sources[0x15]	50433	1			T74	20		T80	41		T129	5
valid_sources[0x16]	49319	1			T73	14		T74	15		T75	9
valid_sources[0x17]	49232	1			T73	15		T74	19		T80	38
valid_sources[0x18]	50216	1			T73	24		T74	17		T75	10
valid_sources[0x19]	49888	1			T73	11		T74	16		T80	42
valid_sources[0x1a]	51613	1			T73	50		T74	12		T75	1
valid_sources[0x1b]	49893	1			T73	20		T74	19		T80	33
valid_sources[0x1c]	49429	1			T74	18		T75	5		T80	36
valid_sources[0x1d]	50623	1			T73	26		T74	14		T80	37
valid_sources[0x1e]	51197	1			T73	8		T74	14		T75	15
valid_sources[0x1f]	49782	1			T73	19		T74	11		T75	11
valid_sources[0x20]	50345	1			T73	10		T74	19		T80	28

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

46133

1

T73

13

T74

14

T75

8

values[0x0]

all_enables

biggest_size

346855

1

T73

89

T74

126

T75

36

values[0x1]

all_enables

biggest_size

45868

1

T73

15

T74

14

T75

6

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2964717	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

482143

1

T73

136

T74

170

T75

49

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1180594	1			T73	313		T74	398		T75	148
values[0x0]	1087629	1			T73	294		T74	378		T75	133
values[0x1]	1178637	1			T73	327		T74	377		T75	128

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2275047	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1171813

1

T73

323

T74

387

T75

133

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	53856	1			T73	9		T74	13		T75	10
valid_sources[0x01]	53178	1			T74	17		T80	33		T420	39
valid_sources[0x02]	54495	1			T73	19		T74	19		T75	11
valid_sources[0x03]	53272	1			T73	13		T74	15		T75	1
valid_sources[0x04]	54173	1			T73	7		T74	13		T75	4
valid_sources[0x05]	53220	1			T73	15		T74	26		T75	10
valid_sources[0x06]	54103	1			T73	12		T74	23		T75	18
valid_sources[0x07]	54049	1			T73	14		T74	13		T75	9
valid_sources[0x08]	54576	1			T73	14		T74	13		T75	18
valid_sources[0x09]	53908	1			T73	33		T74	18		T75	18
valid_sources[0x0a]	54148	1			T73	45		T74	14		T75	4
valid_sources[0x0b]	53459	1			T73	14		T74	27		T80	25
valid_sources[0x0c]	54213	1			T73	45		T74	16		T75	4
valid_sources[0x0d]	53175	1			T73	16		T74	13		T75	2
valid_sources[0x0e]	53472	1			T73	21		T74	18		T75	15
valid_sources[0x0f]	54338	1			T74	20		T75	17		T80	37
valid_sources[0x10]	54679	1			T73	23		T74	12		T75	2
valid_sources[0x11]	53501	1			T74	15		T75	6		T80	33
valid_sources[0x12]	53118	1			T73	7		T74	14		T75	2
valid_sources[0x13]	54211	1			T74	16		T80	47		T129	2
valid_sources[0x14]	53442	1			T73	19		T74	19		T75	15
valid_sources[0x15]	53905	1			T74	31		T75	5		T80	34
valid_sources[0x16]	53739	1			T73	14		T74	24		T75	2
valid_sources[0x17]	52983	1			T73	20		T74	13		T75	4
valid_sources[0x18]	54777	1			T73	21		T74	13		T75	6
valid_sources[0x19]	53436	1			T73	5		T74	30		T75	18
valid_sources[0x1a]	53852	1			T73	37		T74	19		T80	34
valid_sources[0x1b]	54378	1			T73	20		T74	15		T75	1
valid_sources[0x1c]	53348	1			T74	25		T75	9		T80	41
valid_sources[0x1d]	55034	1			T73	16		T74	18		T75	5
valid_sources[0x1e]	54120	1			T73	11		T74	21		T75	2
valid_sources[0x1f]	53765	1			T73	6		T74	25		T75	2
valid_sources[0x20]	53482	1			T73	5		T74	19		T75	16

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

50561

1

T73

17

T74

21

T75

4

values[0x0]

all_enables

biggest_size

380863

1

T73

103

T74

127

T75

43

values[0x1]

all_enables

biggest_size

50719

1

T73

16

T74

22

T75

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2785314	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

441508

1

T73

136

T74

155

T75

52

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1093048	1			T73	294		T74	338		T75	145
values[0x0]	1041168	1			T73	315		T74	362		T75	129
values[0x1]	1092606	1			T73	288		T74	345		T75	126

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2156857	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1069965

1

T73

307

T74

352

T75

122

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	50840	1			T73	14		T74	13		T80	20
valid_sources[0x01]	49584	1			T74	16		T75	22		T80	51
valid_sources[0x02]	49484	1			T73	18		T74	13		T75	20
valid_sources[0x03]	50946	1			T73	13		T74	13		T75	13
valid_sources[0x04]	50143	1			T73	6		T74	15		T75	6
valid_sources[0x05]	50357	1			T73	5		T74	9		T75	10
valid_sources[0x06]	51293	1			T73	20		T74	14		T75	2
valid_sources[0x07]	49788	1			T73	19		T74	17		T75	5
valid_sources[0x08]	50494	1			T73	16		T74	23		T75	6
valid_sources[0x09]	50456	1			T73	25		T74	13		T75	11
valid_sources[0x0a]	51258	1			T73	42		T74	13		T75	5
valid_sources[0x0b]	50346	1			T73	15		T74	13		T75	2
valid_sources[0x0c]	51385	1			T73	44		T74	11		T75	4
valid_sources[0x0d]	50350	1			T73	13		T74	19		T75	2
valid_sources[0x0e]	50481	1			T73	31		T74	11		T75	5
valid_sources[0x0f]	50816	1			T74	13		T75	13		T80	62
valid_sources[0x10]	50661	1			T73	21		T74	21		T75	3
valid_sources[0x11]	49992	1			T74	17		T75	6		T80	39
valid_sources[0x12]	50425	1			T73	11		T74	11		T75	6
valid_sources[0x13]	50629	1			T74	20		T80	32		T420	39
valid_sources[0x14]	49488	1			T73	10		T74	17		T75	13
valid_sources[0x15]	50746	1			T74	11		T80	65		T420	30
valid_sources[0x16]	49727	1			T73	6		T74	13		T75	2
valid_sources[0x17]	50125	1			T73	7		T74	19		T80	50
valid_sources[0x18]	50812	1			T73	37		T74	10		T75	2
valid_sources[0x19]	50460	1			T73	20		T74	15		T75	3
valid_sources[0x1a]	48913	1			T73	55		T74	23		T75	11
valid_sources[0x1b]	50037	1			T73	20		T74	16		T75	12
valid_sources[0x1c]	50029	1			T74	20		T75	11		T80	30
valid_sources[0x1d]	50902	1			T73	26		T74	20		T75	14
valid_sources[0x1e]	50567	1			T73	6		T74	20		T80	14
valid_sources[0x1f]	50599	1			T73	15		T74	14		T80	28
valid_sources[0x20]	49336	1			T73	11		T74	15		T75	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

46238

1

T73

13

T74

13

T75

5

values[0x0]

all_enables

biggest_size

348885

1

T73

108

T74

120

T75

41

values[0x1]

all_enables

biggest_size

46385

1

T73

15

T74

22

T75

6