Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	425325128	45846974	0	0
DepthKnown_A	425325128	425224149	0	0
RvalidKnown_A	425325128	425224149	0	0
WreadyKnown_A	425325128	425224149	0	0
gen_passthru_fifo.paramCheckPass	958	958	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425325128	45846974	0	0
T1	167176	330633	0	0
T2	220583	28406	0	0
T3	234935	21722	0	0
T29	582996	54199	0	0
T58	217973	24678	0	0
T68	786708	3461	0	0
T85	265991	63616	0	0
T86	188775	19988	0	0
T87	71693	7306	0	0
T88	190508	37057	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425325128	425224149	0	0
T1	167176	167170	0	0
T2	220583	220470	0	0
T3	234935	234829	0	0
T29	582996	582734	0	0
T58	217973	217860	0	0
T68	786708	786657	0	0
T85	265991	265929	0	0
T86	188775	188659	0	0
T87	71693	71635	0	0
T88	190508	190446	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425325128	425224149	0	0
T1	167176	167170	0	0
T2	220583	220470	0	0
T3	234935	234829	0	0
T29	582996	582734	0	0
T58	217973	217860	0	0
T68	786708	786657	0	0
T85	265991	265929	0	0
T86	188775	188659	0	0
T87	71693	71635	0	0
T88	190508	190446	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425325128	425224149	0	0
T1	167176	167170	0	0
T2	220583	220470	0	0
T3	234935	234829	0	0
T29	582996	582734	0	0
T58	217973	217860	0	0
T68	786708	786657	0	0
T85	265991	265929	0	0
T86	188775	188659	0	0
T87	71693	71635	0	0
T88	190508	190446	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	958	958	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T29	1	1	0	0
T58	1	1	0	0
T68	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	425325128	35371360	0	0
DepthKnown_A	425325128	425224149	0	0
RvalidKnown_A	425325128	425224149	0	0
WreadyKnown_A	425325128	425224149	0	0
gen_passthru_fifo.paramCheckPass	958	958	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425325128	35371360	0	0
T1	167176	261417	0	0
T2	220583	18897	0	0
T3	234935	17433	0	0
T29	582996	40833	0	0
T58	217973	20714	0	0
T68	786708	1867	0	0
T85	265991	44428	0	0
T86	188775	16594	0	0
T87	71693	5442	0	0
T88	190508	27030	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425325128	425224149	0	0
T1	167176	167170	0	0
T2	220583	220470	0	0
T3	234935	234829	0	0
T29	582996	582734	0	0
T58	217973	217860	0	0
T68	786708	786657	0	0
T85	265991	265929	0	0
T86	188775	188659	0	0
T87	71693	71635	0	0
T88	190508	190446	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425325128	425224149	0	0
T1	167176	167170	0	0
T2	220583	220470	0	0
T3	234935	234829	0	0
T29	582996	582734	0	0
T58	217973	217860	0	0
T68	786708	786657	0	0
T85	265991	265929	0	0
T86	188775	188659	0	0
T87	71693	71635	0	0
T88	190508	190446	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425325128	425224149	0	0
T1	167176	167170	0	0
T2	220583	220470	0	0
T3	234935	234829	0	0
T29	582996	582734	0	0
T58	217973	217860	0	0
T68	786708	786657	0	0
T85	265991	265929	0	0
T86	188775	188659	0	0
T87	71693	71635	0	0
T88	190508	190446	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	958	958	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T29	1	1	0	0
T58	1	1	0	0
T68	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	425325128	30366388	0	0
DepthKnown_A	425325128	425224149	0	0
RvalidKnown_A	425325128	425224149	0	0
WreadyKnown_A	425325128	425224149	0	0
gen_passthru_fifo.paramCheckPass	958	958	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425325128	30366388	0	0
T1	167176	287446	0	0
T2	220583	13667	0	0
T3	234935	12838	0	0
T29	582996	25624	0	0
T58	217973	10990	0	0
T68	786708	459	0	0
T85	265991	27234	0	0
T86	188775	12878	0	0
T87	71693	4345	0	0
T88	190508	21781	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425325128	425224149	0	0
T1	167176	167170	0	0
T2	220583	220470	0	0
T3	234935	234829	0	0
T29	582996	582734	0	0
T58	217973	217860	0	0
T68	786708	786657	0	0
T85	265991	265929	0	0
T86	188775	188659	0	0
T87	71693	71635	0	0
T88	190508	190446	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425325128	425224149	0	0
T1	167176	167170	0	0
T2	220583	220470	0	0
T3	234935	234829	0	0
T29	582996	582734	0	0
T58	217973	217860	0	0
T68	786708	786657	0	0
T85	265991	265929	0	0
T86	188775	188659	0	0
T87	71693	71635	0	0
T88	190508	190446	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425325128	425224149	0	0
T1	167176	167170	0	0
T2	220583	220470	0	0
T3	234935	234829	0	0
T29	582996	582734	0	0
T58	217973	217860	0	0
T68	786708	786657	0	0
T85	265991	265929	0	0
T86	188775	188659	0	0
T87	71693	71635	0	0
T88	190508	190446	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	958	958	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T29	1	1	0	0
T58	1	1	0	0
T68	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	425325128	26961558	0	0
DepthKnown_A	425325128	425224149	0	0
RvalidKnown_A	425325128	425224149	0	0
WreadyKnown_A	425325128	425224149	0	0
gen_passthru_fifo.paramCheckPass	958	958	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425325128	26961558	0	0
T1	167176	286568	0	0
T2	220583	13272	0	0
T3	234935	12596	0	0
T29	582996	24866	0	0
T58	217973	10742	0	0
T68	786708	351	0	0
T85	265991	27038	0	0
T86	188775	12653	0	0
T87	71693	4228	0	0
T88	190508	21230	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425325128	425224149	0	0
T1	167176	167170	0	0
T2	220583	220470	0	0
T3	234935	234829	0	0
T29	582996	582734	0	0
T58	217973	217860	0	0
T68	786708	786657	0	0
T85	265991	265929	0	0
T86	188775	188659	0	0
T87	71693	71635	0	0
T88	190508	190446	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425325128	425224149	0	0
T1	167176	167170	0	0
T2	220583	220470	0	0
T3	234935	234829	0	0
T29	582996	582734	0	0
T58	217973	217860	0	0
T68	786708	786657	0	0
T85	265991	265929	0	0
T86	188775	188659	0	0
T87	71693	71635	0	0
T88	190508	190446	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425325128	425224149	0	0
T1	167176	167170	0	0
T2	220583	220470	0	0
T3	234935	234829	0	0
T29	582996	582734	0	0
T58	217973	217860	0	0
T68	786708	786657	0	0
T85	265991	265929	0	0
T86	188775	188659	0	0
T87	71693	71635	0	0
T88	190508	190446	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	958	958	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T29	1	1	0	0
T58	1	1	0	0
T68	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	500564374	103985	0	0
DepthKnown_A	500564374	500451733	0	0
RvalidKnown_A	500564374	500451733	0	0
WreadyKnown_A	500564374	500451733	0	0
gen_passthru_fifo.paramCheckPass	2847	2847	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500564374	103985	0	0
T1	167176	20	0	0
T2	220583	153	0	0
T3	234935	30	0	0
T29	582996	181	0	0
T58	217973	29	0	0
T68	786708	8	0	0
T85	265991	35	0	0
T86	188775	26	0	0
T87	71693	13	0	0
T88	190508	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500564374	500451733	0	0
T1	167176	167170	0	0
T2	220583	220470	0	0
T3	234935	234829	0	0
T29	582996	582734	0	0
T58	217973	217860	0	0
T68	786708	786657	0	0
T85	265991	265929	0	0
T86	188775	188659	0	0
T87	71693	71635	0	0
T88	190508	190446	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500564374	500451733	0	0
T1	167176	167170	0	0
T2	220583	220470	0	0
T3	234935	234829	0	0
T29	582996	582734	0	0
T58	217973	217860	0	0
T68	786708	786657	0	0
T85	265991	265929	0	0
T86	188775	188659	0	0
T87	71693	71635	0	0
T88	190508	190446	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500564374	500451733	0	0
T1	167176	167170	0	0
T2	220583	220470	0	0
T3	234935	234829	0	0
T29	582996	582734	0	0
T58	217973	217860	0	0
T68	786708	786657	0	0
T85	265991	265929	0	0
T86	188775	188659	0	0
T87	71693	71635	0	0
T88	190508	190446	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2847	2847	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T29	1	1	0	0
T58	1	1	0	0
T68	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	500564374	107474	0	0
DepthKnown_A	500564374	500451733	0	0
RvalidKnown_A	500564374	500451733	0	0
WreadyKnown_A	500564374	500451733	0	0
gen_passthru_fifo.paramCheckPass	2847	2847	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500564374	107474	0	0
T1	167176	20	0	0
T2	220583	153	0	0
T3	234935	30	0	0
T29	582996	181	0	0
T58	217973	29	0	0
T68	786708	8	0	0
T85	265991	35	0	0
T86	188775	26	0	0
T87	71693	13	0	0
T88	190508	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500564374	500451733	0	0
T1	167176	167170	0	0
T2	220583	220470	0	0
T3	234935	234829	0	0
T29	582996	582734	0	0
T58	217973	217860	0	0
T68	786708	786657	0	0
T85	265991	265929	0	0
T86	188775	188659	0	0
T87	71693	71635	0	0
T88	190508	190446	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500564374	500451733	0	0
T1	167176	167170	0	0
T2	220583	220470	0	0
T3	234935	234829	0	0
T29	582996	582734	0	0
T58	217973	217860	0	0
T68	786708	786657	0	0
T85	265991	265929	0	0
T86	188775	188659	0	0
T87	71693	71635	0	0
T88	190508	190446	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500564374	500451733	0	0
T1	167176	167170	0	0
T2	220583	220470	0	0
T3	234935	234829	0	0
T29	582996	582734	0	0
T58	217973	217860	0	0
T68	786708	786657	0	0
T85	265991	265929	0	0
T86	188775	188659	0	0
T87	71693	71635	0	0
T88	190508	190446	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2847	2847	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T29	1	1	0	0
T58	1	1	0	0
T68	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	500564374	50256	0	0
DepthKnown_A	500564374	500451733	0	0
RvalidKnown_A	500564374	500451733	0	0
WreadyKnown_A	500564374	500451733	0	0
gen_passthru_fifo.paramCheckPass	2847	2847	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500564374	50256	0	0
T1	167176	19	0	0
T2	220583	97	0	0
T3	234935	28	0	0
T29	582996	176	0	0
T58	217973	27	0	0
T68	786708	8	0	0
T85	265991	29	0	0
T86	188775	24	0	0
T87	71693	12	0	0
T88	190508	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500564374	500451733	0	0
T1	167176	167170	0	0
T2	220583	220470	0	0
T3	234935	234829	0	0
T29	582996	582734	0	0
T58	217973	217860	0	0
T68	786708	786657	0	0
T85	265991	265929	0	0
T86	188775	188659	0	0
T87	71693	71635	0	0
T88	190508	190446	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500564374	500451733	0	0
T1	167176	167170	0	0
T2	220583	220470	0	0
T3	234935	234829	0	0
T29	582996	582734	0	0
T58	217973	217860	0	0
T68	786708	786657	0	0
T85	265991	265929	0	0
T86	188775	188659	0	0
T87	71693	71635	0	0
T88	190508	190446	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500564374	500451733	0	0
T1	167176	167170	0	0
T2	220583	220470	0	0
T3	234935	234829	0	0
T29	582996	582734	0	0
T58	217973	217860	0	0
T68	786708	786657	0	0
T85	265991	265929	0	0
T86	188775	188659	0	0
T87	71693	71635	0	0
T88	190508	190446	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2847	2847	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T29	1	1	0	0
T58	1	1	0	0
T68	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	500564374	50256	0	0
DepthKnown_A	500564374	500451733	0	0
RvalidKnown_A	500564374	500451733	0	0
WreadyKnown_A	500564374	500451733	0	0
gen_passthru_fifo.paramCheckPass	2847	2847	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500564374	50256	0	0
T1	167176	19	0	0
T2	220583	97	0	0
T3	234935	28	0	0
T29	582996	176	0	0
T58	217973	27	0	0
T68	786708	8	0	0
T85	265991	29	0	0
T86	188775	24	0	0
T87	71693	12	0	0
T88	190508	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500564374	500451733	0	0
T1	167176	167170	0	0
T2	220583	220470	0	0
T3	234935	234829	0	0
T29	582996	582734	0	0
T58	217973	217860	0	0
T68	786708	786657	0	0
T85	265991	265929	0	0
T86	188775	188659	0	0
T87	71693	71635	0	0
T88	190508	190446	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500564374	500451733	0	0
T1	167176	167170	0	0
T2	220583	220470	0	0
T3	234935	234829	0	0
T29	582996	582734	0	0
T58	217973	217860	0	0
T68	786708	786657	0	0
T85	265991	265929	0	0
T86	188775	188659	0	0
T87	71693	71635	0	0
T88	190508	190446	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500564374	500451733	0	0
T1	167176	167170	0	0
T2	220583	220470	0	0
T3	234935	234829	0	0
T29	582996	582734	0	0
T58	217973	217860	0	0
T68	786708	786657	0	0
T85	265991	265929	0	0
T86	188775	188659	0	0
T87	71693	71635	0	0
T88	190508	190446	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2847	2847	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T29	1	1	0	0
T58	1	1	0	0
T68	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	500564374	53729	0	0
DepthKnown_A	500564374	500451733	0	0
RvalidKnown_A	500564374	500451733	0	0
WreadyKnown_A	500564374	500451733	0	0
gen_passthru_fifo.paramCheckPass	2847	2847	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500564374	53729	0	0
T1	167176	1	0	0
T2	220583	56	0	0
T3	234935	2	0	0
T4	0	2	0	0
T29	582996	5	0	0
T58	217973	2	0	0
T68	786708	0	0	0
T85	265991	6	0	0
T86	188775	2	0	0
T87	71693	1	0	0
T88	190508	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500564374	500451733	0	0
T1	167176	167170	0	0
T2	220583	220470	0	0
T3	234935	234829	0	0
T29	582996	582734	0	0
T58	217973	217860	0	0
T68	786708	786657	0	0
T85	265991	265929	0	0
T86	188775	188659	0	0
T87	71693	71635	0	0
T88	190508	190446	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500564374	500451733	0	0
T1	167176	167170	0	0
T2	220583	220470	0	0
T3	234935	234829	0	0
T29	582996	582734	0	0
T58	217973	217860	0	0
T68	786708	786657	0	0
T85	265991	265929	0	0
T86	188775	188659	0	0
T87	71693	71635	0	0
T88	190508	190446	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500564374	500451733	0	0
T1	167176	167170	0	0
T2	220583	220470	0	0
T3	234935	234829	0	0
T29	582996	582734	0	0
T58	217973	217860	0	0
T68	786708	786657	0	0
T85	265991	265929	0	0
T86	188775	188659	0	0
T87	71693	71635	0	0
T88	190508	190446	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2847	2847	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T29	1	1	0	0
T58	1	1	0	0
T68	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	500564374	57218	0	0
DepthKnown_A	500564374	500451733	0	0
RvalidKnown_A	500564374	500451733	0	0
WreadyKnown_A	500564374	500451733	0	0
gen_passthru_fifo.paramCheckPass	2847	2847	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500564374	57218	0	0
T1	167176	1	0	0
T2	220583	56	0	0
T3	234935	2	0	0
T4	0	2	0	0
T29	582996	5	0	0
T58	217973	2	0	0
T68	786708	0	0	0
T85	265991	6	0	0
T86	188775	2	0	0
T87	71693	1	0	0
T88	190508	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500564374	500451733	0	0
T1	167176	167170	0	0
T2	220583	220470	0	0
T3	234935	234829	0	0
T29	582996	582734	0	0
T58	217973	217860	0	0
T68	786708	786657	0	0
T85	265991	265929	0	0
T86	188775	188659	0	0
T87	71693	71635	0	0
T88	190508	190446	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500564374	500451733	0	0
T1	167176	167170	0	0
T2	220583	220470	0	0
T3	234935	234829	0	0
T29	582996	582734	0	0
T58	217973	217860	0	0
T68	786708	786657	0	0
T85	265991	265929	0	0
T86	188775	188659	0	0
T87	71693	71635	0	0
T88	190508	190446	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500564374	500451733	0	0
T1	167176	167170	0	0
T2	220583	220470	0	0
T3	234935	234829	0	0
T29	582996	582734	0	0
T58	217973	217860	0	0
T68	786708	786657	0	0
T85	265991	265929	0	0
T86	188775	188659	0	0
T87	71693	71635	0	0
T88	190508	190446	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2847	2847	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T29	1	1	0	0
T58	1	1	0	0
T68	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0