Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.38	89.61		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.38	89.61		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.38	89.61		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.38	89.61		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	39	39	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T29	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T29,T172,T39	Yes	T29,T172,T39	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T29,T172,T39	Yes	T29,T172,T39	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T4,*T76,*T77	Yes	T4,T76,T77	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_i.a_valid	Yes	Yes	T29,T172,T39	Yes	T29,T172,T39	INPUT
tl_o.a_ready	Yes	Yes	T29,T172,T39	Yes	T29,T172,T39	OUTPUT
tl_o.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T75,T80	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T29,T172,T39	Yes	T29,T172,T39	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T29,T172,T39	Yes	T29,T172,T39	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T29,T172,T39	Yes	T29,T172,T39	OUTPUT
tl_o.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T79,*T60,*T73	Yes	T79,T60,T73	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T29,*T172,*T39	Yes	T29,T172,T39	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T29,T172,T39	Yes	T29,T172,T39	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T174,T124,T328	Yes	T174,T124,T328	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T124,T81,T82	Yes	T124,T81,T82	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T124,T81,T82	Yes	T124,T81,T82	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T174,T124,T328	Yes	T174,T124,T328	OUTPUT
cio_rx_i	Yes	Yes	T2,T3,T29	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T172,T39,T40	Yes	T172,T39,T40	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T29,T172,T186	Yes	T29,T172,T186	OUTPUT
intr_rx_watermark_o	Yes	Yes	T172,T186,T119	Yes	T172,T186,T119	OUTPUT
intr_tx_empty_o	Yes	Yes	T172,T186,T119	Yes	T172,T186,T119	OUTPUT
intr_rx_overflow_o	Yes	Yes	T172,T186,T119	Yes	T172,T186,T119	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T296,T312,T320	Yes	T296,T312,T320	OUTPUT
intr_rx_break_err_o	Yes	Yes	T296,T312,T320	Yes	T296,T312,T320	OUTPUT
intr_rx_timeout_o	Yes	Yes	T296,T312,T320	Yes	T296,T312,T320	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T296,T312,T320	Yes	T296,T312,T320	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	302	302	100.00
Total Bits 0->1	151	151	100.00
Total Bits 1->0	151	151	100.00

Ports	39	39	100.00
Port Bits	302	302	100.00
Port Bits 0->1	151	151	100.00
Port Bits 1->0	151	151	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T29	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T29,T39,T40	Yes	T29,T39,T40	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T29,T39,T40	Yes	T29,T39,T40	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T4,*T76,*T77	Yes	T4,T76,T77	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_i.a_valid	Yes	Yes	T29,T39,T40	Yes	T29,T39,T40	INPUT
tl_o.a_ready	Yes	Yes	T29,T39,T40	Yes	T29,T39,T40	OUTPUT
tl_o.d_error	Yes	Yes	T73,T75,T80	Yes	T73,T75,T80	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T29,T39,T40	Yes	T29,T39,T40	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T29,T39,T40	Yes	T29,T39,T40	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T29,T39,T40	Yes	T29,T39,T40	OUTPUT
tl_o.d_sink	Yes	Yes	T73,T75,T80	Yes	T73,T75,T80	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T79,*T73,*T75	Yes	T79,T73,T75	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T73,T75,T80	Yes	T73,T75,T80	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T29,*T39,*T40	Yes	T29,T39,T40	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T29,T39,T40	Yes	T29,T39,T40	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T124,T357,T155	Yes	T124,T357,T155	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T124,T82,T84	Yes	T124,T82,T84	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T124,T82,T84	Yes	T124,T82,T84	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T124,T357,T155	Yes	T124,T357,T155	OUTPUT
cio_rx_i	Yes	Yes	T2,T3,T29	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T39,T40,T41	Yes	T39,T40,T41	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T29,T295,T296	Yes	T29,T295,T296	OUTPUT
intr_rx_watermark_o	Yes	Yes	T296,T197,T198	Yes	T296,T197,T198	OUTPUT
intr_tx_empty_o	Yes	Yes	T321,T322,T296	Yes	T321,T322,T296	OUTPUT
intr_rx_overflow_o	Yes	Yes	T321,T322,T296	Yes	T321,T322,T296	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T296,T312,T320	Yes	T296,T312,T320	OUTPUT
intr_rx_break_err_o	Yes	Yes	T296,T312,T320	Yes	T296,T312,T320	OUTPUT
intr_rx_timeout_o	Yes	Yes	T296,T312,T320	Yes	T296,T312,T320	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T296,T312,T320	Yes	T296,T312,T320	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	39	39	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T29	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T194,T296,T195	Yes	T194,T296,T195	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T194,T296,T195	Yes	T194,T296,T195	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T4,*T76,*T77	Yes	T4,T76,T77	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_i.a_valid	Yes	Yes	T194,T155,T296	Yes	T194,T155,T296	INPUT
tl_o.a_ready	Yes	Yes	T194,T155,T296	Yes	T194,T155,T296	OUTPUT
tl_o.d_error	Yes	Yes	T73,T80,T129	Yes	T73,T80,T129	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T194,T296,T195	Yes	T194,T296,T195	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T194,T155,T296	Yes	T194,T155,T296	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T194,T155,T296	Yes	T194,T155,T296	OUTPUT
tl_o.d_sink	Yes	Yes	T73,T75,T80	Yes	T73,T75,T80	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T79,*T60,*T73	Yes	T79,T60,T73	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T73,T75,T80	Yes	T73,T75,T80	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T194,*T296,*T195	Yes	T194,T296,T195	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T194,T155,T296	Yes	T194,T155,T296	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T328,T249,T155	Yes	T328,T249,T155	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T82,T84,T153	Yes	T82,T84,T153	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T82,T84,T153	Yes	T82,T84,T153	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T328,T249,T155	Yes	T328,T249,T155	OUTPUT
cio_rx_i	Yes	Yes	T194,T195,T196	Yes	T194,T12,T30	INPUT
cio_tx_o	Yes	Yes	T194,T195,T196	Yes	T194,T195,T196	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T194,T296,T195	Yes	T194,T296,T195	OUTPUT
intr_rx_watermark_o	Yes	Yes	T194,T296,T195	Yes	T194,T296,T195	OUTPUT
intr_tx_empty_o	Yes	Yes	T194,T296,T195	Yes	T194,T296,T195	OUTPUT
intr_rx_overflow_o	Yes	Yes	T194,T296,T195	Yes	T194,T296,T195	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T296,T312,T320	Yes	T296,T312,T320	OUTPUT
intr_rx_break_err_o	Yes	Yes	T296,T312,T320	Yes	T296,T312,T320	OUTPUT
intr_rx_timeout_o	Yes	Yes	T296,T312,T320	Yes	T296,T312,T320	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T296,T312,T320	Yes	T296,T312,T320	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	39	39	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T29	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T172,T186,T119	Yes	T172,T186,T119	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T172,T186,T119	Yes	T172,T186,T119	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T4,*T76,*T77	Yes	T4,T76,T77	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_i.a_valid	Yes	Yes	T172,T186,T119	Yes	T172,T186,T119	INPUT
tl_o.a_ready	Yes	Yes	T172,T186,T119	Yes	T172,T186,T119	OUTPUT
tl_o.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T75,T80	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T172,T186,T119	Yes	T172,T186,T119	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T172,T186,T119	Yes	T172,T186,T119	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T172,T186,T119	Yes	T172,T186,T119	OUTPUT
tl_o.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T75,T80	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T60,*T73,*T75	Yes	T60,T73,T74	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T73,T75,T80	Yes	T73,T75,T80	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T172,*T186,*T119	Yes	T172,T186,T119	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T172,T186,T119	Yes	T172,T186,T119	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T662,T364,T155	Yes	T662,T364,T155	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T82,T84,T153	Yes	T82,T84,T153	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T82,T84,T153	Yes	T82,T84,T153	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T662,T364,T155	Yes	T662,T364,T155	OUTPUT
cio_rx_i	Yes	Yes	T172,T186,T119	Yes	T172,T186,T119	INPUT
cio_tx_o	Yes	Yes	T172,T186,T119	Yes	T172,T186,T119	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T172,T186,T119	Yes	T172,T186,T119	OUTPUT
intr_rx_watermark_o	Yes	Yes	T172,T186,T119	Yes	T172,T186,T119	OUTPUT
intr_tx_empty_o	Yes	Yes	T172,T186,T119	Yes	T172,T186,T119	OUTPUT
intr_rx_overflow_o	Yes	Yes	T172,T186,T119	Yes	T172,T186,T119	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T296,T312,T320	Yes	T296,T312,T320	OUTPUT
intr_rx_break_err_o	Yes	Yes	T296,T312,T320	Yes	T296,T312,T320	OUTPUT
intr_rx_timeout_o	Yes	Yes	T296,T312,T320	Yes	T296,T312,T320	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T296,T312,T320	Yes	T296,T312,T320	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	39	39	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T29	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T14,T15,T296	Yes	T14,T15,T296	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T14,T15,T296	Yes	T14,T15,T296	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T4,*T76,*T77	Yes	T4,T76,T77	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_i.a_valid	Yes	Yes	T14,T15,T155	Yes	T14,T15,T155	INPUT
tl_o.a_ready	Yes	Yes	T14,T15,T155	Yes	T14,T15,T155	OUTPUT
tl_o.d_error	Yes	Yes	T73,T80,T129	Yes	T73,T80,T129	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T14,T15,T296	Yes	T14,T15,T296	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T14,T15,T155	Yes	T14,T15,T155	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T14,T15,T155	Yes	T14,T15,T155	OUTPUT
tl_o.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T60,*T73,*T74	Yes	T60,T73,T74	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T14,*T15,*T296	Yes	T14,T15,T296	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T14,T15,T155	Yes	T14,T15,T155	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T174,T81,T155	Yes	T174,T81,T155	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T81,T82,T84	Yes	T81,T82,T84	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T81,T82,T84	Yes	T81,T82,T84	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T174,T81,T155	Yes	T174,T81,T155	OUTPUT
cio_rx_i	Yes	Yes	T14,T15,T329	Yes	T14,T15,T329	INPUT
cio_tx_o	Yes	Yes	T14,T15,T329	Yes	T14,T15,T329	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T14,T15,T296	Yes	T14,T15,T296	OUTPUT
intr_rx_watermark_o	Yes	Yes	T14,T15,T296	Yes	T14,T15,T296	OUTPUT
intr_tx_empty_o	Yes	Yes	T14,T15,T296	Yes	T14,T15,T296	OUTPUT
intr_rx_overflow_o	Yes	Yes	T14,T15,T296	Yes	T14,T15,T296	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T296,T312,T320	Yes	T296,T312,T320	OUTPUT
intr_rx_break_err_o	Yes	Yes	T296,T312,T320	Yes	T296,T312,T320	OUTPUT
intr_rx_timeout_o	Yes	Yes	T296,T312,T320	Yes	T296,T312,T320	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T296,T312,T320	Yes	T296,T312,T320	OUTPUT

*Tests covering at least one bit in the range