Unified Coverage Report :: Module Instance :: tb.dut.u_padring.gen_dio_pads[0].u_dio_pad.gen_generic.u_impl

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[1].u_dio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[1].u_dio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T16,T17
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T26,T27,T28

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T16,T17
0	1	Covered	T26,T27,T28
1	0	Covered	T1,T2,T3
1	1	Covered	T26,T27,T28

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T1,T16,T18

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T26,T27,T28
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T17
1	0	Covered	T26,T27,T28
1	1	Covered	T26,T27,T28

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T16,T18

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T1,T16,T18

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T26,T27,T28

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T16,T18
1	1	Covered	T26,T27,T28

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T26,T27,T28

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[1].u_dio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	74	(ie_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T16,T18
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[1].u_dio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	958	958	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	958	958
T1	1	1
T2	1	1
T3	1	1
T29	1	1
T58	1	1
T68	1	1
T85	1	1
T86	1	1
T87	1	1
T88	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[2].u_dio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[2].u_dio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T16,T18
1	0	Covered	T26,T27,T28
1	1	Covered	T26,T27,T28

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T26,T27,T28
1	0	Covered	T1,T16,T17
1	1	Covered	T26,T27,T28

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T1,T16,T18

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T26,T27,T28
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T26,T27,T28

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T16,T18

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T1,T16,T18

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T26,T27,T28

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T16,T18
1	1	Covered	T26,T27,T28

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T26,T27,T28

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[2].u_dio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00



	LineNo.	Expression
-1-:	74	(ie_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T16,T18
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[2].u_dio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	958	958	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	958	958
T1	1	1
T2	1	1
T3	1	1
T29	1	1
T58	1	1
T68	1	1
T85	1	1
T86	1	1
T87	1	1
T88	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[5].u_dio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	98	0	0
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	104	1	1	100.00

Line No.	Covered	Statements
39		unreachable
98		unreachable
103	1	1
104	1	1

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[5].u_dio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	958	958	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	958	958
T1	1	1
T2	1	1
T3	1	1
T29	1	1
T58	1	1
T68	1	1
T85	1	1
T86	1	1
T87	1	1
T88	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[8].u_dio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	98	0	0
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	104	1	1	100.00

Line No.	Covered	Statements
39		unreachable
98		unreachable
103	1	1
104	1	1

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[8].u_dio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	958	958	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	958	958
T1	1	1
T2	1	1
T3	1	1
T29	1	1
T58	1	1
T68	1	1
T85	1	1
T86	1	1
T87	1	1
T88	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[9].u_dio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[9].u_dio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T10,T11,T12
1	0	Covered	T26,T27,T28
1	1	Covered	T26,T27,T28

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T26,T27,T28
1	0	Covered	T10,T11,T12
1	1	Covered	T26,T27,T28

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T28,T35
1	1	Covered	T10,T11,T12

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T26,T27,T28
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T26,T27,T28

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T26,T27,T28

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T26,T27,T28
1	0	Covered	T10,T11,T12
1	1	Covered	T26,T27,T28

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T11,T12

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T10,T11,T12

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T11,T12

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[9].u_dio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00



	LineNo.	Expression
-1-:	74	(ie_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[9].u_dio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	958	958	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	958	958
T1	1	1
T2	1	1
T3	1	1
T29	1	1
T58	1	1
T68	1	1
T85	1	1
T86	1	1
T87	1	1
T88	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[10].u_dio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[10].u_dio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T10,T11,T12
1	0	Covered	T26,T27,T28
1	1	Covered	T26,T27,T28

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T26,T27,T28
1	0	Covered	T10,T11,T8
1	1	Covered	T26,T27,T28

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T8,T9,T26

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T26,T27,T28
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T26,T27,T28

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T26,T27,T28

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T26,T27,T28
1	0	Covered	T8,T9,T26
1	1	Covered	T26,T27,T28

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T9,T26

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T8,T9,T26

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T11,T12

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[10].u_dio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00



	LineNo.	Expression
-1-:	74	(ie_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T26
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[10].u_dio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	958	958	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	958	958
T1	1	1
T2	1	1
T3	1	1
T29	1	1
T58	1	1
T68	1	1
T85	1	1
T86	1	1
T87	1	1
T88	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].u_dio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].u_dio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T77
0	1	Covered	T10,T11,T12
1	0	Covered	T26,T27,T28
1	1	Covered	T26,T27,T28

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T26,T27,T28
1	0	Covered	T10,T11,T8
1	1	Covered	T26,T27,T28

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T8,T9,T26

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T26,T27,T28
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T26,T27,T28

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T26,T27,T28

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T26,T27,T28
1	0	Covered	T8,T9,T26
1	1	Covered	T26,T27,T28

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T9,T26

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T8,T9,T26

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T11,T12

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].u_dio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00



	LineNo.	Expression
-1-:	74	(ie_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T26
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].u_dio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	958	958	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	958	958
T1	1	1
T2	1	1
T3	1	1
T29	1	1
T58	1	1
T68	1	1
T85	1	1
T86	1	1
T87	1	1
T88	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].u_dio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].u_dio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T77
0	1	Covered	T10,T11,T12
1	0	Covered	T26,T27,T28
1	1	Covered	T26,T27,T28

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T26,T27,T28
1	0	Covered	T10,T11,T8
1	1	Covered	T26,T27,T28

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T28,T35
1	1	Covered	T7,T8,T9

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T26,T27,T28
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T26,T27,T28

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T26,T27,T28

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T26,T27,T28
1	0	Covered	T7,T8,T9
1	1	Covered	T26,T27,T28

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T8,T9

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T7,T8,T9

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T11,T12

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].u_dio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00



	LineNo.	Expression
-1-:	74	(ie_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].u_dio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	958	958	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	958	958
T1	1	1
T2	1	1
T3	1	1
T29	1	1
T58	1	1
T68	1	1
T85	1	1
T86	1	1
T87	1	1
T88	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[13].u_dio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[13].u_dio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T10,T11,T12
1	0	Covered	T26,T27,T28
1	1	Covered	T26,T27,T28

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T26,T27,T28
1	0	Covered	T10,T11,T12
1	1	Covered	T26,T27,T28

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T10,T11,T12

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T26,T27,T28
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T26,T27,T28

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T26,T27,T28

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T26,T27,T28
1	0	Covered	T10,T11,T12
1	1	Covered	T26,T27,T28

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T11,T12

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T10,T11,T12

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T30,T31

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[13].u_dio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00



	LineNo.	Expression
-1-:	74	(ie_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T12,T30,T31
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[13].u_dio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	958	958	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	958	958
T1	1	1
T2	1	1
T3	1	1
T29	1	1
T58	1	1
T68	1	1
T85	1	1
T86	1	1
T87	1	1
T88	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[14].u_dio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[14].u_dio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T10,T11,T12
1	0	Covered	T26,T27,T28
1	1	Covered	T26,T27,T28

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T26,T27,T28
1	0	Covered	T1,T2,T3
1	1	Covered	T26,T27,T28

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T10,T11,T12

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T26,T27,T28
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T26,T27,T28
1	1	Covered	T26,T27,T28

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T26,T27,T28

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T26,T27,T28
1	0	Covered	T10,T11,T12
1	1	Covered	T26,T27,T28

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T11,T12

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T10,T11,T12

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T30,T31

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[14].u_dio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00



	LineNo.	Expression
-1-:	74	(ie_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T12,T30,T31
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[14].u_dio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	958	958	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	958	958
T1	1	1
T2	1	1
T3	1	1
T29	1	1
T58	1	1
T68	1	1
T85	1	1
T86	1	1
T87	1	1
T88	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[15].u_dio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[15].u_dio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T10,T76
0	1	Covered	T4,T10,T76
1	0	Covered	T26,T27,T28
1	1	Covered	T26,T27,T28

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T26,T27,T28
1	0	Covered	T10,T11,T8
1	1	Covered	T26,T27,T28

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T10,T11,T7

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T26,T27,T28
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T26,T27,T28

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T26,T27,T28

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T26,T27,T28
1	0	Covered	T10,T11,T7
1	1	Covered	T26,T27,T28

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T11,T7

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T10,T11,T7

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T26,T27,T28

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[15].u_dio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00



	LineNo.	Expression
-1-:	74	(ie_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T7
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[15].u_dio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	958	958	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	958	958
T1	1	1
T2	1	1
T3	1	1
T29	1	1
T58	1	1
T68	1	1
T85	1	1
T86	1	1
T87	1	1
T88	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[16].u_dio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[16].u_dio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T10,T76
0	1	Covered	T4,T10,T76
1	0	Covered	T26,T27,T28
1	1	Covered	T26,T27,T28

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T26,T27,T28
1	0	Covered	T4,T10,T76
1	1	Covered	T26,T27,T28

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T4,T10,T76

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T26,T27,T28
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T26,T27,T28

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T26,T27,T28

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T26,T27,T28
1	0	Covered	T4,T10,T76
1	1	Covered	T26,T27,T28

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T10,T76

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T4,T10,T76

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T26,T27,T28

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[16].u_dio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00



	LineNo.	Expression
-1-:	74	(ie_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T10,T76
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[16].u_dio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	958	958	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	958	958
T1	1	1
T2	1	1
T3	1	1
T29	1	1
T58	1	1
T68	1	1
T85	1	1
T86	1	1
T87	1	1
T88	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].u_dio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].u_dio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T10,T76
0	1	Covered	T10,T11,T7
1	0	Covered	T26,T27,T28
1	1	Covered	T26,T27,T28

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T26,T27,T28
1	0	Covered	T10,T11,T7
1	1	Covered	T26,T27,T28

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T28,T35
1	1	Covered	T10,T11,T7

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T26,T27,T28
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T26,T27,T28

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T26,T28,T35

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T26,T27,T28
1	0	Covered	T10,T11,T7
1	1	Covered	T26,T28,T35

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T11,T7

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T28,T35
1	1	Covered	T10,T11,T7

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T26,T27,T28

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].u_dio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00



	LineNo.	Expression
-1-:	74	(ie_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T26,T28,T35
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T7
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].u_dio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	958	958	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	958	958
T1	1	1
T2	1	1
T3	1	1
T29	1	1
T58	1	1
T68	1	1
T85	1	1
T86	1	1
T87	1	1
T88	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].u_dio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].u_dio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T10,T76
0	1	Covered	T10,T11,T7
1	0	Covered	T26,T27,T28
1	1	Covered	T26,T28,T35

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T26,T27,T28
1	0	Covered	T10,T11,T189
1	1	Covered	T26,T27,T28

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T10,T11,T189

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T26,T27,T28
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T26,T27,T28

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T26,T27,T28

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T26,T27,T28
1	0	Covered	T10,T11,T189
1	1	Covered	T26,T27,T28

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T11,T189

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T10,T11,T189

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T26,T27,T28

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].u_dio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00



	LineNo.	Expression
-1-:	74	(ie_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T189
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].u_dio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	958	958	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	958	958
T1	1	1
T2	1	1
T3	1	1
T29	1	1
T58	1	1
T68	1	1
T85	1	1
T86	1	1
T87	1	1
T88	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[19].u_dio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	53	0	0
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	67	1	1	100.00

Line No.	Covered	Statements
39		unreachable
53		unreachable
60	1	1
62	1	1
67	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[19].u_dio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	7	7	100.00
Logical	7	7	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       62
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T10,T76
1	0	Covered	T26,T27,T28
1	1	Covered	T26,T27,T28

 LINE       67
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T26,T27,T28

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[19].u_dio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
TERNARY	60	1	1	100.00
TERNARY	67	2	2	100.00



	LineNo.	Expression
-1-:	60	(ie_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



	LineNo.	Expression
-1-:	67	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[19].u_dio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	958	958	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	958	958
T1	1	1
T2	1	1
T3	1	1
T29	1	1
T58	1	1
T68	1	1
T85	1	1
T86	1	1
T87	1	1
T88	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[20].u_dio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	53	0	0
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	67	1	1	100.00

Line No.	Covered	Statements
39		unreachable
53		unreachable
60	1	1
62	1	1
67	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[20].u_dio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	7	7	100.00
Logical	7	7	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       62
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T10,T76
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T26,T27,T28

 LINE       67
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T26,T27,T28

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[20].u_dio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
TERNARY	60	1	1	100.00
TERNARY	67	2	2	100.00



	LineNo.	Expression
-1-:	60	(ie_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



	LineNo.	Expression
-1-:	67	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[20].u_dio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	958	958	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	958	958
T1	1	1
T2	1	1
T3	1	1
T29	1	1
T58	1	1
T68	1	1
T85	1	1
T86	1	1
T87	1	1
T88	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[21].u_dio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[21].u_dio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T43,T19,T20
1	0	Covered	T26,T27,T28
1	1	Covered	T26,T27,T28

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T26,T27,T28
1	0	Covered	T19,T20,T21
1	1	Covered	T26,T27,T28

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T43,T52,T57
1	0	Covered	T26,T27,T28
1	1	Covered	T1,T2,T3

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T26,T27,T28
0	1	Covered	T1,T2,T3
1	0	Covered	T32,T33,T34

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T32,T33,T34

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T26,T28,T35

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T26,T28,T35
1	0	Covered	T1,T2,T3
1	1	Covered	T26,T28,T35

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T43,T52,T57
1	Covered	T1,T2,T3

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T43,T52,T57
1	0	Covered	T26,T28,T35
1	1	Covered	T1,T2,T3

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T26,T27,T28

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[21].u_dio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00



	LineNo.	Expression
-1-:	74	(ie_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T26,T28,T35
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T43,T52,T57



	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[21].u_dio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	958	958	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	958	958
T1	1	1
T2	1	1
T3	1	1
T29	1	1
T58	1	1
T68	1	1
T85	1	1
T86	1	1
T87	1	1
T88	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T43,T19,T32
1	0	Covered	T26,T27,T28
1	1	Covered	T26,T27,T28

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T26,T27,T28
1	0	Covered	T19,T32,T20
1	1	Covered	T26,T27,T28

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T43,T52,T57
1	0	Covered	T32,T33,T34
1	1	Covered	T1,T2,T3

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Covered	T1,T2,T3
1	0	Covered	T32,T33,T34

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T32,T33,T34
1	1	Covered	T32,T33,T34

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T27,T28,T35

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T26,T27,T28
1	0	Covered	T1,T2,T3
1	1	Covered	T27,T28,T35

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T43,T32,T33
1	Covered	T1,T2,T3

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T43,T32,T33
1	0	Covered	T27,T28,T35
1	1	Covered	T1,T2,T3

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T26,T27,T28

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00



	LineNo.	Expression
-1-:	74	(ie_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T27,T28,T35
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T43,T32,T33



	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	958	958	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	958	958
T1	1	1
T2	1	1
T3	1	1
T29	1	1
T58	1	1
T68	1	1
T85	1	1
T86	1	1
T87	1	1
T88	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T26,T27,T28
1	1	Covered	T26,T27,T28

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T26,T27,T28
1	0	Covered	T13,T22,T23
1	1	Covered	T26,T27,T28

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T13,T22,T23

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T26,T27,T28
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T26,T27,T28

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T26,T27,T28

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T26,T27,T28
1	0	Covered	T13,T22,T23
1	1	Covered	T26,T27,T28

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T22,T23

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T13,T22,T23

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T26,T27,T28

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00



	LineNo.	Expression
-1-:	74	(ie_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T13,T22,T23
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	958	958	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	958	958
T1	1	1
T2	1	1
T3	1	1
T29	1	1
T58	1	1
T68	1	1
T85	1	1
T86	1	1
T87	1	1
T88	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T26,T27,T28
1	1	Covered	T26,T27,T28

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T26,T27,T28
1	0	Covered	T13,T14,T15
1	1	Covered	T26,T27,T28

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T13,T14,T15

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T26,T27,T28
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T26,T27,T28

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T26,T27,T28

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T26,T27,T28
1	0	Covered	T13,T14,T15
1	1	Covered	T26,T27,T28

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T14,T15

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T13,T14,T15

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T26,T27,T28

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00



	LineNo.	Expression
-1-:	74	(ie_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	958	958	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	958	958
T1	1	1
T2	1	1
T3	1	1
T29	1	1
T58	1	1
T68	1	1
T85	1	1
T86	1	1
T87	1	1
T88	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T13,T77,T78
0	1	Covered	T13,T12,T30
1	0	Covered	T26,T27,T28
1	1	Covered	T26,T27,T28

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T26,T27,T28
1	0	Covered	T13,T22,T23
1	1	Covered	T26,T27,T28

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T13,T22,T23

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T26,T27,T28
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T26,T27,T28

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T26,T27,T28

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T26,T27,T28
1	0	Covered	T13,T22,T23
1	1	Covered	T26,T27,T28

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T22,T23

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T13,T22,T23

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T30,T31

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00



	LineNo.	Expression
-1-:	74	(ie_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T13,T22,T23
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T12,T30,T31
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	958	958	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	958	958
T1	1	1
T2	1	1
T3	1	1
T29	1	1
T58	1	1
T68	1	1
T85	1	1
T86	1	1
T87	1	1
T88	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T13,T77,T78
0	1	Covered	T13,T22,T23
1	0	Covered	T26,T27,T28
1	1	Covered	T26,T27,T28

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T26,T27,T28
1	0	Covered	T13,T22,T23
1	1	Covered	T26,T27,T28

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T13,T22,T23

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T26,T27,T28
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T26,T27,T28

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T26,T27,T28

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T26,T27,T28
1	0	Covered	T13,T22,T23
1	1	Covered	T26,T27,T28

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T22,T23

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T13,T22,T23

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T26,T27,T28

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00



	LineNo.	Expression
-1-:	74	(ie_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T13,T22,T23
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	958	958	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	958	958
T1	1	1
T2	1	1
T3	1	1
T29	1	1
T58	1	1
T68	1	1
T85	1	1
T86	1	1
T87	1	1
T88	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T172,T186,T13
0	1	Covered	T172,T186,T13
1	0	Covered	T26,T27,T28
1	1	Covered	T26,T27,T28

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T26,T27,T28
1	0	Covered	T13,T22,T23
1	1	Covered	T26,T27,T28

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T13,T22,T23

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T26,T27,T28
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T26,T27,T28

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T26,T27,T28

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T26,T27,T28
1	0	Covered	T13,T22,T23
1	1	Covered	T26,T27,T28

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T22,T23

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T13,T22,T23

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T26,T27,T28

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00



	LineNo.	Expression
-1-:	74	(ie_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T13,T22,T23
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T28
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	958	958	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	958	958
T1	1	1
T2	1	1
T3	1	1
T29	1	1
T58	1	1
T68	1	1
T85	1	1
T86	1	1
T87	1	1
T88	1	1

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[1].u_dio_pad

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[2].u_dio_pad

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00