Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T180,T181,T283
0	1	Covered	T180,T181,T283
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T180,T181,T283
1	Covered	T180,T181,T283

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T180,T181,T283
1	Covered	T180,T181,T283

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T180,T181,T283
1	1	Covered	T180,T181,T283

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T180,T181,T283
1	0	Covered	T180,T181,T283
1	1	Covered	T180,T181,T283

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T180,T181,T283

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T180,T181,T283
0	Covered	T180,T181,T283

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T180,T181,T283
0	Covered	T180,T181,T283

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	850650256	833618958	0	0
CheckNGreaterZero_A	1916	1916	0	0
GntImpliesReady_A	850650256	5454	0	0
GntImpliesValid_A	850650256	5454	0	0
GrantKnown_A	850650256	833618958	0	0
IdxKnown_A	850650256	833618958	0	0
IndexIsCorrect_A	850650256	5454	0	0
NoReadyValidNoGrant_A	850650256	0	0	0
Priority_A	850650256	5454	0	0
ReadyAndValidImplyGrant_A	850650256	5454	0	0
ReqAndReadyImplyGrant_A	850650256	5454	0	0
ReqImpliesValid_A	850650256	5454	0	0
ValidKnown_A	850650256	833618958	0	0
gen_data_port_assertion.DataFlow_A	850650256	5454	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	850650256	833618958	0	0
T1	334352	334340	0	0
T2	441166	440940	0	0
T3	469870	469658	0	0
T29	1165992	1165468	0	0
T58	435946	435720	0	0
T68	1573416	1573314	0	0
T85	531982	531858	0	0
T86	377550	377318	0	0
T87	143386	143270	0	0
T88	381016	380892	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1916	1916	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T29	2	2	0	0
T58	2	2	0	0
T68	2	2	0	0
T85	2	2	0	0
T86	2	2	0	0
T87	2	2	0	0
T88	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	850650256	5454	0	0
T180	148912	1820	0	0
T181	0	1814	0	0
T283	0	1820	0	0
T331	568430	0	0	0
T378	184990	0	0	0
T379	423952	0	0	0
T380	178306	0	0	0
T381	80622	0	0	0
T382	408228	0	0	0
T383	268122	0	0	0
T384	98614	0	0	0
T385	206570	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	850650256	5454	0	0
T180	148912	1820	0	0
T181	0	1814	0	0
T283	0	1820	0	0
T331	568430	0	0	0
T378	184990	0	0	0
T379	423952	0	0	0
T380	178306	0	0	0
T381	80622	0	0	0
T382	408228	0	0	0
T383	268122	0	0	0
T384	98614	0	0	0
T385	206570	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	850650256	833618958	0	0
T1	334352	334340	0	0
T2	441166	440940	0	0
T3	469870	469658	0	0
T29	1165992	1165468	0	0
T58	435946	435720	0	0
T68	1573416	1573314	0	0
T85	531982	531858	0	0
T86	377550	377318	0	0
T87	143386	143270	0	0
T88	381016	380892	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	850650256	833618958	0	0
T1	334352	334340	0	0
T2	441166	440940	0	0
T3	469870	469658	0	0
T29	1165992	1165468	0	0
T58	435946	435720	0	0
T68	1573416	1573314	0	0
T85	531982	531858	0	0
T86	377550	377318	0	0
T87	143386	143270	0	0
T88	381016	380892	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	850650256	5454	0	0
T180	148912	1820	0	0
T181	0	1814	0	0
T283	0	1820	0	0
T331	568430	0	0	0
T378	184990	0	0	0
T379	423952	0	0	0
T380	178306	0	0	0
T381	80622	0	0	0
T382	408228	0	0	0
T383	268122	0	0	0
T384	98614	0	0	0
T385	206570	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	850650256	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	850650256	5454	0	0
T180	148912	1820	0	0
T181	0	1814	0	0
T283	0	1820	0	0
T331	568430	0	0	0
T378	184990	0	0	0
T379	423952	0	0	0
T380	178306	0	0	0
T381	80622	0	0	0
T382	408228	0	0	0
T383	268122	0	0	0
T384	98614	0	0	0
T385	206570	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	850650256	5454	0	0
T180	148912	1820	0	0
T181	0	1814	0	0
T283	0	1820	0	0
T331	568430	0	0	0
T378	184990	0	0	0
T379	423952	0	0	0
T380	178306	0	0	0
T381	80622	0	0	0
T382	408228	0	0	0
T383	268122	0	0	0
T384	98614	0	0	0
T385	206570	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	850650256	5454	0	0
T180	148912	1820	0	0
T181	0	1814	0	0
T283	0	1820	0	0
T331	568430	0	0	0
T378	184990	0	0	0
T379	423952	0	0	0
T380	178306	0	0	0
T381	80622	0	0	0
T382	408228	0	0	0
T383	268122	0	0	0
T384	98614	0	0	0
T385	206570	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	850650256	5454	0	0
T180	148912	1820	0	0
T181	0	1814	0	0
T283	0	1820	0	0
T331	568430	0	0	0
T378	184990	0	0	0
T379	423952	0	0	0
T380	178306	0	0	0
T381	80622	0	0	0
T382	408228	0	0	0
T383	268122	0	0	0
T384	98614	0	0	0
T385	206570	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	850650256	833618958	0	0
T1	334352	334340	0	0
T2	441166	440940	0	0
T3	469870	469658	0	0
T29	1165992	1165468	0	0
T58	435946	435720	0	0
T68	1573416	1573314	0	0
T85	531982	531858	0	0
T86	377550	377318	0	0
T87	143386	143270	0	0
T88	381016	380892	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	850650256	5454	0	0
T180	148912	1820	0	0
T181	0	1814	0	0
T283	0	1820	0	0
T331	568430	0	0	0
T378	184990	0	0	0
T379	423952	0	0	0
T380	178306	0	0	0
T381	80622	0	0	0
T382	408228	0	0	0
T383	268122	0	0	0
T384	98614	0	0	0
T385	206570	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T180,T181,T283
0	1	Covered	T180,T181,T283
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T180,T181,T283
1	Covered	T180,T181,T283

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T180,T181,T283
1	Covered	T180,T181,T283

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T180,T181,T283
1	1	Covered	T180,T181,T283

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T180,T181,T283
1	0	Covered	T180,T181,T283
1	1	Covered	T180,T181,T283

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T180,T181,T283

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T180,T181,T283
0	Covered	T180,T181,T283

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T180,T181,T283
0	Covered	T180,T181,T283

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425325128	416809479	0	0
CheckNGreaterZero_A	958	958	0	0
GntImpliesReady_A	425325128	4416	0	0
GntImpliesValid_A	425325128	4416	0	0
GrantKnown_A	425325128	416809479	0	0
IdxKnown_A	425325128	416809479	0	0
IndexIsCorrect_A	425325128	4416	0	0
NoReadyValidNoGrant_A	425325128	0	0	0
Priority_A	425325128	4416	0	0
ReadyAndValidImplyGrant_A	425325128	4416	0	0
ReqAndReadyImplyGrant_A	425325128	4416	0	0
ReqImpliesValid_A	425325128	4416	0	0
ValidKnown_A	425325128	416809479	0	0
gen_data_port_assertion.DataFlow_A	425325128	4416	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425325128	416809479	0	0
T1	167176	167170	0	0
T2	220583	220470	0	0
T3	234935	234829	0	0
T29	582996	582734	0	0
T58	217973	217860	0	0
T68	786708	786657	0	0
T85	265991	265929	0	0
T86	188775	188659	0	0
T87	71693	71635	0	0
T88	190508	190446	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	958	958	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T29	1	1	0	0
T58	1	1	0	0
T68	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425325128	4416	0	0
T180	74456	1474	0	0
T181	0	1468	0	0
T283	0	1474	0	0
T331	284215	0	0	0
T378	92495	0	0	0
T379	211976	0	0	0
T380	89153	0	0	0
T381	40311	0	0	0
T382	204114	0	0	0
T383	134061	0	0	0
T384	49307	0	0	0
T385	103285	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425325128	4416	0	0
T180	74456	1474	0	0
T181	0	1468	0	0
T283	0	1474	0	0
T331	284215	0	0	0
T378	92495	0	0	0
T379	211976	0	0	0
T380	89153	0	0	0
T381	40311	0	0	0
T382	204114	0	0	0
T383	134061	0	0	0
T384	49307	0	0	0
T385	103285	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425325128	416809479	0	0
T1	167176	167170	0	0
T2	220583	220470	0	0
T3	234935	234829	0	0
T29	582996	582734	0	0
T58	217973	217860	0	0
T68	786708	786657	0	0
T85	265991	265929	0	0
T86	188775	188659	0	0
T87	71693	71635	0	0
T88	190508	190446	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425325128	416809479	0	0
T1	167176	167170	0	0
T2	220583	220470	0	0
T3	234935	234829	0	0
T29	582996	582734	0	0
T58	217973	217860	0	0
T68	786708	786657	0	0
T85	265991	265929	0	0
T86	188775	188659	0	0
T87	71693	71635	0	0
T88	190508	190446	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425325128	4416	0	0
T180	74456	1474	0	0
T181	0	1468	0	0
T283	0	1474	0	0
T331	284215	0	0	0
T378	92495	0	0	0
T379	211976	0	0	0
T380	89153	0	0	0
T381	40311	0	0	0
T382	204114	0	0	0
T383	134061	0	0	0
T384	49307	0	0	0
T385	103285	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425325128	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425325128	4416	0	0
T180	74456	1474	0	0
T181	0	1468	0	0
T283	0	1474	0	0
T331	284215	0	0	0
T378	92495	0	0	0
T379	211976	0	0	0
T380	89153	0	0	0
T381	40311	0	0	0
T382	204114	0	0	0
T383	134061	0	0	0
T384	49307	0	0	0
T385	103285	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425325128	4416	0	0
T180	74456	1474	0	0
T181	0	1468	0	0
T283	0	1474	0	0
T331	284215	0	0	0
T378	92495	0	0	0
T379	211976	0	0	0
T380	89153	0	0	0
T381	40311	0	0	0
T382	204114	0	0	0
T383	134061	0	0	0
T384	49307	0	0	0
T385	103285	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425325128	4416	0	0
T180	74456	1474	0	0
T181	0	1468	0	0
T283	0	1474	0	0
T331	284215	0	0	0
T378	92495	0	0	0
T379	211976	0	0	0
T380	89153	0	0	0
T381	40311	0	0	0
T382	204114	0	0	0
T383	134061	0	0	0
T384	49307	0	0	0
T385	103285	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425325128	4416	0	0
T180	74456	1474	0	0
T181	0	1468	0	0
T283	0	1474	0	0
T331	284215	0	0	0
T378	92495	0	0	0
T379	211976	0	0	0
T380	89153	0	0	0
T381	40311	0	0	0
T382	204114	0	0	0
T383	134061	0	0	0
T384	49307	0	0	0
T385	103285	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425325128	416809479	0	0
T1	167176	167170	0	0
T2	220583	220470	0	0
T3	234935	234829	0	0
T29	582996	582734	0	0
T58	217973	217860	0	0
T68	786708	786657	0	0
T85	265991	265929	0	0
T86	188775	188659	0	0
T87	71693	71635	0	0
T88	190508	190446	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425325128	4416	0	0
T180	74456	1474	0	0
T181	0	1468	0	0
T283	0	1474	0	0
T331	284215	0	0	0
T378	92495	0	0	0
T379	211976	0	0	0
T380	89153	0	0	0
T381	40311	0	0	0
T382	204114	0	0	0
T383	134061	0	0	0
T384	49307	0	0	0
T385	103285	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T180,T181,T283
0	1	Covered	T180,T181,T283
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T180,T181,T283
1	Covered	T180,T181,T283

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T180,T181,T283
1	Covered	T180,T181,T283

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T180,T181,T283
1	1	Covered	T180,T181,T283

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T180,T181,T283
1	0	Covered	T180,T181,T283
1	1	Covered	T180,T181,T283

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T180,T181,T283

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T180,T181,T283
0	Covered	T180,T181,T283

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T180,T181,T283
0	Covered	T180,T181,T283

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425325128	416809479	0	0
CheckNGreaterZero_A	958	958	0	0
GntImpliesReady_A	425325128	1038	0	0
GntImpliesValid_A	425325128	1038	0	0
GrantKnown_A	425325128	416809479	0	0
IdxKnown_A	425325128	416809479	0	0
IndexIsCorrect_A	425325128	1038	0	0
NoReadyValidNoGrant_A	425325128	0	0	0
Priority_A	425325128	1038	0	0
ReadyAndValidImplyGrant_A	425325128	1038	0	0
ReqAndReadyImplyGrant_A	425325128	1038	0	0
ReqImpliesValid_A	425325128	1038	0	0
ValidKnown_A	425325128	416809479	0	0
gen_data_port_assertion.DataFlow_A	425325128	1038	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425325128	416809479	0	0
T1	167176	167170	0	0
T2	220583	220470	0	0
T3	234935	234829	0	0
T29	582996	582734	0	0
T58	217973	217860	0	0
T68	786708	786657	0	0
T85	265991	265929	0	0
T86	188775	188659	0	0
T87	71693	71635	0	0
T88	190508	190446	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	958	958	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T29	1	1	0	0
T58	1	1	0	0
T68	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425325128	1038	0	0
T180	74456	346	0	0
T181	0	346	0	0
T283	0	346	0	0
T331	284215	0	0	0
T378	92495	0	0	0
T379	211976	0	0	0
T380	89153	0	0	0
T381	40311	0	0	0
T382	204114	0	0	0
T383	134061	0	0	0
T384	49307	0	0	0
T385	103285	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425325128	1038	0	0
T180	74456	346	0	0
T181	0	346	0	0
T283	0	346	0	0
T331	284215	0	0	0
T378	92495	0	0	0
T379	211976	0	0	0
T380	89153	0	0	0
T381	40311	0	0	0
T382	204114	0	0	0
T383	134061	0	0	0
T384	49307	0	0	0
T385	103285	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425325128	416809479	0	0
T1	167176	167170	0	0
T2	220583	220470	0	0
T3	234935	234829	0	0
T29	582996	582734	0	0
T58	217973	217860	0	0
T68	786708	786657	0	0
T85	265991	265929	0	0
T86	188775	188659	0	0
T87	71693	71635	0	0
T88	190508	190446	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425325128	416809479	0	0
T1	167176	167170	0	0
T2	220583	220470	0	0
T3	234935	234829	0	0
T29	582996	582734	0	0
T58	217973	217860	0	0
T68	786708	786657	0	0
T85	265991	265929	0	0
T86	188775	188659	0	0
T87	71693	71635	0	0
T88	190508	190446	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425325128	1038	0	0
T180	74456	346	0	0
T181	0	346	0	0
T283	0	346	0	0
T331	284215	0	0	0
T378	92495	0	0	0
T379	211976	0	0	0
T380	89153	0	0	0
T381	40311	0	0	0
T382	204114	0	0	0
T383	134061	0	0	0
T384	49307	0	0	0
T385	103285	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425325128	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425325128	1038	0	0
T180	74456	346	0	0
T181	0	346	0	0
T283	0	346	0	0
T331	284215	0	0	0
T378	92495	0	0	0
T379	211976	0	0	0
T380	89153	0	0	0
T381	40311	0	0	0
T382	204114	0	0	0
T383	134061	0	0	0
T384	49307	0	0	0
T385	103285	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425325128	1038	0	0
T180	74456	346	0	0
T181	0	346	0	0
T283	0	346	0	0
T331	284215	0	0	0
T378	92495	0	0	0
T379	211976	0	0	0
T380	89153	0	0	0
T381	40311	0	0	0
T382	204114	0	0	0
T383	134061	0	0	0
T384	49307	0	0	0
T385	103285	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425325128	1038	0	0
T180	74456	346	0	0
T181	0	346	0	0
T283	0	346	0	0
T331	284215	0	0	0
T378	92495	0	0	0
T379	211976	0	0	0
T380	89153	0	0	0
T381	40311	0	0	0
T382	204114	0	0	0
T383	134061	0	0	0
T384	49307	0	0	0
T385	103285	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425325128	1038	0	0
T180	74456	346	0	0
T181	0	346	0	0
T283	0	346	0	0
T331	284215	0	0	0
T378	92495	0	0	0
T379	211976	0	0	0
T380	89153	0	0	0
T381	40311	0	0	0
T382	204114	0	0	0
T383	134061	0	0	0
T384	49307	0	0	0
T385	103285	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425325128	416809479	0	0
T1	167176	167170	0	0
T2	220583	220470	0	0
T3	234935	234829	0	0
T29	582996	582734	0	0
T58	217973	217860	0	0
T68	786708	786657	0	0
T85	265991	265929	0	0
T86	188775	188659	0	0
T87	71693	71635	0	0
T88	190508	190446	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425325128	1038	0	0
T180	74456	346	0	0
T181	0	346	0	0
T283	0	346	0	0
T331	284215	0	0	0
T378	92495	0	0	0
T379	211976	0	0	0
T380	89153	0	0	0
T381	40311	0	0	0
T382	204114	0	0	0
T383	134061	0	0	0
T384	49307	0	0	0
T385	103285	0	0	0