Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1115861	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

29763719

1

T1

33630

T2

33629

T3

7243

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	20357398	1			T1	19730		T2	19729		T3	1935
values[0x0]	9405342	1			T1	13900		T2	13900		T3	5308
values[0x1]	1116840	1			T1	1428		T2	1428		T3	232

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8968	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

30870612

1

T1

35058

T2

35057

T3

7475

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15426000	1			T1	17534		T2	17533		T3	3738
valid_sources[0x01]	15424895	1			T1	17524		T2	17524		T3	3737
valid_sources[0x02]	345	1			T79	1		T80	3		T52	2
valid_sources[0x03]	384	1			T79	6		T26	47		T27	57
valid_sources[0x04]	412	1			T335	11		T26	50		T27	46
valid_sources[0x05]	451	1			T81	39		T26	47		T27	39
valid_sources[0x06]	335	1			T79	1		T335	23		T26	36
valid_sources[0x07]	299	1			T26	41		T27	28		T31	35
valid_sources[0x08]	332	1			T79	1		T26	42		T27	38
valid_sources[0x09]	317	1			T26	41		T27	50		T31	44
valid_sources[0x0a]	2714	1			T79	1		T80	1		T26	51
valid_sources[0x0b]	325	1			T79	1		T80	2		T26	51
valid_sources[0x0c]	326	1			T26	41		T27	40		T31	30
valid_sources[0x0d]	328	1			T80	3		T26	32		T27	37
valid_sources[0x0e]	331	1			T80	3		T52	2		T26	41
valid_sources[0x0f]	376	1			T26	43		T27	49		T31	46
valid_sources[0x10]	357	1			T80	1		T26	40		T27	48
valid_sources[0x11]	309	1			T52	3		T26	52		T27	46
valid_sources[0x12]	366	1			T79	3		T80	2		T26	50
valid_sources[0x13]	350	1			T26	47		T27	45		T31	26
valid_sources[0x14]	356	1			T26	36		T27	45		T31	32
valid_sources[0x15]	342	1			T79	5		T26	41		T27	44
valid_sources[0x16]	402	1			T79	1		T80	1		T52	4
valid_sources[0x17]	401	1			T52	3		T26	51		T27	53
valid_sources[0x18]	376	1			T26	47		T27	42		T31	44
valid_sources[0x19]	335	1			T80	2		T52	3		T146	39
valid_sources[0x1a]	344	1			T26	49		T27	46		T31	60
valid_sources[0x1b]	365	1			T26	50		T27	38		T31	47
valid_sources[0x1c]	351	1			T26	45		T27	46		T31	57
valid_sources[0x1d]	343	1			T26	40		T27	46		T31	46
valid_sources[0x1e]	386	1			T79	1		T26	40		T27	50
valid_sources[0x1f]	417	1			T26	36		T27	38		T31	52
valid_sources[0x20]	390	1			T26	44		T27	36		T31	46

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

20357398

1

T1

19730

T2

19729

T3

1935

values[0x0]

all_enables

biggest_size

9400755

1

T1

13900

T2

13900

T3

5308

values[0x1]

all_enables

biggest_size

5566

1

T79

25

T80

24

T81

20