| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 90.47 | 93.52 | 83.37 | 90.65 | 94.80 | 97.38 | 83.11 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP | |||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 41.60 | 41.60 | 40.48 | 40.48 | 41.22 | 41.22 | 25.07 | 25.07 | 57.33 | 57.33 | 61.37 | 61.37 | 24.12 | 24.12 | /workspace/coverage/default/1.chip_sw_alert_handler_entropy.3657883248 | ||
| 55.01 | 13.41 | 53.15 | 12.66 | 55.09 | 13.88 | 28.41 | 3.34 | 70.12 | 12.79 | 89.09 | 27.73 | 34.21 | 10.09 | /workspace/coverage/default/2.chip_jtag_csr_rw.229721189 | ||
| 61.21 | 6.20 | 63.28 | 10.13 | 62.42 | 7.33 | 33.68 | 5.27 | 78.68 | 8.56 | 89.28 | 0.18 | 39.91 | 5.70 | /workspace/coverage/default/1.chip_jtag_csr_rw.1285615732 | ||
| 65.67 | 4.46 | 69.68 | 6.40 | 66.29 | 3.87 | 43.33 | 9.65 | 81.02 | 2.34 | 90.94 | 1.66 | 42.76 | 2.85 | /workspace/coverage/default/98.chip_sw_all_escalation_resets.432711832 | ||
| 70.01 | 4.34 | 79.69 | 10.01 | 71.38 | 5.09 | 47.31 | 3.98 | 83.36 | 2.34 | 90.94 | 0.00 | 47.37 | 4.61 | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.2804705801 | ||
| 73.80 | 3.79 | 79.69 | 0.00 | 71.41 | 0.03 | 50.30 | 2.99 | 83.36 | 0.00 | 90.94 | 0.00 | 67.11 | 19.74 | /workspace/coverage/default/0.chip_sw_alert_test.1687653760 | ||
| 76.60 | 2.80 | 79.69 | 0.00 | 71.41 | 0.00 | 67.09 | 16.80 | 83.36 | 0.00 | 90.94 | 0.00 | 67.11 | 0.00 | /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.691299486 | ||
| 78.30 | 1.70 | 79.92 | 0.24 | 71.57 | 0.16 | 76.38 | 9.28 | 83.54 | 0.18 | 91.31 | 0.37 | 67.11 | 0.00 | /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.1779780699 | ||
| 79.88 | 1.58 | 83.46 | 3.54 | 73.75 | 2.18 | 77.64 | 1.27 | 86.01 | 2.47 | 91.31 | 0.00 | 67.11 | 0.00 | /workspace/coverage/default/2.chip_plic_all_irqs_0.2430766367 | ||
| 81.26 | 1.37 | 85.53 | 2.07 | 76.79 | 3.04 | 77.88 | 0.23 | 88.92 | 2.90 | 91.31 | 0.00 | 67.11 | 0.00 | /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.2947653147 | ||
| 82.26 | 1.01 | 87.44 | 1.91 | 78.11 | 1.32 | 78.97 | 1.09 | 90.63 | 1.71 | 91.31 | 0.00 | 67.11 | 0.00 | /workspace/coverage/default/0.chip_plic_all_irqs_20.553404899 | ||
| 83.03 | 0.77 | 87.75 | 0.30 | 78.23 | 0.12 | 78.99 | 0.02 | 90.76 | 0.13 | 95.38 | 4.07 | 67.11 | 0.00 | /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1342746858 | ||
| 83.74 | 0.70 | 88.73 | 0.99 | 79.17 | 0.94 | 80.15 | 1.16 | 91.48 | 0.72 | 95.56 | 0.18 | 67.32 | 0.22 | /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1636624407 | ||
| 84.19 | 0.46 | 88.73 | 0.00 | 79.20 | 0.03 | 82.64 | 2.49 | 91.49 | 0.02 | 95.56 | 0.00 | 67.54 | 0.22 | /workspace/coverage/default/2.chip_sw_flash_init.1557862228 | ||
| 84.61 | 0.41 | 89.52 | 0.79 | 79.77 | 0.57 | 82.89 | 0.25 | 92.35 | 0.86 | 95.56 | 0.00 | 67.54 | 0.00 | /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.3473511020 | ||
| 84.96 | 0.36 | 90.00 | 0.48 | 80.19 | 0.42 | 83.16 | 0.27 | 92.77 | 0.42 | 96.12 | 0.55 | 67.54 | 0.00 | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.230488511 | ||
| 85.29 | 0.32 | 90.68 | 0.69 | 80.63 | 0.45 | 83.63 | 0.47 | 93.11 | 0.34 | 96.12 | 0.00 | 67.54 | 0.00 | /workspace/coverage/default/2.chip_sw_gpio.564705632 | ||
| 85.58 | 0.30 | 90.72 | 0.03 | 80.64 | 0.01 | 83.65 | 0.02 | 93.12 | 0.01 | 96.30 | 0.18 | 69.08 | 1.54 | /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.2970662350 | ||
| 85.85 | 0.26 | 91.25 | 0.53 | 81.09 | 0.45 | 83.79 | 0.14 | 93.56 | 0.45 | 96.30 | 0.00 | 69.08 | 0.00 | /workspace/coverage/default/1.chip_plic_all_irqs_10.1969715703 | ||
| 86.08 | 0.24 | 91.26 | 0.01 | 81.10 | 0.01 | 85.01 | 1.23 | 93.56 | 0.00 | 96.49 | 0.18 | 69.08 | 0.00 | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.3397635454 | ||
| 86.29 | 0.21 | 91.26 | 0.00 | 81.10 | 0.00 | 86.26 | 1.25 | 93.56 | 0.00 | 96.49 | 0.00 | 69.08 | 0.00 | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.1862019988 | ||
| 86.46 | 0.17 | 91.58 | 0.32 | 81.27 | 0.17 | 86.27 | 0.01 | 93.67 | 0.11 | 96.67 | 0.18 | 69.30 | 0.22 | /workspace/coverage/default/81.chip_sw_all_escalation_resets.3923822104 | ||
| 86.61 | 0.15 | 91.80 | 0.22 | 81.60 | 0.33 | 86.63 | 0.36 | 93.67 | 0.00 | 96.67 | 0.00 | 69.30 | 0.00 | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2070973319 | ||
| 86.74 | 0.13 | 91.88 | 0.08 | 81.90 | 0.31 | 86.69 | 0.06 | 93.99 | 0.32 | 96.67 | 0.00 | 69.30 | 0.00 | /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2833283294 | ||
| 86.86 | 0.12 | 91.88 | 0.00 | 81.90 | 0.00 | 87.40 | 0.71 | 93.99 | 0.00 | 96.67 | 0.00 | 69.30 | 0.00 | /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.875781843 | ||
| 86.95 | 0.09 | 92.34 | 0.46 | 81.95 | 0.05 | 87.43 | 0.04 | 93.99 | 0.00 | 96.67 | 0.00 | 69.30 | 0.00 | /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2847785930 | ||
| 87.04 | 0.09 | 92.34 | 0.01 | 82.18 | 0.23 | 87.46 | 0.03 | 94.26 | 0.26 | 96.67 | 0.00 | 69.30 | 0.00 | /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3617860354 | ||
| 87.12 | 0.08 | 92.36 | 0.02 | 82.22 | 0.04 | 87.61 | 0.15 | 94.31 | 0.05 | 96.67 | 0.00 | 69.52 | 0.22 | /workspace/coverage/default/3.chip_sw_all_escalation_resets.3311521392 | ||
| 87.19 | 0.08 | 92.36 | 0.00 | 82.22 | 0.00 | 88.08 | 0.47 | 94.31 | 0.00 | 96.67 | 0.00 | 69.52 | 0.00 | /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.935477401 | ||
| 87.27 | 0.08 | 92.37 | 0.01 | 82.24 | 0.01 | 88.08 | 0.00 | 94.33 | 0.02 | 96.86 | 0.18 | 69.74 | 0.22 | /workspace/coverage/default/13.chip_sw_all_escalation_resets.218521011 | ||
| 87.34 | 0.07 | 92.38 | 0.01 | 82.25 | 0.01 | 88.09 | 0.01 | 94.34 | 0.01 | 97.04 | 0.18 | 69.96 | 0.22 | /workspace/coverage/default/20.chip_sw_all_escalation_resets.1798062235 | ||
| 87.40 | 0.06 | 92.38 | 0.00 | 82.25 | 0.00 | 88.24 | 0.15 | 94.34 | 0.00 | 97.04 | 0.00 | 70.18 | 0.22 | /workspace/coverage/default/29.chip_sw_all_escalation_resets.2792511659 | ||
| 87.46 | 0.05 | 92.40 | 0.03 | 82.27 | 0.02 | 88.32 | 0.08 | 94.35 | 0.02 | 97.23 | 0.18 | 70.18 | 0.00 | /workspace/coverage/default/0.chip_sw_data_integrity_escalation.2195338188 | ||
| 87.51 | 0.05 | 92.49 | 0.09 | 82.34 | 0.06 | 88.40 | 0.08 | 94.41 | 0.06 | 97.23 | 0.00 | 70.18 | 0.00 | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.2758230778 | ||
| 87.55 | 0.05 | 92.49 | 0.00 | 82.34 | 0.00 | 88.47 | 0.06 | 94.41 | 0.00 | 97.23 | 0.00 | 70.39 | 0.22 | /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2899002049 | ||
| 87.60 | 0.04 | 92.49 | 0.00 | 82.34 | 0.00 | 88.73 | 0.27 | 94.41 | 0.00 | 97.23 | 0.00 | 70.39 | 0.00 | /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.4166651040 | ||
| 87.64 | 0.04 | 92.62 | 0.13 | 82.34 | 0.01 | 88.84 | 0.11 | 94.43 | 0.02 | 97.23 | 0.00 | 70.39 | 0.00 | /workspace/coverage/default/3.chip_tap_straps_rma.2709772342 | ||
| 87.68 | 0.04 | 92.62 | 0.00 | 82.34 | 0.00 | 88.87 | 0.03 | 94.43 | 0.00 | 97.23 | 0.00 | 70.61 | 0.22 | /workspace/coverage/default/30.chip_sw_all_escalation_resets.283586431 | ||
| 87.72 | 0.04 | 92.66 | 0.04 | 82.47 | 0.13 | 88.87 | 0.00 | 94.50 | 0.07 | 97.23 | 0.00 | 70.61 | 0.00 | /workspace/coverage/default/1.chip_sw_sleep_pin_retention.1719575558 | ||
| 87.76 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.89 | 0.01 | 94.50 | 0.00 | 97.23 | 0.00 | 70.83 | 0.22 | /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.145866304 | ||
| 87.80 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.90 | 0.01 | 94.50 | 0.00 | 97.23 | 0.00 | 71.05 | 0.22 | /workspace/coverage/default/18.chip_sw_all_escalation_resets.3414065648 | ||
| 87.84 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.01 | 94.50 | 0.00 | 97.23 | 0.00 | 71.27 | 0.22 | /workspace/coverage/default/72.chip_sw_all_escalation_resets.3110558221 | ||
| 87.88 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.01 | 94.50 | 0.00 | 97.23 | 0.00 | 71.49 | 0.22 | /workspace/coverage/default/85.chip_sw_all_escalation_resets.327008022 | ||
| 87.91 | 0.04 | 92.66 | 0.00 | 82.47 | 0.01 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 71.71 | 0.22 | /workspace/coverage/default/38.chip_sw_all_escalation_resets.3236437159 | ||
| 87.95 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.01 | 94.50 | 0.00 | 97.23 | 0.00 | 71.93 | 0.22 | /workspace/coverage/default/8.chip_sw_all_escalation_resets.676510171 | ||
| 87.99 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.01 | 94.50 | 0.00 | 97.23 | 0.00 | 72.15 | 0.22 | /workspace/coverage/default/90.chip_sw_all_escalation_resets.834892751 | ||
| 88.02 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 72.37 | 0.22 | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.3589977320 | ||
| 88.06 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 72.59 | 0.22 | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1280636774 | ||
| 88.10 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 72.81 | 0.22 | /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.622620714 | ||
| 88.13 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 73.03 | 0.22 | /workspace/coverage/default/10.chip_sw_all_escalation_resets.3832653399 | ||
| 88.17 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 73.25 | 0.22 | /workspace/coverage/default/12.chip_sw_all_escalation_resets.3808202516 | ||
| 88.21 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 73.46 | 0.22 | /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.1809013623 | ||
| 88.24 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 73.68 | 0.22 | /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1930537166 | ||
| 88.28 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 73.90 | 0.22 | /workspace/coverage/default/15.chip_sw_all_escalation_resets.1265147139 | ||
| 88.32 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 74.12 | 0.22 | /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.1945128478 | ||
| 88.35 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 74.34 | 0.22 | /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.562510405 | ||
| 88.39 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 74.56 | 0.22 | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.1951831567 | ||
| 88.43 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 74.78 | 0.22 | /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.3018608202 | ||
| 88.46 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 75.00 | 0.22 | /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.3421462541 | ||
| 88.50 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 75.22 | 0.22 | /workspace/coverage/default/21.chip_sw_all_escalation_resets.4261132067 | ||
| 88.54 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 75.44 | 0.22 | /workspace/coverage/default/23.chip_sw_all_escalation_resets.2484376604 | ||
| 88.57 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 75.66 | 0.22 | /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.3031459892 | ||
| 88.61 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 75.88 | 0.22 | /workspace/coverage/default/24.chip_sw_all_escalation_resets.3060272586 | ||
| 88.65 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 76.10 | 0.22 | /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.3593921716 | ||
| 88.68 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 76.32 | 0.22 | /workspace/coverage/default/25.chip_sw_all_escalation_resets.1223210167 | ||
| 88.72 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 76.54 | 0.22 | /workspace/coverage/default/28.chip_sw_all_escalation_resets.3086343644 | ||
| 88.75 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 76.75 | 0.22 | /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.879516653 | ||
| 88.79 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 76.97 | 0.22 | /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.3893147892 | ||
| 88.83 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 77.19 | 0.22 | /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.44225826 | ||
| 88.86 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 77.41 | 0.22 | /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.1677953136 | ||
| 88.90 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 77.63 | 0.22 | /workspace/coverage/default/32.chip_sw_all_escalation_resets.2255197820 | ||
| 88.94 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 77.85 | 0.22 | /workspace/coverage/default/33.chip_sw_all_escalation_resets.2432885924 | ||
| 88.97 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 78.07 | 0.22 | /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.105503810 | ||
| 89.01 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 78.29 | 0.22 | /workspace/coverage/default/35.chip_sw_all_escalation_resets.325235750 | ||
| 89.05 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 78.51 | 0.22 | /workspace/coverage/default/39.chip_sw_all_escalation_resets.3462540884 | ||
| 89.08 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 78.73 | 0.22 | /workspace/coverage/default/4.chip_sw_all_escalation_resets.2741768420 | ||
| 89.12 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 78.95 | 0.22 | /workspace/coverage/default/41.chip_sw_all_escalation_resets.1584557179 | ||
| 89.16 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 79.17 | 0.22 | /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.547050300 | ||
| 89.19 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 79.39 | 0.22 | /workspace/coverage/default/44.chip_sw_all_escalation_resets.833073435 | ||
| 89.23 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 79.61 | 0.22 | /workspace/coverage/default/46.chip_sw_all_escalation_resets.4030475870 | ||
| 89.27 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 79.82 | 0.22 | /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.661998345 | ||
| 89.30 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 80.04 | 0.22 | /workspace/coverage/default/5.chip_sw_all_escalation_resets.1504659938 | ||
| 89.34 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 80.26 | 0.22 | /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.2956022499 | ||
| 89.38 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 80.48 | 0.22 | /workspace/coverage/default/53.chip_sw_all_escalation_resets.939633325 | ||
| 89.41 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 80.70 | 0.22 | /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.2481258155 | ||
| 89.45 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 80.92 | 0.22 | /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.279990911 | ||
| 89.49 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 81.14 | 0.22 | /workspace/coverage/default/58.chip_sw_all_escalation_resets.2523591706 | ||
| 89.52 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 81.36 | 0.22 | /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.2873754566 | ||
| 89.56 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 81.58 | 0.22 | /workspace/coverage/default/60.chip_sw_all_escalation_resets.4225130689 | ||
| 89.60 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 81.80 | 0.22 | /workspace/coverage/default/62.chip_sw_all_escalation_resets.3662154319 | ||
| 89.63 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 82.02 | 0.22 | /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.2648420701 | ||
| 89.67 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 82.24 | 0.22 | /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.947283427 | ||
| 89.71 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 82.46 | 0.22 | /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2229395005 | ||
| 89.74 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 82.68 | 0.22 | /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2937135272 | ||
| 89.78 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 82.89 | 0.22 | /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2473512409 | ||
| 89.81 | 0.04 | 92.66 | 0.00 | 82.47 | 0.00 | 88.91 | 0.00 | 94.50 | 0.00 | 97.23 | 0.00 | 83.11 | 0.22 | /workspace/coverage/default/80.chip_sw_all_escalation_resets.3663643046 | ||
| 89.85 | 0.03 | 92.66 | 0.01 | 82.47 | 0.01 | 89.11 | 0.19 | 94.50 | 0.00 | 97.23 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.4155222068 | ||
| 89.88 | 0.03 | 92.66 | 0.00 | 82.47 | 0.00 | 89.11 | 0.00 | 94.50 | 0.00 | 97.41 | 0.18 | 83.11 | 0.00 | /workspace/coverage/default/1.chip_sw_data_integrity_escalation.505652901 | ||
| 89.91 | 0.03 | 92.66 | 0.00 | 82.47 | 0.00 | 89.27 | 0.16 | 94.50 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.1225414053 | ||
| 89.93 | 0.03 | 92.73 | 0.07 | 82.50 | 0.03 | 89.28 | 0.01 | 94.55 | 0.05 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.2582915961 | ||
| 89.96 | 0.03 | 92.73 | 0.00 | 82.50 | 0.00 | 89.44 | 0.16 | 94.55 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.1795505777 | ||
| 89.98 | 0.03 | 92.79 | 0.06 | 82.57 | 0.06 | 89.44 | 0.00 | 94.58 | 0.02 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/2.chip_sw_sleep_pin_wake.3289390763 | ||
| 90.01 | 0.02 | 92.79 | 0.00 | 82.57 | 0.00 | 89.59 | 0.14 | 94.58 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.3526854603 | ||
| 90.03 | 0.02 | 92.81 | 0.02 | 82.63 | 0.07 | 89.59 | 0.01 | 94.63 | 0.05 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.786234445 | ||
| 90.06 | 0.02 | 92.87 | 0.05 | 82.69 | 0.05 | 89.59 | 0.00 | 94.66 | 0.03 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/0.chip_sw_sleep_pin_wake.171721034 | ||
| 90.08 | 0.02 | 92.87 | 0.00 | 82.83 | 0.14 | 89.59 | 0.00 | 94.66 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/0.chip_plic_all_irqs_0.2176670608 | ||
| 90.10 | 0.02 | 92.90 | 0.03 | 82.88 | 0.05 | 89.61 | 0.02 | 94.68 | 0.02 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2976462248 | ||
| 90.12 | 0.02 | 92.91 | 0.01 | 82.92 | 0.03 | 89.67 | 0.06 | 94.70 | 0.02 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/0.chip_sw_usbdev_pincfg.470102636 | ||
| 90.14 | 0.02 | 92.91 | 0.00 | 82.92 | 0.00 | 89.78 | 0.11 | 94.70 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.2313940332 | ||
| 90.16 | 0.02 | 92.92 | 0.01 | 82.97 | 0.05 | 89.83 | 0.05 | 94.70 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/0.chip_jtag_csr_rw.659062609 | ||
| 90.17 | 0.02 | 92.92 | 0.00 | 82.97 | 0.00 | 89.94 | 0.10 | 94.70 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.149266890 | ||
| 90.19 | 0.02 | 92.95 | 0.03 | 82.98 | 0.01 | 89.99 | 0.06 | 94.70 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/0.chip_sw_spi_device_tpm.3785132577 | ||
| 90.21 | 0.02 | 92.95 | 0.01 | 83.01 | 0.04 | 90.05 | 0.06 | 94.70 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2905777987 | ||
| 90.22 | 0.01 | 92.95 | 0.00 | 83.09 | 0.08 | 90.05 | 0.00 | 94.70 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/1.chip_plic_all_irqs_0.2117643946 | ||
| 90.23 | 0.01 | 92.98 | 0.03 | 83.11 | 0.02 | 90.06 | 0.01 | 94.73 | 0.02 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/96.chip_sw_all_escalation_resets.1005664377 | ||
| 90.24 | 0.01 | 93.04 | 0.06 | 83.11 | 0.01 | 90.06 | 0.00 | 94.73 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3816330953 | ||
| 90.26 | 0.01 | 93.05 | 0.01 | 83.13 | 0.01 | 90.10 | 0.04 | 94.73 | 0.01 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3523193604 | ||
| 90.27 | 0.01 | 93.07 | 0.03 | 83.14 | 0.01 | 90.11 | 0.01 | 94.75 | 0.02 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.416285548 | ||
| 90.27 | 0.01 | 93.10 | 0.03 | 83.14 | 0.01 | 90.12 | 0.01 | 94.77 | 0.02 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1458307867 | ||
| 90.28 | 0.01 | 93.12 | 0.02 | 83.15 | 0.01 | 90.12 | 0.01 | 94.78 | 0.02 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.1002074150 | ||
| 90.29 | 0.01 | 93.12 | 0.00 | 83.15 | 0.00 | 90.17 | 0.05 | 94.78 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.1244917097 | ||
| 90.30 | 0.01 | 93.13 | 0.01 | 83.16 | 0.01 | 90.20 | 0.03 | 94.78 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.2358153457 | ||
| 90.31 | 0.01 | 93.15 | 0.02 | 83.16 | 0.01 | 90.22 | 0.02 | 94.78 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/0.chip_sw_power_idle_load.100142094 | ||
| 90.31 | 0.01 | 93.15 | 0.00 | 83.20 | 0.04 | 90.22 | 0.00 | 94.78 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/0.chip_plic_all_irqs_10.2050407271 | ||
| 90.32 | 0.01 | 93.15 | 0.00 | 83.20 | 0.00 | 90.26 | 0.04 | 94.78 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.96521967 | ||
| 90.33 | 0.01 | 93.15 | 0.00 | 83.20 | 0.00 | 90.30 | 0.04 | 94.78 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.869924940 | ||
| 90.33 | 0.01 | 93.15 | 0.00 | 83.20 | 0.00 | 90.33 | 0.04 | 94.78 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/0.chip_sw_kmac_app_rom.3165192312 | ||
| 90.34 | 0.01 | 93.15 | 0.00 | 83.20 | 0.00 | 90.37 | 0.04 | 94.78 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.510380383 | ||
| 90.34 | 0.01 | 93.18 | 0.03 | 83.20 | 0.00 | 90.38 | 0.01 | 94.78 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.980464770 | ||
| 90.35 | 0.01 | 93.18 | 0.00 | 83.20 | 0.00 | 90.41 | 0.03 | 94.78 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/0.chip_jtag_mem_access.3234567215 | ||
| 90.35 | 0.01 | 93.18 | 0.00 | 83.20 | 0.00 | 90.44 | 0.03 | 94.78 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3838415245 | ||
| 90.36 | 0.01 | 93.18 | 0.00 | 83.23 | 0.03 | 90.44 | 0.00 | 94.78 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/2.chip_plic_all_irqs_20.1513420978 | ||
| 90.36 | 0.01 | 93.18 | 0.00 | 83.23 | 0.00 | 90.47 | 0.03 | 94.78 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2126209095 | ||
| 90.37 | 0.01 | 93.18 | 0.00 | 83.26 | 0.03 | 90.47 | 0.00 | 94.78 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/1.chip_plic_all_irqs_20.3272876906 | ||
| 90.37 | 0.01 | 93.18 | 0.00 | 83.28 | 0.03 | 90.47 | 0.00 | 94.78 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/1.chip_sw_uart_tx_rx.762123659 | ||
| 90.38 | 0.01 | 93.18 | 0.01 | 83.30 | 0.02 | 90.47 | 0.00 | 94.78 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/1.chip_sw_entropy_src_csrng.800751965 | ||
| 90.38 | 0.01 | 93.20 | 0.01 | 83.30 | 0.00 | 90.48 | 0.01 | 94.78 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/0.chip_sw_pattgen_ios.2419266181 | ||
| 90.38 | 0.01 | 93.20 | 0.01 | 83.32 | 0.01 | 90.48 | 0.01 | 94.78 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.1986348886 | ||
| 90.39 | 0.01 | 93.20 | 0.00 | 83.32 | 0.00 | 90.50 | 0.02 | 94.78 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3067306219 | ||
| 90.39 | 0.01 | 93.20 | 0.00 | 83.32 | 0.00 | 90.52 | 0.02 | 94.78 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.470754193 | ||
| 90.39 | 0.01 | 93.20 | 0.00 | 83.32 | 0.00 | 90.53 | 0.01 | 94.79 | 0.01 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.4281660029 | ||
| 90.40 | 0.01 | 93.21 | 0.01 | 83.32 | 0.01 | 90.53 | 0.00 | 94.80 | 0.01 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/1.chip_sw_sleep_pin_wake.3012944570 | ||
| 90.40 | 0.01 | 93.21 | 0.00 | 83.33 | 0.01 | 90.53 | 0.00 | 94.80 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3531434642 | ||
| 90.40 | 0.01 | 93.21 | 0.00 | 83.35 | 0.01 | 90.53 | 0.00 | 94.80 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.1325110208 | ||
| 90.40 | 0.01 | 93.21 | 0.00 | 83.35 | 0.00 | 90.54 | 0.01 | 94.80 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/0.chip_sw_edn_boot_mode.3953226413 | ||
| 90.41 | 0.01 | 93.21 | 0.00 | 83.35 | 0.00 | 90.56 | 0.01 | 94.80 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1861520478 | ||
| 90.41 | 0.01 | 93.21 | 0.00 | 83.35 | 0.00 | 90.57 | 0.01 | 94.80 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.1296893213 | ||
| 90.41 | 0.01 | 93.21 | 0.01 | 83.35 | 0.00 | 90.58 | 0.01 | 94.80 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.3021887683 | ||
| 90.41 | 0.01 | 93.22 | 0.01 | 83.35 | 0.00 | 90.58 | 0.01 | 94.80 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.3873798839 | ||
| 90.41 | 0.01 | 93.23 | 0.01 | 83.35 | 0.00 | 90.59 | 0.01 | 94.80 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1754687644 | ||
| 90.42 | 0.01 | 93.23 | 0.00 | 83.36 | 0.01 | 90.59 | 0.00 | 94.80 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.2147990493 | ||
| 90.42 | 0.01 | 93.23 | 0.00 | 83.36 | 0.00 | 90.59 | 0.01 | 94.80 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.1501241036 | ||
| 90.42 | 0.01 | 93.23 | 0.00 | 83.36 | 0.00 | 90.60 | 0.01 | 94.80 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/0.rom_keymgr_functest.1963676497 | ||
| 90.42 | 0.01 | 93.23 | 0.00 | 83.36 | 0.00 | 90.61 | 0.01 | 94.80 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.4247401614 | ||
| 90.42 | 0.01 | 93.23 | 0.00 | 83.37 | 0.01 | 90.61 | 0.00 | 94.80 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/2.chip_plic_all_irqs_10.281705314 | ||
| 90.42 | 0.01 | 93.23 | 0.01 | 83.37 | 0.00 | 90.61 | 0.00 | 94.80 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/0.chip_sw_plic_sw_irq.1626436170 | ||
| 90.42 | 0.01 | 93.23 | 0.00 | 83.37 | 0.00 | 90.62 | 0.01 | 94.80 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.2453528670 | ||
| 90.43 | 0.01 | 93.23 | 0.00 | 83.37 | 0.00 | 90.63 | 0.01 | 94.80 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.396658785 | ||
| 90.43 | 0.01 | 93.23 | 0.00 | 83.37 | 0.00 | 90.63 | 0.01 | 94.80 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/0.chip_sw_hmac_enc.2322675946 | ||
| 90.43 | 0.01 | 93.23 | 0.00 | 83.37 | 0.00 | 90.64 | 0.01 | 94.80 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.3262029955 | ||
| 90.43 | 0.01 | 93.23 | 0.00 | 83.37 | 0.00 | 90.64 | 0.01 | 94.80 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1782843352 | ||
| 90.43 | 0.01 | 93.23 | 0.00 | 83.37 | 0.01 | 90.64 | 0.00 | 94.80 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2704594666 | ||
| 90.43 | 0.01 | 93.23 | 0.00 | 83.37 | 0.00 | 90.64 | 0.01 | 94.80 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/0.chip_sw_edn_auto_mode.494352724 | ||
| 90.43 | 0.01 | 93.23 | 0.00 | 83.37 | 0.00 | 90.64 | 0.01 | 94.80 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.4183709778 | ||
| 90.43 | 0.01 | 93.23 | 0.00 | 83.37 | 0.00 | 90.65 | 0.01 | 94.80 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.2554023648 | ||
| 90.43 | 0.01 | 93.23 | 0.00 | 83.37 | 0.00 | 90.65 | 0.01 | 94.80 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.1278384645 | ||
| 90.43 | 0.01 | 93.23 | 0.00 | 83.37 | 0.00 | 90.65 | 0.01 | 94.80 | 0.00 | 97.41 | 0.00 | 83.11 | 0.00 | /workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.1619064413 | ||
| Name |
|---|
| /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.1364175091 |
| /workspace/coverage/default/0.chip_sival_flash_info_access.697331726 |
| /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.4083154560 |
| /workspace/coverage/default/0.chip_sw_aes_enc.671320962 |
| /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.3326929185 |
| /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.1570352526 |
| /workspace/coverage/default/0.chip_sw_aes_entropy.3180362797 |
| /workspace/coverage/default/0.chip_sw_aes_idle.3565773780 |
| /workspace/coverage/default/0.chip_sw_aes_masking_off.1193500384 |
| /workspace/coverage/default/0.chip_sw_aes_smoketest.440316804 |
| /workspace/coverage/default/0.chip_sw_alert_handler_entropy.3477386090 |
| /workspace/coverage/default/0.chip_sw_alert_handler_escalation.283862078 |
| /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.4193004797 |
| /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.763381801 |
| /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.2269347751 |
| /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1200024619 |
| /workspace/coverage/default/0.chip_sw_all_escalation_resets.497171815 |
| /workspace/coverage/default/0.chip_sw_aon_timer_irq.1343410950 |
| /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.225682728 |
| /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.2513978419 |
| /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.3426239800 |
| /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.645992374 |
| /workspace/coverage/default/0.chip_sw_ast_clk_outputs.2266571086 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2107019671 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2523489450 |
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| /workspace/coverage/default/2.chip_sw_power_sleep_load.3615299011 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.1785987024 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.2078104701 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1775328341 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.901788421 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.3955906307 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3281528077 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.1786582196 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.433719047 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.348321309 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2177798992 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.724439693 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3846597031 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.2737255307 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2883744986 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.4005593886 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.1153959335 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1027891955 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.3055181853 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.598562973 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.1838233545 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.550743989 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.3932343972 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.2792437584 |
| /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.1092335095 |
| /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.3940224588 |
| /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.3551800129 |
| /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.3202037717 |
| /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.1266186383 |
| /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.2602805295 |
| /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.1418128538 |
| /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.2247124000 |
| /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.776817112 |
| /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.2070497064 |
| /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.1975968839 |
| /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.4288451985 |
| /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3979815680 |
| /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.2382825136 |
| /workspace/coverage/default/2.chip_sw_rv_timer_irq.2852393647 |
| /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.3379361962 |
| /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3909440280 |
| /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.2888455676 |
| /workspace/coverage/default/2.chip_sw_sleep_pin_retention.1711870501 |
| /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.356247010 |
| /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.183131029 |
| /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.4207211079 |
| /workspace/coverage/default/2.chip_sw_spi_device_pass_through.2546821896 |
| /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.3830680783 |
| /workspace/coverage/default/2.chip_sw_spi_device_tpm.1277808697 |
| /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.2774449585 |
| /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.861668793 |
| /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.2303008984 |
| /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3412889001 |
| /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1204460080 |
| /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.3309123342 |
| /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.3028286662 |
| /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.2733806731 |
| /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.3442393991 |
| /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.3914008089 |
| /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.314923647 |
| /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.2081592812 |
| /workspace/coverage/default/2.chip_sw_uart_smoketest.4234144391 |
| /workspace/coverage/default/2.chip_sw_uart_tx_rx.1227305883 |
| /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.2749798330 |
| /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.3612794308 |
| /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.3334599164 |
| /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.1408617021 |
| /workspace/coverage/default/2.chip_tap_straps_dev.3127780784 |
| /workspace/coverage/default/2.chip_tap_straps_prod.4084618176 |
| /workspace/coverage/default/2.chip_tap_straps_rma.1200450726 |
| /workspace/coverage/default/2.chip_tap_straps_testunlock0.2193675480 |
| /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.2654333410 |
| /workspace/coverage/default/2.rom_keymgr_functest.217828422 |
| /workspace/coverage/default/2.rom_volatile_raw_unlock.3629016258 |
| /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.368995503 |
| /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.517886842 |
| /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.806689640 |
| /workspace/coverage/default/26.chip_sw_all_escalation_resets.1893431706 |
| /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.49190059 |
| /workspace/coverage/default/27.chip_sw_all_escalation_resets.1471489220 |
| /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.3685607433 |
| /workspace/coverage/default/3.chip_sw_data_integrity_escalation.1971810213 |
| /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.2367265748 |
| /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.3980813543 |
| /workspace/coverage/default/3.chip_sw_uart_tx_rx.684539300 |
| /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.3605164623 |
| /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4094543527 |
| /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.4108184701 |
| /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.4105785852 |
| /workspace/coverage/default/3.chip_tap_straps_dev.889860171 |
| /workspace/coverage/default/3.chip_tap_straps_prod.3197374272 |
| /workspace/coverage/default/3.chip_tap_straps_testunlock0.4199591156 |
| /workspace/coverage/default/31.chip_sw_all_escalation_resets.1613701852 |
| /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.1035222709 |
| /workspace/coverage/default/34.chip_sw_all_escalation_resets.4257990362 |
| /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.372837259 |
| /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.1475129914 |
| /workspace/coverage/default/36.chip_sw_all_escalation_resets.2718914416 |
| /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1799705403 |
| /workspace/coverage/default/37.chip_sw_all_escalation_resets.3529726522 |
| /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.3695235304 |
| /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.4047578457 |
| /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.3411674154 |
| /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1508384791 |
| /workspace/coverage/default/4.chip_sw_data_integrity_escalation.3017626332 |
| /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.3686869330 |
| /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.4206698210 |
| /workspace/coverage/default/4.chip_sw_uart_tx_rx.164437163 |
| /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.78999189 |
| /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1499784705 |
| /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.1565241939 |
| /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.2337612428 |
| /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1912897120 |
| /workspace/coverage/default/4.chip_tap_straps_dev.2643217110 |
| /workspace/coverage/default/4.chip_tap_straps_prod.1168006977 |
| /workspace/coverage/default/4.chip_tap_straps_rma.271996380 |
| /workspace/coverage/default/4.chip_tap_straps_testunlock0.1297990910 |
| /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.3057313398 |
| /workspace/coverage/default/40.chip_sw_all_escalation_resets.3769002667 |
| /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.2137555859 |
| /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.87182962 |
| /workspace/coverage/default/42.chip_sw_all_escalation_resets.603595318 |
| /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.1865595725 |
| /workspace/coverage/default/43.chip_sw_all_escalation_resets.3646658718 |
| /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.60079499 |
| /workspace/coverage/default/45.chip_sw_all_escalation_resets.3196611910 |
| /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.672166663 |
| /workspace/coverage/default/47.chip_sw_all_escalation_resets.471877108 |
| /workspace/coverage/default/48.chip_sw_all_escalation_resets.728224177 |
| /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.71418645 |
| /workspace/coverage/default/49.chip_sw_all_escalation_resets.3236702013 |
| /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.4002596550 |
| /workspace/coverage/default/5.chip_sw_data_integrity_escalation.2886912217 |
| /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.1299814977 |
| /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1420887133 |
| /workspace/coverage/default/50.chip_sw_all_escalation_resets.3325654642 |
| /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.3019059842 |
| /workspace/coverage/default/51.chip_sw_all_escalation_resets.911727842 |
| /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.3626841429 |
| /workspace/coverage/default/52.chip_sw_all_escalation_resets.646811398 |
| /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2641590395 |
| /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.2288254526 |
| /workspace/coverage/default/54.chip_sw_all_escalation_resets.1233889833 |
| /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3355636805 |
| /workspace/coverage/default/55.chip_sw_all_escalation_resets.173630369 |
| /workspace/coverage/default/56.chip_sw_all_escalation_resets.1048350027 |
| /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.395107997 |
| /workspace/coverage/default/57.chip_sw_all_escalation_resets.1174094351 |
| /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1411772059 |
| /workspace/coverage/default/59.chip_sw_all_escalation_resets.2140988292 |
| /workspace/coverage/default/6.chip_sw_all_escalation_resets.4284484818 |
| /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.3300349732 |
| /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3692255717 |
| /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.2949054147 |
| /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3762349734 |
| /workspace/coverage/default/61.chip_sw_all_escalation_resets.3615486989 |
| /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3913422213 |
| /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1641464016 |
| /workspace/coverage/default/63.chip_sw_all_escalation_resets.466062692 |
| /workspace/coverage/default/64.chip_sw_all_escalation_resets.3217419802 |
| /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.1744206911 |
| /workspace/coverage/default/65.chip_sw_all_escalation_resets.3926007865 |
| /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1560942380 |
| /workspace/coverage/default/66.chip_sw_all_escalation_resets.1803580749 |
| /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.1011819327 |
| /workspace/coverage/default/67.chip_sw_all_escalation_resets.4132405760 |
| /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.97133947 |
| /workspace/coverage/default/68.chip_sw_all_escalation_resets.362648822 |
| /workspace/coverage/default/69.chip_sw_all_escalation_resets.2827394945 |
| /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2994803802 |
| /workspace/coverage/default/7.chip_sw_all_escalation_resets.2488054452 |
| /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.856826505 |
| /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.516343578 |
| /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3370670558 |
| /workspace/coverage/default/70.chip_sw_all_escalation_resets.1420201976 |
| /workspace/coverage/default/71.chip_sw_all_escalation_resets.3452269426 |
| /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3388892323 |
| /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.2990313019 |
| /workspace/coverage/default/73.chip_sw_all_escalation_resets.675948293 |
| /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2986925443 |
| /workspace/coverage/default/74.chip_sw_all_escalation_resets.3062506010 |
| /workspace/coverage/default/75.chip_sw_all_escalation_resets.602666149 |
| /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3039942473 |
| /workspace/coverage/default/76.chip_sw_all_escalation_resets.2918119999 |
| /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.4076074848 |
| /workspace/coverage/default/77.chip_sw_all_escalation_resets.1390837078 |
| /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3451888500 |
| /workspace/coverage/default/78.chip_sw_all_escalation_resets.221571748 |
| /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3903876531 |
| /workspace/coverage/default/79.chip_sw_all_escalation_resets.4010242755 |
| /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.22062450 |
| /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3654902079 |
| /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.1471189087 |
| /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.634976640 |
| /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.3855013875 |
| /workspace/coverage/default/82.chip_sw_all_escalation_resets.3201072926 |
| /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.2958175190 |
| /workspace/coverage/default/83.chip_sw_all_escalation_resets.1995472993 |
| /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.325408248 |
| /workspace/coverage/default/84.chip_sw_all_escalation_resets.2751939906 |
| /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.3129646662 |
| /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.4246399168 |
| /workspace/coverage/default/86.chip_sw_all_escalation_resets.1815976381 |
| /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.2927190125 |
| /workspace/coverage/default/88.chip_sw_all_escalation_resets.3828418253 |
| /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.2185880276 |
| /workspace/coverage/default/89.chip_sw_all_escalation_resets.4075913658 |
| /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1620452391 |
| /workspace/coverage/default/9.chip_sw_all_escalation_resets.1720577323 |
| /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.2533965367 |
| /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.2312234866 |
| /workspace/coverage/default/91.chip_sw_all_escalation_resets.2742028176 |
| /workspace/coverage/default/92.chip_sw_all_escalation_resets.3020870780 |
| /workspace/coverage/default/93.chip_sw_all_escalation_resets.2323652484 |
| /workspace/coverage/default/94.chip_sw_all_escalation_resets.3223158241 |
| /workspace/coverage/default/95.chip_sw_all_escalation_resets.3391340477 |
| /workspace/coverage/default/97.chip_sw_all_escalation_resets.3618590691 |
| /workspace/coverage/default/99.chip_sw_all_escalation_resets.3617541260 |
| /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.3206450054 |
| /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.3371056460 |
| /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.1631193557 |
| /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.3434890576 |
| /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.143687226 |
| /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1066657293 |
| /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2152366532 |
| /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.635074746 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/0.chip_sw_flash_init.3437778046 | Apr 21 02:56:51 PM PDT 24 | Apr 21 03:29:53 PM PDT 24 | 24228513300 ps | ||
| T2 | /workspace/coverage/default/2.chip_sw_flash_init.1557862228 | Apr 21 03:21:57 PM PDT 24 | Apr 21 04:02:08 PM PDT 24 | 22738829220 ps | ||
| T3 | /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.225682728 | Apr 21 03:00:57 PM PDT 24 | Apr 21 03:06:46 PM PDT 24 | 5805060932 ps | ||
| T65 | /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.72759768 | Apr 21 03:16:45 PM PDT 24 | Apr 21 03:20:06 PM PDT 24 | 2566307508 ps | ||
| T59 | /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.867756081 | Apr 21 03:33:03 PM PDT 24 | Apr 21 03:42:29 PM PDT 24 | 3737775420 ps | ||
| T82 | /workspace/coverage/default/1.chip_sw_alert_handler_entropy.3657883248 | Apr 21 03:12:25 PM PDT 24 | Apr 21 03:17:06 PM PDT 24 | 2508131912 ps | ||
| T29 | /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.863070548 | Apr 21 02:59:46 PM PDT 24 | Apr 21 03:09:23 PM PDT 24 | 4114599300 ps | ||
| T36 | /workspace/coverage/default/0.chip_sw_spi_device_tpm.3785132577 | Apr 21 02:57:18 PM PDT 24 | Apr 21 03:02:55 PM PDT 24 | 3723837813 ps | ||
| T46 | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2126209095 | Apr 21 02:59:29 PM PDT 24 | Apr 21 03:07:24 PM PDT 24 | 4348390344 ps | ||
| T64 | /workspace/coverage/default/98.chip_sw_all_escalation_resets.432711832 | Apr 21 03:39:34 PM PDT 24 | Apr 21 03:49:41 PM PDT 24 | 4502852218 ps | ||
| T4 | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.1862019988 | Apr 21 03:00:16 PM PDT 24 | Apr 21 03:11:08 PM PDT 24 | 8823309220 ps | ||
| T181 | /workspace/coverage/default/1.chip_sw_csrng_smoketest.2443434209 | Apr 21 03:17:44 PM PDT 24 | Apr 21 03:22:13 PM PDT 24 | 2743742272 ps | ||
| T283 | /workspace/coverage/default/2.chip_sw_rv_timer_irq.2852393647 | Apr 21 03:20:56 PM PDT 24 | Apr 21 03:25:31 PM PDT 24 | 2891798700 ps | ||
| T66 | /workspace/coverage/default/0.chip_sw_flash_crash_alert.867888842 | Apr 21 03:02:13 PM PDT 24 | Apr 21 03:12:13 PM PDT 24 | 5403915900 ps | ||
| T268 | /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1636624407 | Apr 21 03:34:31 PM PDT 24 | Apr 21 03:41:11 PM PDT 24 | 3879611708 ps | ||
| T341 | /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2899002049 | Apr 21 03:39:21 PM PDT 24 | Apr 21 03:48:52 PM PDT 24 | 4080022796 ps | ||
| T114 | /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.2888455676 | Apr 21 03:25:47 PM PDT 24 | Apr 21 03:30:27 PM PDT 24 | 3346800458 ps | ||
| T127 | /workspace/coverage/default/2.chip_sw_edn_boot_mode.1367263852 | Apr 21 03:22:55 PM PDT 24 | Apr 21 03:30:54 PM PDT 24 | 3013853728 ps | ||
| T11 | /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.3473511020 | Apr 21 03:33:53 PM PDT 24 | Apr 21 04:08:48 PM PDT 24 | 9104495304 ps | ||
| T117 | /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3838415245 | Apr 21 03:13:10 PM PDT 24 | Apr 21 03:21:03 PM PDT 24 | 19315726700 ps | ||
| T256 | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.786234445 | Apr 21 02:56:27 PM PDT 24 | Apr 21 03:06:49 PM PDT 24 | 4113101388 ps | ||
| T214 | /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.145866304 | Apr 21 03:33:47 PM PDT 24 | Apr 21 03:40:58 PM PDT 24 | 3522718880 ps | ||
| T328 | /workspace/coverage/default/0.chip_sw_uart_smoketest.2373917171 | Apr 21 03:07:10 PM PDT 24 | Apr 21 03:11:43 PM PDT 24 | 2788222688 ps | ||
| T118 | /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.1741140599 | Apr 21 03:23:02 PM PDT 24 | Apr 21 03:30:55 PM PDT 24 | 7193466940 ps | ||
| T161 | /workspace/coverage/default/2.chip_sw_kmac_app_rom.2382508142 | Apr 21 03:25:10 PM PDT 24 | Apr 21 03:29:34 PM PDT 24 | 2695101434 ps | ||
| T387 | /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.2815116604 | Apr 21 03:01:44 PM PDT 24 | Apr 21 03:17:39 PM PDT 24 | 4744737328 ps | ||
| T128 | /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.2168770290 | Apr 21 03:13:26 PM PDT 24 | Apr 21 03:49:30 PM PDT 24 | 9866647300 ps | ||
| T67 | /workspace/coverage/default/3.chip_sw_all_escalation_resets.3311521392 | Apr 21 03:31:18 PM PDT 24 | Apr 21 03:43:26 PM PDT 24 | 5573249144 ps | ||
| T333 | /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.1722850366 | Apr 21 03:26:24 PM PDT 24 | Apr 21 03:34:14 PM PDT 24 | 3777023014 ps | ||
| T528 | /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.92418797 | Apr 21 03:03:14 PM PDT 24 | Apr 21 03:12:42 PM PDT 24 | 4401932408 ps | ||
| T141 | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2976462248 | Apr 21 03:29:39 PM PDT 24 | Apr 21 03:38:56 PM PDT 24 | 3639038792 ps | ||
| T154 | /workspace/coverage/default/71.chip_sw_all_escalation_resets.3452269426 | Apr 21 03:37:49 PM PDT 24 | Apr 21 03:49:51 PM PDT 24 | 4287174320 ps | ||
| T210 | /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.3768908452 | Apr 21 03:00:50 PM PDT 24 | Apr 21 03:09:42 PM PDT 24 | 4424636664 ps | ||
| T254 | /workspace/coverage/default/8.chip_sw_all_escalation_resets.676510171 | Apr 21 03:32:28 PM PDT 24 | Apr 21 03:43:15 PM PDT 24 | 5074928424 ps | ||
| T119 | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.3397635454 | Apr 21 03:28:43 PM PDT 24 | Apr 21 04:01:44 PM PDT 24 | 10755874450 ps | ||
| T120 | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.953381953 | Apr 21 02:58:37 PM PDT 24 | Apr 21 03:09:01 PM PDT 24 | 4213493419 ps | ||
| T211 | /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.760988749 | Apr 21 03:16:37 PM PDT 24 | Apr 21 03:24:15 PM PDT 24 | 3672722340 ps | ||
| T170 | /workspace/coverage/default/1.chip_sw_hmac_smoketest.1642468193 | Apr 21 03:19:25 PM PDT 24 | Apr 21 03:24:15 PM PDT 24 | 2832201650 ps | ||
| T357 | /workspace/coverage/default/18.chip_sw_all_escalation_resets.3414065648 | Apr 21 03:34:47 PM PDT 24 | Apr 21 03:44:16 PM PDT 24 | 5463430524 ps | ||
| T175 | /workspace/coverage/default/2.chip_sw_kmac_idle.472839303 | Apr 21 03:24:24 PM PDT 24 | Apr 21 03:29:12 PM PDT 24 | 2764636040 ps | ||
| T44 | /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.2367265748 | Apr 21 03:31:19 PM PDT 24 | Apr 21 03:38:25 PM PDT 24 | 5484493371 ps | ||
| T14 | /workspace/coverage/default/0.chip_sw_usbdev_dpi.3949116521 | Apr 21 02:56:04 PM PDT 24 | Apr 21 03:54:07 PM PDT 24 | 11714068504 ps | ||
| T529 | /workspace/coverage/default/2.chip_sw_example_rom.3819293963 | Apr 21 03:16:38 PM PDT 24 | Apr 21 03:18:58 PM PDT 24 | 2493426000 ps | ||
| T212 | /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.4259144161 | Apr 21 02:59:29 PM PDT 24 | Apr 21 03:04:08 PM PDT 24 | 2651279070 ps | ||
| T236 | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.3021887683 | Apr 21 02:58:16 PM PDT 24 | Apr 21 03:17:47 PM PDT 24 | 6078198250 ps | ||
| T530 | /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.2640497319 | Apr 21 03:23:23 PM PDT 24 | Apr 21 03:27:56 PM PDT 24 | 2572779264 ps | ||
| T277 | /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.2288254526 | Apr 21 03:36:33 PM PDT 24 | Apr 21 03:42:57 PM PDT 24 | 4054960064 ps | ||
| T155 | /workspace/coverage/default/29.chip_sw_all_escalation_resets.2792511659 | Apr 21 03:36:47 PM PDT 24 | Apr 21 03:47:54 PM PDT 24 | 4891595816 ps | ||
| T313 | /workspace/coverage/default/30.chip_sw_all_escalation_resets.283586431 | Apr 21 03:35:18 PM PDT 24 | Apr 21 03:49:18 PM PDT 24 | 5423163670 ps | ||
| T45 | /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.1779780699 | Apr 21 03:20:03 PM PDT 24 | Apr 21 04:59:56 PM PDT 24 | 48995074282 ps | ||
| T71 | /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.4281660029 | Apr 21 03:01:11 PM PDT 24 | Apr 21 03:12:21 PM PDT 24 | 6130636357 ps | ||
| T274 | /workspace/coverage/default/0.chip_sw_data_integrity_escalation.2195338188 | Apr 21 02:57:23 PM PDT 24 | Apr 21 03:10:13 PM PDT 24 | 6103305530 ps | ||
| T147 | /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.3421462541 | Apr 21 03:34:33 PM PDT 24 | Apr 21 03:41:57 PM PDT 24 | 4233751330 ps | ||
| T308 | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.258663714 | Apr 21 02:58:10 PM PDT 24 | Apr 21 03:03:54 PM PDT 24 | 6078720980 ps | ||
| T309 | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1280636774 | Apr 21 03:13:19 PM PDT 24 | Apr 21 03:20:18 PM PDT 24 | 4251764564 ps | ||
| T310 | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.3418755657 | Apr 21 03:00:21 PM PDT 24 | Apr 21 03:04:54 PM PDT 24 | 3212932624 ps | ||
| T12 | /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.1471189087 | Apr 21 03:31:38 PM PDT 24 | Apr 21 03:43:44 PM PDT 24 | 4211676804 ps | ||
| T225 | /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.2354424665 | Apr 21 03:11:46 PM PDT 24 | Apr 21 03:14:06 PM PDT 24 | 2997198854 ps | ||
| T286 | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3068881811 | Apr 21 03:11:27 PM PDT 24 | Apr 21 03:29:49 PM PDT 24 | 8578201430 ps | ||
| T68 | /workspace/coverage/default/3.chip_tap_straps_testunlock0.4199591156 | Apr 21 03:28:55 PM PDT 24 | Apr 21 03:31:00 PM PDT 24 | 2448301447 ps | ||
| T129 | /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.800913509 | Apr 21 03:03:57 PM PDT 24 | Apr 21 04:19:15 PM PDT 24 | 18450901926 ps | ||
| T267 | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1981979208 | Apr 21 03:15:42 PM PDT 24 | Apr 21 03:26:00 PM PDT 24 | 5206241580 ps | ||
| T220 | /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.1300219644 | Apr 21 03:13:28 PM PDT 24 | Apr 21 05:05:48 PM PDT 24 | 49432686429 ps | ||
| T180 | /workspace/coverage/default/1.chip_sw_aes_entropy.1622970173 | Apr 21 03:13:10 PM PDT 24 | Apr 21 03:16:09 PM PDT 24 | 2936061530 ps | ||
| T383 | /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.3031459892 | Apr 21 03:34:15 PM PDT 24 | Apr 21 03:40:48 PM PDT 24 | 3369486102 ps | ||
| T531 | /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.1166481880 | Apr 21 03:18:36 PM PDT 24 | Apr 21 03:29:23 PM PDT 24 | 5927209920 ps | ||
| T352 | /workspace/coverage/default/97.chip_sw_all_escalation_resets.3618590691 | Apr 21 03:39:33 PM PDT 24 | Apr 21 03:47:58 PM PDT 24 | 5377286056 ps | ||
| T338 | /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2473512409 | Apr 21 03:41:39 PM PDT 24 | Apr 21 03:49:45 PM PDT 24 | 4300425528 ps | ||
| T139 | /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.416285548 | Apr 21 02:59:35 PM PDT 24 | Apr 21 03:08:20 PM PDT 24 | 4572455830 ps | ||
| T342 | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.3375090819 | Apr 21 03:13:24 PM PDT 24 | Apr 21 03:24:52 PM PDT 24 | 6817700596 ps | ||
| T142 | /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.2411674346 | Apr 21 02:57:02 PM PDT 24 | Apr 21 03:07:47 PM PDT 24 | 5038683690 ps | ||
| T73 | /workspace/coverage/default/2.chip_tap_straps_prod.4084618176 | Apr 21 03:26:12 PM PDT 24 | Apr 21 03:37:57 PM PDT 24 | 6072009775 ps | ||
| T124 | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2905777987 | Apr 21 03:18:27 PM PDT 24 | Apr 21 03:40:09 PM PDT 24 | 9365079020 ps | ||
| T378 | /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.183131029 | Apr 21 03:28:29 PM PDT 24 | Apr 21 03:40:15 PM PDT 24 | 6472794228 ps | ||
| T39 | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.4155222068 | Apr 21 03:08:51 PM PDT 24 | Apr 22 12:05:18 AM PDT 24 | 153116644826 ps | ||
| T173 | /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.2506681161 | Apr 21 03:00:44 PM PDT 24 | Apr 21 03:07:47 PM PDT 24 | 4539536786 ps | ||
| T377 | /workspace/coverage/default/90.chip_sw_all_escalation_resets.834892751 | Apr 21 03:41:58 PM PDT 24 | Apr 21 03:51:03 PM PDT 24 | 4690109968 ps | ||
| T381 | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.4005593886 | Apr 21 03:20:08 PM PDT 24 | Apr 21 03:24:27 PM PDT 24 | 2853113142 ps | ||
| T15 | /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.1986348886 | Apr 21 02:56:58 PM PDT 24 | Apr 21 03:04:01 PM PDT 24 | 3849302912 ps | ||
| T174 | /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.2236712852 | Apr 21 03:26:12 PM PDT 24 | Apr 21 03:35:38 PM PDT 24 | 4914966288 ps | ||
| T532 | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.3178819893 | Apr 21 02:57:52 PM PDT 24 | Apr 21 03:15:33 PM PDT 24 | 5451326102 ps | ||
| T239 | /workspace/coverage/default/80.chip_sw_all_escalation_resets.3663643046 | Apr 21 03:38:06 PM PDT 24 | Apr 21 03:53:16 PM PDT 24 | 5759341148 ps | ||
| T278 | /workspace/coverage/default/81.chip_sw_all_escalation_resets.3923822104 | Apr 21 03:38:20 PM PDT 24 | Apr 21 03:47:03 PM PDT 24 | 5530284060 ps | ||
| T177 | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.2289838027 | Apr 21 03:01:04 PM PDT 24 | Apr 21 03:10:02 PM PDT 24 | 4261872138 ps | ||
| T228 | /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.1075990272 | Apr 21 02:58:16 PM PDT 24 | Apr 21 03:00:26 PM PDT 24 | 3413521196 ps | ||
| T253 | /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.248978849 | Apr 21 03:08:48 PM PDT 24 | Apr 21 03:17:02 PM PDT 24 | 6236343764 ps | ||
| T221 | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3311583903 | Apr 21 03:19:38 PM PDT 24 | Apr 21 03:21:27 PM PDT 24 | 2548485235 ps | ||
| T255 | /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.1810320484 | Apr 21 03:18:48 PM PDT 24 | Apr 21 03:37:42 PM PDT 24 | 12617687958 ps | ||
| T178 | /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.2453528670 | Apr 21 03:24:19 PM PDT 24 | Apr 21 03:31:10 PM PDT 24 | 3694995032 ps | ||
| T187 | /workspace/coverage/default/95.chip_sw_all_escalation_resets.3391340477 | Apr 21 03:39:50 PM PDT 24 | Apr 21 03:52:55 PM PDT 24 | 4818321032 ps | ||
| T292 | /workspace/coverage/default/1.chip_sw_clkmgr_jitter.614533106 | Apr 21 03:14:35 PM PDT 24 | Apr 21 03:17:15 PM PDT 24 | 2582286227 ps | ||
| T293 | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.2147990493 | Apr 21 03:18:18 PM PDT 24 | Apr 21 03:29:49 PM PDT 24 | 3612237594 ps | ||
| T263 | /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.691299486 | Apr 21 03:00:08 PM PDT 24 | Apr 21 04:37:58 PM PDT 24 | 19842432878 ps | ||
| T294 | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1782843352 | Apr 21 02:57:52 PM PDT 24 | Apr 21 03:04:10 PM PDT 24 | 5108886196 ps | ||
| T137 | /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3909440280 | Apr 21 03:24:57 PM PDT 24 | Apr 21 03:33:28 PM PDT 24 | 4352608586 ps | ||
| T295 | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.2318992086 | Apr 21 03:24:41 PM PDT 24 | Apr 21 03:35:17 PM PDT 24 | 4102113122 ps | ||
| T125 | /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4094543527 | Apr 21 03:32:35 PM PDT 24 | Apr 21 03:53:13 PM PDT 24 | 8168706967 ps | ||
| T275 | /workspace/coverage/default/1.chip_sw_data_integrity_escalation.505652901 | Apr 21 03:07:05 PM PDT 24 | Apr 21 03:19:42 PM PDT 24 | 4482151970 ps | ||
| T13 | /workspace/coverage/default/2.chip_sw_gpio.564705632 | Apr 21 03:18:35 PM PDT 24 | Apr 21 03:27:22 PM PDT 24 | 4531819720 ps | ||
| T230 | /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.3057845225 | Apr 21 03:15:53 PM PDT 24 | Apr 21 03:19:27 PM PDT 24 | 2648905802 ps | ||
| T198 | /workspace/coverage/default/43.chip_sw_all_escalation_resets.3646658718 | Apr 21 03:35:15 PM PDT 24 | Apr 21 03:46:01 PM PDT 24 | 5822689380 ps | ||
| T203 | /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1200024619 | Apr 21 02:59:34 PM PDT 24 | Apr 21 06:35:01 PM PDT 24 | 255278790200 ps | ||
| T300 | /workspace/coverage/default/1.chip_sw_entropy_src_csrng.800751965 | Apr 21 03:16:36 PM PDT 24 | Apr 21 03:51:25 PM PDT 24 | 8545824688 ps | ||
| T162 | /workspace/coverage/default/0.chip_sw_kmac_app_rom.3165192312 | Apr 21 03:00:02 PM PDT 24 | Apr 21 03:04:36 PM PDT 24 | 3091699150 ps | ||
| T301 | /workspace/coverage/default/1.chip_sw_aes_enc.2783935720 | Apr 21 03:14:12 PM PDT 24 | Apr 21 03:19:50 PM PDT 24 | 2569006736 ps | ||
| T17 | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.2758230778 | Apr 21 03:00:49 PM PDT 24 | Apr 21 03:37:02 PM PDT 24 | 23569449080 ps | ||
| T176 | /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.2587975345 | Apr 21 03:26:24 PM PDT 24 | Apr 21 03:33:08 PM PDT 24 | 3632411750 ps | ||
| T316 | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.3459800003 | Apr 21 02:57:19 PM PDT 24 | Apr 21 03:06:01 PM PDT 24 | 3546662500 ps | ||
| T317 | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2240090946 | Apr 21 03:21:10 PM PDT 24 | Apr 21 03:32:28 PM PDT 24 | 4567270304 ps | ||
| T179 | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.1390697862 | Apr 21 02:59:17 PM PDT 24 | Apr 21 03:16:39 PM PDT 24 | 7865052058 ps | ||
| T237 | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.583330047 | Apr 21 03:19:04 PM PDT 24 | Apr 21 03:34:24 PM PDT 24 | 5657422400 ps | ||
| T186 | /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.1278384645 | Apr 21 03:02:17 PM PDT 24 | Apr 21 03:10:24 PM PDT 24 | 5994054224 ps | ||
| T287 | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.456857799 | Apr 21 02:59:03 PM PDT 24 | Apr 21 03:46:27 PM PDT 24 | 25667299379 ps | ||
| T271 | /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.130198154 | Apr 21 03:32:44 PM PDT 24 | Apr 21 04:03:48 PM PDT 24 | 8971213456 ps | ||
| T199 | /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2229395005 | Apr 21 03:39:15 PM PDT 24 | Apr 21 03:44:41 PM PDT 24 | 2975680200 ps | ||
| T533 | /workspace/coverage/default/2.chip_sw_aes_enc.606505930 | Apr 21 03:21:56 PM PDT 24 | Apr 21 03:25:23 PM PDT 24 | 2671111156 ps | ||
| T534 | /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.124906131 | Apr 21 03:28:48 PM PDT 24 | Apr 21 03:34:54 PM PDT 24 | 3023965488 ps | ||
| T185 | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.1080626761 | Apr 21 03:09:43 PM PDT 24 | Apr 21 03:27:44 PM PDT 24 | 6759414798 ps | ||
| T204 | /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1930537166 | Apr 21 03:32:16 PM PDT 24 | Apr 21 03:38:23 PM PDT 24 | 3258021078 ps | ||
| T296 | /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.2966623061 | Apr 21 03:17:04 PM PDT 24 | Apr 21 03:25:51 PM PDT 24 | 3440616944 ps | ||
| T69 | /workspace/coverage/default/0.chip_tap_straps_rma.2294587236 | Apr 21 03:00:42 PM PDT 24 | Apr 21 03:06:47 PM PDT 24 | 5382683813 ps | ||
| T50 | /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.1364175091 | Apr 21 03:01:54 PM PDT 24 | Apr 21 03:07:47 PM PDT 24 | 3742773444 ps | ||
| T379 | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.1048421557 | Apr 21 03:00:57 PM PDT 24 | Apr 21 03:12:52 PM PDT 24 | 7517641200 ps | ||
| T332 | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.3173546519 | Apr 21 03:10:50 PM PDT 24 | Apr 21 03:21:32 PM PDT 24 | 6404291288 ps | ||
| T369 | /workspace/coverage/default/82.chip_sw_all_escalation_resets.3201072926 | Apr 21 03:38:47 PM PDT 24 | Apr 21 03:47:51 PM PDT 24 | 5685345400 ps | ||
| T83 | /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.1865595725 | Apr 21 03:35:30 PM PDT 24 | Apr 21 03:43:40 PM PDT 24 | 3963531394 ps | ||
| T94 | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1912897120 | Apr 21 03:30:17 PM PDT 24 | Apr 21 03:40:47 PM PDT 24 | 4674113654 ps | ||
| T95 | /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1411772059 | Apr 21 03:37:08 PM PDT 24 | Apr 21 03:42:57 PM PDT 24 | 3982960040 ps | ||
| T96 | /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.4199399291 | Apr 21 02:57:15 PM PDT 24 | Apr 21 03:01:58 PM PDT 24 | 3278088910 ps | ||
| T16 | /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.3932343972 | Apr 21 03:29:41 PM PDT 24 | Apr 21 03:36:24 PM PDT 24 | 5609554520 ps | ||
| T97 | /workspace/coverage/default/1.chip_sw_kmac_smoketest.3373436681 | Apr 21 03:17:49 PM PDT 24 | Apr 21 03:22:41 PM PDT 24 | 3106931960 ps | ||
| T98 | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.1565241939 | Apr 21 03:31:33 PM PDT 24 | Apr 21 03:40:59 PM PDT 24 | 4277329216 ps | ||
| T99 | /workspace/coverage/default/1.chip_sw_uart_tx_rx.762123659 | Apr 21 03:09:35 PM PDT 24 | Apr 21 03:21:56 PM PDT 24 | 4480882360 ps | ||
| T100 | /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.3551800129 | Apr 21 03:20:30 PM PDT 24 | Apr 21 03:30:43 PM PDT 24 | 5791553764 ps | ||
| T101 | /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.2648420701 | Apr 21 03:37:14 PM PDT 24 | Apr 21 03:42:36 PM PDT 24 | 4027585930 ps | ||
| T227 | /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.3515540611 | Apr 21 03:09:04 PM PDT 24 | Apr 21 03:24:00 PM PDT 24 | 10427379344 ps | ||
| T121 | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3523193604 | Apr 21 03:02:49 PM PDT 24 | Apr 21 03:12:45 PM PDT 24 | 5225724496 ps | ||
| T370 | /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.3593921716 | Apr 21 03:33:45 PM PDT 24 | Apr 21 03:39:47 PM PDT 24 | 3099461004 ps | ||
| T182 | /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.875781843 | Apr 21 03:11:53 PM PDT 24 | Apr 21 03:20:04 PM PDT 24 | 5205297672 ps | ||
| T144 | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1894436144 | Apr 21 03:15:32 PM PDT 24 | Apr 21 03:25:02 PM PDT 24 | 4579974144 ps | ||
| T358 | /workspace/coverage/default/12.chip_sw_all_escalation_resets.3808202516 | Apr 21 03:32:54 PM PDT 24 | Apr 21 03:42:52 PM PDT 24 | 5144897980 ps | ||
| T380 | /workspace/coverage/default/1.chip_sw_all_escalation_resets.1417423221 | Apr 21 03:06:09 PM PDT 24 | Apr 21 03:20:21 PM PDT 24 | 6189768530 ps | ||
| T276 | /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.2970662350 | Apr 21 03:11:26 PM PDT 24 | Apr 21 03:22:58 PM PDT 24 | 5383829448 ps | ||
| T297 | /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.1371372006 | Apr 21 03:09:58 PM PDT 24 | Apr 21 03:11:49 PM PDT 24 | 1824533067 ps | ||
| T74 | /workspace/coverage/default/4.chip_tap_straps_dev.2643217110 | Apr 21 03:30:14 PM PDT 24 | Apr 21 03:39:58 PM PDT 24 | 4805365099 ps | ||
| T382 | /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.3202037717 | Apr 21 03:17:55 PM PDT 24 | Apr 21 03:27:32 PM PDT 24 | 5909857742 ps | ||
| T487 | /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1620452391 | Apr 21 03:33:44 PM PDT 24 | Apr 21 03:38:55 PM PDT 24 | 3260216728 ps | ||
| T122 | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.4037797186 | Apr 21 03:14:55 PM PDT 24 | Apr 21 03:24:10 PM PDT 24 | 3756329813 ps | ||
| T288 | /workspace/coverage/default/1.chip_sw_aon_timer_irq.2817748171 | Apr 21 03:11:02 PM PDT 24 | Apr 21 03:18:24 PM PDT 24 | 4561752536 ps | ||
| T344 | /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.879516653 | Apr 21 03:35:05 PM PDT 24 | Apr 21 03:42:02 PM PDT 24 | 3504580250 ps | ||
| T18 | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.3028286662 | Apr 21 03:20:50 PM PDT 24 | Apr 21 04:27:03 PM PDT 24 | 20591178897 ps | ||
| T169 | /workspace/coverage/default/0.chip_plic_all_irqs_20.553404899 | Apr 21 02:59:39 PM PDT 24 | Apr 21 03:10:11 PM PDT 24 | 4170298744 ps | ||
| T410 | /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.1744206911 | Apr 21 03:37:55 PM PDT 24 | Apr 21 03:43:34 PM PDT 24 | 3659648066 ps | ||
| T70 | /workspace/coverage/default/1.chip_tap_straps_rma.1554053466 | Apr 21 03:15:37 PM PDT 24 | Apr 21 03:24:51 PM PDT 24 | 5530271585 ps | ||
| T20 | /workspace/coverage/default/0.chip_sw_usbdev_setuprx.779853526 | Apr 21 02:56:34 PM PDT 24 | Apr 21 03:04:55 PM PDT 24 | 4165773000 ps | ||
| T388 | /workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.1619064413 | Apr 21 03:27:12 PM PDT 24 | Apr 21 03:30:31 PM PDT 24 | 1964628240 ps | ||
| T535 | /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.3300349732 | Apr 21 03:31:49 PM PDT 24 | Apr 21 03:38:18 PM PDT 24 | 5330457189 ps | ||
| T298 | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.710237262 | Apr 21 03:20:06 PM PDT 24 | Apr 21 03:21:59 PM PDT 24 | 2688352622 ps | ||
| T350 | /workspace/coverage/default/0.chip_sw_otbn_randomness.2843557312 | Apr 21 02:59:57 PM PDT 24 | Apr 21 03:13:59 PM PDT 24 | 5909685880 ps | ||
| T194 | /workspace/coverage/default/54.chip_sw_all_escalation_resets.1233889833 | Apr 21 03:38:21 PM PDT 24 | Apr 21 03:50:03 PM PDT 24 | 5155405168 ps | ||
| T536 | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.1347255195 | Apr 21 03:12:25 PM PDT 24 | Apr 21 03:25:23 PM PDT 24 | 7120947140 ps | ||
| T339 | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.918146300 | Apr 21 02:57:02 PM PDT 24 | Apr 21 03:06:22 PM PDT 24 | 4483271118 ps | ||
| T244 | /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2945469137 | Apr 21 03:35:01 PM PDT 24 | Apr 21 03:42:37 PM PDT 24 | 3561105530 ps | ||
| T418 | /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.757879070 | Apr 21 03:01:58 PM PDT 24 | Apr 21 03:07:11 PM PDT 24 | 2598600396 ps | ||
| T353 | /workspace/coverage/default/63.chip_sw_all_escalation_resets.466062692 | Apr 21 03:36:16 PM PDT 24 | Apr 21 03:46:47 PM PDT 24 | 4807476380 ps | ||
| T145 | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1482078420 | Apr 21 03:14:41 PM PDT 24 | Apr 21 03:26:06 PM PDT 24 | 4552406000 ps | ||
| T537 | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.2782556335 | Apr 21 03:00:02 PM PDT 24 | Apr 21 03:06:51 PM PDT 24 | 4031409652 ps | ||
| T474 | /workspace/coverage/default/55.chip_sw_all_escalation_resets.173630369 | Apr 21 03:38:16 PM PDT 24 | Apr 21 03:53:42 PM PDT 24 | 6113680504 ps | ||
| T205 | /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.2990313019 | Apr 21 03:38:48 PM PDT 24 | Apr 21 03:45:01 PM PDT 24 | 3393237200 ps | ||
| T326 | /workspace/coverage/default/37.chip_sw_all_escalation_resets.3529726522 | Apr 21 03:35:14 PM PDT 24 | Apr 21 03:46:25 PM PDT 24 | 4793083420 ps | ||
| T60 | /workspace/coverage/default/0.chip_sw_alert_test.1687653760 | Apr 21 02:59:00 PM PDT 24 | Apr 21 03:04:18 PM PDT 24 | 3393946694 ps | ||
| T538 | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.4014614214 | Apr 21 02:57:02 PM PDT 24 | Apr 21 03:15:05 PM PDT 24 | 8362177472 ps | ||
| T132 | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.3055181853 | Apr 21 03:26:30 PM PDT 24 | Apr 21 03:34:22 PM PDT 24 | 4679906748 ps | ||
| T539 | /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.2719482552 | Apr 21 03:21:29 PM PDT 24 | Apr 21 03:25:45 PM PDT 24 | 2965497234 ps | ||
| T273 | /workspace/coverage/default/4.chip_tap_straps_prod.1168006977 | Apr 21 03:30:06 PM PDT 24 | Apr 21 03:32:33 PM PDT 24 | 2763170770 ps | ||
| T131 | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.885542521 | Apr 21 03:16:25 PM PDT 24 | Apr 21 04:29:15 PM PDT 24 | 25317107116 ps | ||
| T540 | /workspace/coverage/default/1.chip_tap_straps_dev.3333184407 | Apr 21 03:15:18 PM PDT 24 | Apr 21 03:32:31 PM PDT 24 | 9147201033 ps | ||
| T541 | /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.1838233545 | Apr 21 03:19:50 PM PDT 24 | Apr 21 03:32:54 PM PDT 24 | 5720914356 ps | ||
| T542 | /workspace/coverage/default/0.chip_sw_usbdev_vbus.1391847585 | Apr 21 02:55:42 PM PDT 24 | Apr 21 02:59:16 PM PDT 24 | 3286058732 ps | ||
| T543 | /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.1560356950 | Apr 21 03:15:55 PM PDT 24 | Apr 21 03:22:50 PM PDT 24 | 3678729848 ps | ||
| T226 | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.3526854603 | Apr 21 02:58:40 PM PDT 24 | Apr 21 04:50:40 PM PDT 24 | 50477608244 ps | ||
| T544 | /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.2653520950 | Apr 21 03:31:26 PM PDT 24 | Apr 21 03:36:57 PM PDT 24 | 3166672050 ps | ||
| T72 | /workspace/coverage/default/3.chip_tap_straps_rma.2709772342 | Apr 21 03:29:17 PM PDT 24 | Apr 21 03:42:30 PM PDT 24 | 6302957493 ps | ||
| T545 | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3977446502 | Apr 21 02:58:57 PM PDT 24 | Apr 21 03:31:19 PM PDT 24 | 17057819967 ps | ||
| T546 | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.4188944345 | Apr 21 03:14:18 PM PDT 24 | Apr 21 03:26:59 PM PDT 24 | 4448708696 ps | ||
| T163 | /workspace/coverage/default/93.chip_sw_all_escalation_resets.2323652484 | Apr 21 03:39:34 PM PDT 24 | Apr 21 03:52:35 PM PDT 24 | 4633589096 ps | ||
| T272 | /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1420887133 | Apr 21 03:30:14 PM PDT 24 | Apr 21 03:58:58 PM PDT 24 | 8243928820 ps | ||
| T289 | /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.3716239468 | Apr 21 03:00:14 PM PDT 24 | Apr 21 03:11:24 PM PDT 24 | 5957852056 ps | ||
| T126 | /workspace/coverage/default/0.chip_sw_power_sleep_load.1964956009 | Apr 21 03:02:15 PM PDT 24 | Apr 21 03:10:52 PM PDT 24 | 10552077736 ps | ||
| T257 | /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.3899125002 | Apr 21 03:09:23 PM PDT 24 | Apr 21 05:18:37 PM PDT 24 | 47593525021 ps | ||
| T508 | /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1799705403 | Apr 21 03:36:21 PM PDT 24 | Apr 21 03:44:39 PM PDT 24 | 3888823586 ps | ||
| T547 | /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.2527585564 | Apr 21 03:06:06 PM PDT 24 | Apr 21 03:09:08 PM PDT 24 | 2781919710 ps | ||
| T548 | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.99395153 | Apr 21 02:57:31 PM PDT 24 | Apr 21 03:09:16 PM PDT 24 | 10482920628 ps | ||
| T86 | /workspace/coverage/default/26.chip_sw_all_escalation_resets.1893431706 | Apr 21 03:35:03 PM PDT 24 | Apr 21 03:46:15 PM PDT 24 | 4738140876 ps | ||
| T249 | /workspace/coverage/default/85.chip_sw_all_escalation_resets.327008022 | Apr 21 03:39:09 PM PDT 24 | Apr 21 03:49:05 PM PDT 24 | 5120190064 ps | ||
| T207 | /workspace/coverage/default/0.chip_sw_otbn_smoketest.1854841763 | Apr 21 03:05:22 PM PDT 24 | Apr 21 03:25:24 PM PDT 24 | 6680672904 ps | ||
| T158 | /workspace/coverage/default/2.chip_tap_straps_testunlock0.2193675480 | Apr 21 03:27:16 PM PDT 24 | Apr 21 03:31:23 PM PDT 24 | 3203480166 ps | ||
| T549 | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.612303518 | Apr 21 03:19:27 PM PDT 24 | Apr 21 03:43:35 PM PDT 24 | 8362925944 ps | ||
| T550 | /workspace/coverage/default/2.chip_sw_example_manufacturer.4140223822 | Apr 21 03:17:48 PM PDT 24 | Apr 21 03:22:21 PM PDT 24 | 2913166400 ps | ||
| T47 | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1134215873 | Apr 21 03:02:45 PM PDT 24 | Apr 21 03:27:28 PM PDT 24 | 23327836540 ps | ||
| T105 | /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.416180184 | Apr 21 03:11:48 PM PDT 24 | Apr 21 03:15:53 PM PDT 24 | 2802094744 ps | ||
| T106 | /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.687998284 | Apr 21 03:08:01 PM PDT 24 | Apr 21 03:27:13 PM PDT 24 | 7389631576 ps | ||
| T107 | /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.3262029955 | Apr 21 02:58:56 PM PDT 24 | Apr 21 03:07:47 PM PDT 24 | 5263293080 ps | ||
| T108 | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1499784705 | Apr 21 03:30:46 PM PDT 24 | Apr 21 04:04:32 PM PDT 24 | 13800408083 ps | ||
| T21 | /workspace/coverage/default/0.chip_sw_usbdev_config_host.887685444 | Apr 21 02:57:42 PM PDT 24 | Apr 21 03:37:05 PM PDT 24 | 8684484600 ps | ||
| T109 | /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.1181288914 | Apr 21 03:25:32 PM PDT 24 | Apr 21 03:49:31 PM PDT 24 | 11325807010 ps | ||
| T110 | /workspace/coverage/default/92.chip_sw_all_escalation_resets.3020870780 | Apr 21 03:42:08 PM PDT 24 | Apr 21 03:51:23 PM PDT 24 | 4373457596 ps | ||
| T111 | /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.4009058567 | Apr 21 03:19:29 PM PDT 24 | Apr 21 03:40:46 PM PDT 24 | 6520202478 ps | ||
| T112 | /workspace/coverage/default/99.chip_sw_all_escalation_resets.3617541260 | Apr 21 03:40:27 PM PDT 24 | Apr 21 03:50:55 PM PDT 24 | 4497334200 ps | ||
| T208 | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.492075349 | Apr 21 03:12:50 PM PDT 24 | Apr 21 04:23:46 PM PDT 24 | 16713155220 ps | ||
| T551 | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.3958378966 | Apr 21 03:14:43 PM PDT 24 | Apr 21 03:21:06 PM PDT 24 | 2934139398 ps | ||
| T356 | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.44072758 | Apr 21 03:09:58 PM PDT 24 | Apr 21 03:23:55 PM PDT 24 | 4332755313 ps | ||
| T552 | /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.2284884476 | Apr 21 03:00:53 PM PDT 24 | Apr 21 03:08:10 PM PDT 24 | 3956623286 ps | ||
| T77 | /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.1910359464 | Apr 21 03:19:00 PM PDT 24 | Apr 21 06:36:03 PM PDT 24 | 58443048174 ps | ||
| T440 | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.2864312274 | Apr 21 02:59:43 PM PDT 24 | Apr 21 04:16:52 PM PDT 24 | 18983174164 ps | ||
| T143 | /workspace/coverage/default/0.chip_sw_power_idle_load.100142094 | Apr 21 03:03:09 PM PDT 24 | Apr 21 03:17:06 PM PDT 24 | 4269551512 ps | ||
| T553 | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.2749798330 | Apr 21 03:21:08 PM PDT 24 | Apr 21 03:28:00 PM PDT 24 | 3866429627 ps | ||
| T554 | /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.3752135418 | Apr 21 03:21:00 PM PDT 24 | Apr 21 03:24:28 PM PDT 24 | 3386621880 ps | ||
| T48 | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.230488511 | Apr 21 03:15:48 PM PDT 24 | Apr 21 03:46:10 PM PDT 24 | 21003113170 ps | ||
| T555 | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2141011242 | Apr 21 03:01:38 PM PDT 24 | Apr 21 03:12:02 PM PDT 24 | 5270559216 ps | ||
| T556 | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.214512077 | Apr 21 03:03:41 PM PDT 24 | Apr 21 03:09:14 PM PDT 24 | 3440157452 ps | ||
| T470 | /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.105503810 | Apr 21 03:34:19 PM PDT 24 | Apr 21 03:40:40 PM PDT 24 | 3842593618 ps | ||
| T115 | /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.700740950 | Apr 21 03:00:06 PM PDT 24 | Apr 21 03:03:47 PM PDT 24 | 2226292293 ps | ||
| T557 | /workspace/coverage/default/4.chip_tap_straps_rma.271996380 | Apr 21 03:30:15 PM PDT 24 | Apr 21 03:38:21 PM PDT 24 | 4866199578 ps | ||
| T558 | /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.3678071826 | Apr 21 03:26:18 PM PDT 24 | Apr 21 03:35:29 PM PDT 24 | 5501590840 ps | ||
| T42 | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.132433472 | Apr 21 03:08:24 PM PDT 24 | Apr 21 08:09:08 PM PDT 24 | 77522300280 ps | ||
| T238 | /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.429966781 | Apr 21 03:07:57 PM PDT 24 | Apr 21 03:15:54 PM PDT 24 | 4025099784 ps | ||
| T559 | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.3612794308 | Apr 21 03:22:02 PM PDT 24 | Apr 21 03:35:28 PM PDT 24 | 4049397310 ps | ||
| T164 | /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.732571161 | Apr 21 03:13:17 PM PDT 24 | Apr 21 03:22:09 PM PDT 24 | 9284055136 ps | ||
| T234 | /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.96521967 | Apr 21 02:56:47 PM PDT 24 | Apr 21 04:22:39 PM PDT 24 | 43862170675 ps | ||
| T171 | /workspace/coverage/default/0.chip_sw_hmac_enc_idle.1916894695 | Apr 21 03:00:07 PM PDT 24 | Apr 21 03:05:14 PM PDT 24 | 2752660000 ps | ||
| T560 | /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.3337125552 | Apr 21 03:17:01 PM PDT 24 | Apr 21 03:20:16 PM PDT 24 | 3031679252 ps | ||
| T172 | /workspace/coverage/default/0.chip_sw_hmac_enc.2322675946 | Apr 21 03:00:42 PM PDT 24 | Apr 21 03:05:41 PM PDT 24 | 3375676520 ps | ||
| T561 | /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.1470433893 | Apr 21 03:24:01 PM PDT 24 | Apr 21 03:33:57 PM PDT 24 | 4781324450 ps | ||
| T87 | /workspace/coverage/default/20.chip_sw_all_escalation_resets.1798062235 | Apr 21 03:37:03 PM PDT 24 | Apr 21 03:48:53 PM PDT 24 | 5283871400 ps | ||
| T562 | /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.856826505 | Apr 21 03:31:26 PM PDT 24 | Apr 21 03:37:54 PM PDT 24 | 6410360730 ps | ||
| T78 | /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.149266890 | Apr 21 03:02:23 PM PDT 24 | Apr 21 03:12:35 PM PDT 24 | 4429810580 ps | ||
| T563 | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.3334599164 | Apr 21 03:18:34 PM PDT 24 | Apr 21 03:29:31 PM PDT 24 | 3708214128 ps | ||
| T240 | /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.22062450 | Apr 21 03:32:27 PM PDT 24 | Apr 21 03:40:04 PM PDT 24 | 3838573456 ps | ||
| T290 | /workspace/coverage/default/6.chip_sw_all_escalation_resets.4284484818 | Apr 21 03:31:13 PM PDT 24 | Apr 21 03:45:20 PM PDT 24 | 6135540648 ps | ||
| T269 | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.1211089190 | Apr 21 03:11:52 PM PDT 24 | Apr 21 03:24:29 PM PDT 24 | 4314903317 ps | ||
| T79 | /workspace/coverage/default/0.chip_jtag_mem_access.3234567215 | Apr 21 02:53:42 PM PDT 24 | Apr 21 03:18:32 PM PDT 24 | 13835840272 ps | ||
| T340 | /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.44225826 | Apr 21 03:34:03 PM PDT 24 | Apr 21 03:41:35 PM PDT 24 | 3534665506 ps | ||
| T159 | /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1872613506 | Apr 21 03:15:20 PM PDT 24 | Apr 21 03:25:35 PM PDT 24 | 4413712860 ps | ||
| T270 | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.2269775732 | Apr 21 02:59:38 PM PDT 24 | Apr 21 03:10:43 PM PDT 24 | 4041911316 ps | ||
| T351 | /workspace/coverage/default/38.chip_sw_all_escalation_resets.3236437159 | Apr 21 03:35:55 PM PDT 24 | Apr 21 03:46:10 PM PDT 24 | 5086971608 ps | ||
| T564 | /workspace/coverage/default/0.chip_sw_flash_ctrl_access.2994915239 | Apr 21 02:59:32 PM PDT 24 | Apr 21 03:15:52 PM PDT 24 | 5239661408 ps | ||
| T80 | /workspace/coverage/default/1.chip_jtag_csr_rw.1285615732 | Apr 21 03:07:40 PM PDT 24 | Apr 21 03:44:04 PM PDT 24 | 20333955560 ps | ||
| T479 | /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.1677953136 | Apr 21 03:34:39 PM PDT 24 | Apr 21 03:40:21 PM PDT 24 | 3922239236 ps | ||
| T565 | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.1408617021 | Apr 21 03:21:52 PM PDT 24 | Apr 21 03:35:41 PM PDT 24 | 3635384618 ps |
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