Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_rnd_data
Instance :
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 |
100.00 |
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Instance's subtree :
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 |
100.00 |
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Parent :
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.59 |
99.44 |
69.77 |
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97.14 |
100.00 |
u_reg_cfg |
Subtrees :
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_fpga_info
Instance :
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
33.33 |
33.33 |
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Instance's subtree :
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
33.33 |
33.33 |
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Parent :
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.59 |
99.44 |
69.77 |
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|
97.14 |
100.00 |
u_reg_cfg |
Subtrees :
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_alert_test_fatal_sw_err
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 26 | 0 | 0 | |
CONT_ASSIGN | 27 | 0 | 0 | |
CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
26 |
|
unreachable |
27 |
|
unreachable |
28 |
1 |
1 |
29 |
1 |
1 |
30 |
|
unreachable |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_alert_test_recov_sw_err
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 26 | 0 | 0 | |
CONT_ASSIGN | 27 | 0 | 0 | |
CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
26 |
|
unreachable |
27 |
|
unreachable |
28 |
1 |
1 |
29 |
1 |
1 |
30 |
|
unreachable |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_alert_test_fatal_hw_err
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 26 | 0 | 0 | |
CONT_ASSIGN | 27 | 0 | 0 | |
CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
26 |
|
unreachable |
27 |
|
unreachable |
28 |
1 |
1 |
29 |
1 |
1 |
30 |
|
unreachable |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_alert_test_recov_hw_err
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 26 | 0 | 0 | |
CONT_ASSIGN | 27 | 0 | 0 | |
CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
26 |
|
unreachable |
27 |
|
unreachable |
28 |
1 |
1 |
29 |
1 |
1 |
30 |
|
unreachable |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_rnd_data
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
CONT_ASSIGN | 28 | 0 | 0 | |
CONT_ASSIGN | 29 | 0 | 0 | |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
26 |
1 |
1 |
27 |
1 |
1 |
28 |
|
unreachable |
29 |
|
unreachable |
30 |
1 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_rnd_status_rnd_data_valid
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
CONT_ASSIGN | 28 | 0 | 0 | |
CONT_ASSIGN | 29 | 0 | 0 | |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
26 |
1 |
1 |
27 |
1 |
1 |
28 |
|
unreachable |
29 |
|
unreachable |
30 |
1 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_rnd_status_rnd_data_fips
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
CONT_ASSIGN | 28 | 0 | 0 | |
CONT_ASSIGN | 29 | 0 | 0 | |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
26 |
1 |
1 |
27 |
1 |
1 |
28 |
|
unreachable |
29 |
|
unreachable |
30 |
1 |
1 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_fpga_info
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 1 | 33.33 |
CONT_ASSIGN | 26 | 1 | 0 | 0.00 |
CONT_ASSIGN | 27 | 1 | 0 | 0.00 |
CONT_ASSIGN | 28 | 0 | 0 | |
CONT_ASSIGN | 29 | 0 | 0 | |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
26 |
0 |
1 |
27 |
0 |
1 |
28 |
|
unreachable |
29 |
|
unreachable |
30 |
1 |
1 |
0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |