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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.47 93.52 83.37 90.65 94.80 97.38 83.11


Total test records in report: 905
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T516 /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3355636805 Apr 21 03:38:57 PM PDT 24 Apr 21 03:45:37 PM PDT 24 3662070700 ps
T489 /workspace/coverage/default/46.chip_sw_all_escalation_resets.4030475870 Apr 21 03:36:08 PM PDT 24 Apr 21 03:49:41 PM PDT 24 5659990416 ps
T566 /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3692255717 Apr 21 03:30:46 PM PDT 24 Apr 21 03:56:03 PM PDT 24 7967573560 ps
T407 /workspace/coverage/default/2.chip_sw_edn_auto_mode.2644121228 Apr 21 03:23:07 PM PDT 24 Apr 21 03:48:46 PM PDT 24 5782616760 ps
T75 /workspace/coverage/default/0.chip_sw_usbdev_pincfg.470102636 Apr 21 02:56:55 PM PDT 24 Apr 21 05:24:59 PM PDT 24 31307392400 ps
T189 /workspace/coverage/default/0.chip_sw_edn_boot_mode.3953226413 Apr 21 02:59:40 PM PDT 24 Apr 21 03:09:44 PM PDT 24 3041439852 ps
T567 /workspace/coverage/default/0.chip_sw_aes_enc.671320962 Apr 21 03:01:11 PM PDT 24 Apr 21 03:07:09 PM PDT 24 2947383424 ps
T22 /workspace/coverage/default/0.chip_sw_gpio_smoketest.4192379251 Apr 21 03:05:54 PM PDT 24 Apr 21 03:10:14 PM PDT 24 3431182738 ps
T490 /workspace/coverage/default/5.chip_sw_all_escalation_resets.1504659938 Apr 21 03:32:37 PM PDT 24 Apr 21 03:43:24 PM PDT 24 4903374616 ps
T568 /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.3661206864 Apr 21 03:07:10 PM PDT 24 Apr 21 03:11:46 PM PDT 24 2963373640 ps
T455 /workspace/coverage/default/50.chip_sw_all_escalation_resets.3325654642 Apr 21 03:35:21 PM PDT 24 Apr 21 03:45:51 PM PDT 24 4517121960 ps
T88 /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.2958175190 Apr 21 03:40:52 PM PDT 24 Apr 21 03:47:57 PM PDT 24 3803289548 ps
T473 /workspace/coverage/default/72.chip_sw_all_escalation_resets.3110558221 Apr 21 03:37:26 PM PDT 24 Apr 21 03:48:37 PM PDT 24 4826938554 ps
T331 /workspace/coverage/default/0.chip_sw_pattgen_ios.2419266181 Apr 21 02:56:53 PM PDT 24 Apr 21 03:01:18 PM PDT 24 3339734250 ps
T200 /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.3171174743 Apr 21 03:22:24 PM PDT 24 Apr 21 03:27:47 PM PDT 24 3349629948 ps
T462 /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.4002596550 Apr 21 03:32:33 PM PDT 24 Apr 21 03:41:40 PM PDT 24 3857708736 ps
T417 /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.1975968839 Apr 21 03:21:53 PM PDT 24 Apr 21 03:36:44 PM PDT 24 6051148684 ps
T569 /workspace/coverage/default/0.chip_tap_straps_dev.3585076138 Apr 21 03:00:31 PM PDT 24 Apr 21 03:22:25 PM PDT 24 12455376550 ps
T284 /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.3379361962 Apr 21 03:29:52 PM PDT 24 Apr 21 03:36:00 PM PDT 24 3313634444 ps
T570 /workspace/coverage/default/2.chip_sw_uart_smoketest.4234144391 Apr 21 03:31:17 PM PDT 24 Apr 21 03:35:32 PM PDT 24 2714141850 ps
T439 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.3589977320 Apr 21 02:59:26 PM PDT 24 Apr 21 03:04:07 PM PDT 24 3471139732 ps
T23 /workspace/coverage/default/2.chip_sw_gpio_smoketest.2173215144 Apr 21 03:29:43 PM PDT 24 Apr 21 03:33:02 PM PDT 24 2347078841 ps
T571 /workspace/coverage/default/1.chip_sw_aes_idle.1766098028 Apr 21 03:13:59 PM PDT 24 Apr 21 03:18:23 PM PDT 24 2591809784 ps
T572 /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.3366282852 Apr 21 03:05:56 PM PDT 24 Apr 21 03:08:56 PM PDT 24 2472174536 ps
T258 /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.559831645 Apr 21 03:02:11 PM PDT 24 Apr 21 03:40:47 PM PDT 24 21948952167 ps
T231 /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.3632164162 Apr 21 03:15:08 PM PDT 24 Apr 21 03:18:45 PM PDT 24 3050240028 ps
T396 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.2992478436 Apr 21 03:11:47 PM PDT 24 Apr 21 03:22:02 PM PDT 24 8900582060 ps
T397 /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.634976640 Apr 21 03:39:56 PM PDT 24 Apr 21 03:48:40 PM PDT 24 4165218066 ps
T398 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.724439693 Apr 21 03:20:18 PM PDT 24 Apr 21 03:35:18 PM PDT 24 6702921366 ps
T399 /workspace/coverage/default/1.chip_sw_edn_boot_mode.2595208746 Apr 21 03:11:56 PM PDT 24 Apr 21 03:19:20 PM PDT 24 2875659742 ps
T49 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.4232638407 Apr 21 02:56:49 PM PDT 24 Apr 21 02:59:49 PM PDT 24 2233953068 ps
T281 /workspace/coverage/default/1.chip_sw_plic_sw_irq.307037521 Apr 21 03:13:22 PM PDT 24 Apr 21 03:17:40 PM PDT 24 3089952664 ps
T400 /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.1956999188 Apr 21 02:57:49 PM PDT 24 Apr 21 03:17:23 PM PDT 24 6865119760 ps
T401 /workspace/coverage/default/36.chip_sw_all_escalation_resets.2718914416 Apr 21 03:35:12 PM PDT 24 Apr 21 03:48:11 PM PDT 24 6152728784 ps
T402 /workspace/coverage/default/1.chip_tap_straps_testunlock0.720670113 Apr 21 03:14:21 PM PDT 24 Apr 21 03:17:15 PM PDT 24 2610738986 ps
T408 /workspace/coverage/default/1.chip_sw_edn_auto_mode.3020306311 Apr 21 03:12:05 PM PDT 24 Apr 21 03:35:10 PM PDT 24 6066357840 ps
T421 /workspace/coverage/default/45.chip_sw_all_escalation_resets.3196611910 Apr 21 03:37:12 PM PDT 24 Apr 21 03:47:29 PM PDT 24 6062731864 ps
T422 /workspace/coverage/default/31.chip_sw_all_escalation_resets.1613701852 Apr 21 03:34:59 PM PDT 24 Apr 21 03:45:55 PM PDT 24 5457191680 ps
T423 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.3882691042 Apr 21 03:07:59 PM PDT 24 Apr 21 04:01:59 PM PDT 24 12834214987 ps
T188 /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.861668793 Apr 21 03:24:32 PM PDT 24 Apr 21 03:38:56 PM PDT 24 8412547797 ps
T148 /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.2358153457 Apr 21 03:00:35 PM PDT 24 Apr 21 03:34:53 PM PDT 24 11495812648 ps
T573 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.3955906307 Apr 21 03:20:06 PM PDT 24 Apr 21 03:29:58 PM PDT 24 8247753266 ps
T574 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.3364912947 Apr 21 03:00:36 PM PDT 24 Apr 21 03:10:52 PM PDT 24 5750446331 ps
T166 /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.2185533601 Apr 21 03:00:10 PM PDT 24 Apr 21 03:16:46 PM PDT 24 8661980600 ps
T262 /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.1244917097 Apr 21 03:07:28 PM PDT 24 Apr 21 03:13:37 PM PDT 24 4485321401 ps
T472 /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.661998345 Apr 21 03:37:22 PM PDT 24 Apr 21 03:43:30 PM PDT 24 3431069714 ps
T348 /workspace/coverage/default/2.chip_sw_entropy_src_csrng.55234418 Apr 21 03:26:01 PM PDT 24 Apr 21 03:55:52 PM PDT 24 8466101628 ps
T575 /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.3626841429 Apr 21 03:36:33 PM PDT 24 Apr 21 03:43:19 PM PDT 24 3582731000 ps
T241 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.3873798839 Apr 21 02:57:48 PM PDT 24 Apr 21 03:10:00 PM PDT 24 4778914236 ps
T576 /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.26099717 Apr 21 03:11:10 PM PDT 24 Apr 21 03:20:48 PM PDT 24 4682966050 ps
T167 /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.3717381133 Apr 21 03:10:05 PM PDT 24 Apr 21 03:13:22 PM PDT 24 2296117902 ps
T53 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1079701136 Apr 21 03:15:31 PM PDT 24 Apr 21 03:39:02 PM PDT 24 20117037624 ps
T491 /workspace/coverage/default/77.chip_sw_all_escalation_resets.1390837078 Apr 21 03:39:05 PM PDT 24 Apr 21 03:48:09 PM PDT 24 5353073860 ps
T577 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.1153959335 Apr 21 03:24:44 PM PDT 24 Apr 21 03:34:13 PM PDT 24 5055261484 ps
T578 /workspace/coverage/default/1.chip_sw_gpio_smoketest.1658376523 Apr 21 03:19:15 PM PDT 24 Apr 21 03:24:34 PM PDT 24 2818862673 ps
T323 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.1438680815 Apr 21 03:01:35 PM PDT 24 Apr 21 03:12:52 PM PDT 24 4704567884 ps
T19 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.1511300990 Apr 21 03:10:43 PM PDT 24 Apr 21 04:18:04 PM PDT 24 20542846493 ps
T579 /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.2450824748 Apr 21 03:16:27 PM PDT 24 Apr 21 03:20:48 PM PDT 24 2647277936 ps
T411 /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.1809013623 Apr 21 03:33:32 PM PDT 24 Apr 21 03:41:45 PM PDT 24 3924223688 ps
T580 /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.2602805295 Apr 21 03:20:00 PM PDT 24 Apr 21 03:27:02 PM PDT 24 3466281106 ps
T136 /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.2582915961 Apr 21 03:32:52 PM PDT 24 Apr 21 03:45:44 PM PDT 24 8215512376 ps
T581 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.3384843248 Apr 21 03:12:27 PM PDT 24 Apr 21 03:16:33 PM PDT 24 2603456932 ps
T582 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.3083205596 Apr 21 03:02:01 PM PDT 24 Apr 21 03:09:18 PM PDT 24 6005029232 ps
T583 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.1424959734 Apr 21 02:59:36 PM PDT 24 Apr 21 03:24:21 PM PDT 24 8384121368 ps
T584 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.1929892667 Apr 21 03:10:31 PM PDT 24 Apr 21 03:14:42 PM PDT 24 3103280144 ps
T585 /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.3568130565 Apr 21 03:15:47 PM PDT 24 Apr 21 03:24:32 PM PDT 24 4045696056 ps
T586 /workspace/coverage/default/0.chip_sw_usbdev_stream.4153334989 Apr 21 02:58:02 PM PDT 24 Apr 21 04:26:57 PM PDT 24 18561873080 ps
T587 /workspace/coverage/default/0.chip_sw_aes_idle.3565773780 Apr 21 03:01:01 PM PDT 24 Apr 21 03:04:27 PM PDT 24 2521401886 ps
T5 /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.2947653147 Apr 21 03:18:02 PM PDT 24 Apr 21 03:24:07 PM PDT 24 3863086359 ps
T588 /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.2826797999 Apr 21 02:58:58 PM PDT 24 Apr 21 03:08:29 PM PDT 24 4686397724 ps
T58 /workspace/coverage/default/0.chip_sw_sleep_pin_wake.171721034 Apr 21 02:57:59 PM PDT 24 Apr 21 03:02:10 PM PDT 24 3191858300 ps
T432 /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3039942473 Apr 21 03:38:33 PM PDT 24 Apr 21 03:45:33 PM PDT 24 4011153128 ps
T113 /workspace/coverage/default/1.chip_sw_inject_scramble_seed.1911312389 Apr 21 03:07:48 PM PDT 24 Apr 21 06:48:04 PM PDT 24 64943262659 ps
T433 /workspace/coverage/default/4.chip_sw_uart_tx_rx.164437163 Apr 21 03:31:33 PM PDT 24 Apr 21 03:42:28 PM PDT 24 3510957000 ps
T434 /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.3853253419 Apr 21 03:15:55 PM PDT 24 Apr 21 03:23:29 PM PDT 24 5349202350 ps
T435 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3846597031 Apr 21 03:22:10 PM PDT 24 Apr 21 04:11:06 PM PDT 24 24820169292 ps
T232 /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.2247124000 Apr 21 03:27:31 PM PDT 24 Apr 21 03:31:43 PM PDT 24 2967486472 ps
T245 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.3220218227 Apr 21 03:09:09 PM PDT 24 Apr 21 03:27:58 PM PDT 24 6134495950 ps
T436 /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.1486303347 Apr 21 03:09:28 PM PDT 24 Apr 21 03:16:52 PM PDT 24 4269044724 ps
T437 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1989525939 Apr 21 03:08:40 PM PDT 24 Apr 21 03:19:13 PM PDT 24 3884121120 ps
T589 /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.2744510377 Apr 21 03:10:42 PM PDT 24 Apr 21 03:55:58 PM PDT 24 24166390001 ps
T590 /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.898687065 Apr 21 03:32:01 PM PDT 24 Apr 21 03:58:01 PM PDT 24 8323208888 ps
T302 /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.1021119429 Apr 21 03:21:32 PM PDT 24 Apr 21 03:29:28 PM PDT 24 4330046784 ps
T468 /workspace/coverage/default/41.chip_sw_all_escalation_resets.1584557179 Apr 21 03:35:48 PM PDT 24 Apr 21 03:49:40 PM PDT 24 5225349880 ps
T438 /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2994803802 Apr 21 03:32:12 PM PDT 24 Apr 21 03:38:27 PM PDT 24 3503365304 ps
T469 /workspace/coverage/default/84.chip_sw_all_escalation_resets.2751939906 Apr 21 03:40:16 PM PDT 24 Apr 21 03:50:21 PM PDT 24 4580305768 ps
T591 /workspace/coverage/default/0.chip_sw_hmac_smoketest.3031180016 Apr 21 03:06:05 PM PDT 24 Apr 21 03:11:15 PM PDT 24 2533801368 ps
T592 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.925775579 Apr 21 03:16:54 PM PDT 24 Apr 21 03:26:24 PM PDT 24 3677741960 ps
T593 /workspace/coverage/default/0.chip_sw_kmac_smoketest.3000074323 Apr 21 03:06:37 PM PDT 24 Apr 21 03:12:58 PM PDT 24 3587711646 ps
T354 /workspace/coverage/default/79.chip_sw_all_escalation_resets.4010242755 Apr 21 03:38:42 PM PDT 24 Apr 21 03:49:34 PM PDT 24 4823279880 ps
T368 /workspace/coverage/default/69.chip_sw_all_escalation_resets.2827394945 Apr 21 03:42:26 PM PDT 24 Apr 21 03:52:09 PM PDT 24 5357845920 ps
T594 /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.1418331806 Apr 21 03:13:21 PM PDT 24 Apr 21 03:17:24 PM PDT 24 2836463060 ps
T595 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.1570352526 Apr 21 03:01:01 PM PDT 24 Apr 21 03:04:43 PM PDT 24 3075958137 ps
T596 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.965453554 Apr 21 03:21:43 PM PDT 24 Apr 21 03:32:48 PM PDT 24 5241076824 ps
T325 /workspace/coverage/default/2.chip_sw_power_sleep_load.3615299011 Apr 21 03:28:49 PM PDT 24 Apr 21 03:39:11 PM PDT 24 10739632768 ps
T376 /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.3931236312 Apr 21 03:11:01 PM PDT 24 Apr 21 03:43:32 PM PDT 24 9395342885 ps
T346 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3634371062 Apr 21 03:27:11 PM PDT 24 Apr 21 03:39:11 PM PDT 24 4435019042 ps
T84 /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2848580556 Apr 21 03:14:14 PM PDT 24 Apr 21 06:49:54 PM PDT 24 256044788000 ps
T597 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.4275774603 Apr 21 03:08:48 PM PDT 24 Apr 21 03:28:44 PM PDT 24 6918301736 ps
T598 /workspace/coverage/default/2.chip_sw_flash_ctrl_access.1031610051 Apr 21 03:21:00 PM PDT 24 Apr 21 03:39:59 PM PDT 24 5722970680 ps
T37 /workspace/coverage/default/2.chip_sw_spi_device_tpm.1277808697 Apr 21 03:17:57 PM PDT 24 Apr 21 03:25:59 PM PDT 24 3558879516 ps
T599 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3281528077 Apr 21 03:20:44 PM PDT 24 Apr 21 03:27:30 PM PDT 24 7306818236 ps
T6 /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2833283294 Apr 21 02:56:16 PM PDT 24 Apr 21 03:00:14 PM PDT 24 2660838369 ps
T600 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.135299473 Apr 21 03:01:59 PM PDT 24 Apr 21 03:05:59 PM PDT 24 2250207152 ps
T601 /workspace/coverage/default/73.chip_sw_all_escalation_resets.675948293 Apr 21 03:38:34 PM PDT 24 Apr 21 03:50:15 PM PDT 24 5192899988 ps
T602 /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.2381514551 Apr 21 02:59:44 PM PDT 24 Apr 21 03:06:06 PM PDT 24 3668312026 ps
T373 /workspace/coverage/default/2.chip_sw_power_idle_load.1251607805 Apr 21 03:28:07 PM PDT 24 Apr 21 03:40:45 PM PDT 24 4502956890 ps
T38 /workspace/coverage/default/1.chip_sw_spi_device_tpm.208186900 Apr 21 03:07:57 PM PDT 24 Apr 21 03:14:36 PM PDT 24 3631348001 ps
T24 /workspace/coverage/default/1.chip_sw_gpio.440403931 Apr 21 03:08:50 PM PDT 24 Apr 21 03:16:48 PM PDT 24 3419102790 ps
T412 /workspace/coverage/default/2.chip_sw_edn_kat.983833163 Apr 21 03:23:01 PM PDT 24 Apr 21 03:33:26 PM PDT 24 3460978254 ps
T235 /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.4166651040 Apr 21 03:07:32 PM PDT 24 Apr 21 04:34:24 PM PDT 24 43742595205 ps
T413 /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2641590395 Apr 21 03:36:47 PM PDT 24 Apr 21 03:44:53 PM PDT 24 4035985472 ps
T603 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2883744986 Apr 21 03:24:48 PM PDT 24 Apr 21 04:12:49 PM PDT 24 30522080098 ps
T246 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.3839613024 Apr 21 03:21:10 PM PDT 24 Apr 21 03:35:41 PM PDT 24 4736772440 ps
T133 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2070973319 Apr 21 02:59:15 PM PDT 24 Apr 21 03:05:09 PM PDT 24 4746608728 ps
T604 /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.489188046 Apr 21 03:32:56 PM PDT 24 Apr 21 04:00:54 PM PDT 24 8245209408 ps
T605 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.2337612428 Apr 21 03:31:05 PM PDT 24 Apr 21 03:41:32 PM PDT 24 3819902184 ps
T511 /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.3855013875 Apr 21 03:40:23 PM PDT 24 Apr 21 03:47:17 PM PDT 24 3083234504 ps
T259 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.1296893213 Apr 21 03:13:01 PM PDT 24 Apr 21 05:06:22 PM PDT 24 48709554099 ps
T123 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.3275079439 Apr 21 03:13:41 PM PDT 24 Apr 21 03:19:54 PM PDT 24 3913372076 ps
T606 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2292127469 Apr 21 03:28:03 PM PDT 24 Apr 21 03:45:32 PM PDT 24 7715110484 ps
T607 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.3182949377 Apr 21 03:00:26 PM PDT 24 Apr 21 04:56:38 PM PDT 24 23774234480 ps
T478 /workspace/coverage/default/1.chip_sw_ast_clk_outputs.2914702751 Apr 21 03:16:55 PM PDT 24 Apr 21 03:31:04 PM PDT 24 6824659632 ps
T608 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1775328341 Apr 21 03:20:02 PM PDT 24 Apr 21 03:42:30 PM PDT 24 11455025351 ps
T279 /workspace/coverage/default/9.chip_sw_all_escalation_resets.1720577323 Apr 21 03:33:56 PM PDT 24 Apr 21 03:44:46 PM PDT 24 4488538480 ps
T364 /workspace/coverage/default/0.chip_sival_flash_info_access.697331726 Apr 21 02:57:43 PM PDT 24 Apr 21 03:03:08 PM PDT 24 2600625420 ps
T609 /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.648901263 Apr 21 03:34:10 PM PDT 24 Apr 21 03:41:38 PM PDT 24 3891066232 ps
T303 /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.4183709778 Apr 21 02:58:17 PM PDT 24 Apr 21 03:05:21 PM PDT 24 3902564968 ps
T501 /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.3018608202 Apr 21 03:34:00 PM PDT 24 Apr 21 03:39:56 PM PDT 24 3202428368 ps
T524 /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.3411674154 Apr 21 03:30:20 PM PDT 24 Apr 21 03:36:10 PM PDT 24 3842364600 ps
T610 /workspace/coverage/default/1.chip_sw_otbn_randomness.3428103433 Apr 21 03:10:50 PM PDT 24 Apr 21 03:26:29 PM PDT 24 5653116612 ps
T165 /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.1092335095 Apr 21 03:25:32 PM PDT 24 Apr 21 03:35:40 PM PDT 24 8384020033 ps
T324 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.1225414053 Apr 21 03:12:37 PM PDT 24 Apr 21 03:32:28 PM PDT 24 5801780026 ps
T25 /workspace/coverage/default/0.chip_sw_gpio.3048891334 Apr 21 02:57:04 PM PDT 24 Apr 21 03:04:56 PM PDT 24 4455000358 ps
T482 /workspace/coverage/default/39.chip_sw_all_escalation_resets.3462540884 Apr 21 03:35:12 PM PDT 24 Apr 21 03:49:40 PM PDT 24 5578543176 ps
T515 /workspace/coverage/default/7.chip_sw_all_escalation_resets.2488054452 Apr 21 03:31:09 PM PDT 24 Apr 21 03:40:19 PM PDT 24 4687505898 ps
T229 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3412889001 Apr 21 03:24:42 PM PDT 24 Apr 21 03:33:08 PM PDT 24 5034888259 ps
T611 /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.550743989 Apr 21 03:20:44 PM PDT 24 Apr 21 03:29:10 PM PDT 24 4722669360 ps
T612 /workspace/coverage/default/2.chip_sival_flash_info_access.1881920476 Apr 21 03:17:00 PM PDT 24 Apr 21 03:22:03 PM PDT 24 3608353044 ps
T334 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.1881217791 Apr 21 03:14:11 PM PDT 24 Apr 21 03:23:17 PM PDT 24 6461956360 ps
T443 /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.1921553420 Apr 21 03:20:04 PM PDT 24 Apr 21 03:22:12 PM PDT 24 2986913408 ps
T613 /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.1856765195 Apr 21 03:05:35 PM PDT 24 Apr 21 03:09:37 PM PDT 24 3359496400 ps
T614 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1103875157 Apr 21 03:07:21 PM PDT 24 Apr 21 03:37:34 PM PDT 24 13677618224 ps
T615 /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.658581904 Apr 21 03:11:57 PM PDT 24 Apr 21 03:18:53 PM PDT 24 4034541860 ps
T343 /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2134737093 Apr 21 03:21:42 PM PDT 24 Apr 21 03:34:24 PM PDT 24 19332067542 ps
T616 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.30892707 Apr 21 03:08:46 PM PDT 24 Apr 21 03:18:23 PM PDT 24 4296755834 ps
T327 /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.49190059 Apr 21 03:36:25 PM PDT 24 Apr 21 03:43:39 PM PDT 24 3635455116 ps
T617 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.309211221 Apr 21 02:57:26 PM PDT 24 Apr 21 03:06:55 PM PDT 24 4665401630 ps
T509 /workspace/coverage/default/56.chip_sw_all_escalation_resets.1048350027 Apr 21 03:36:25 PM PDT 24 Apr 21 03:51:22 PM PDT 24 5220346968 ps
T618 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1288042964 Apr 21 03:23:56 PM PDT 24 Apr 21 04:34:16 PM PDT 24 19134794110 ps
T168 /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.1418128538 Apr 21 03:20:01 PM PDT 24 Apr 21 03:23:40 PM PDT 24 2702421144 ps
T206 /workspace/coverage/default/1.chip_sw_power_idle_load.2617390498 Apr 21 03:16:58 PM PDT 24 Apr 21 03:30:35 PM PDT 24 4260224622 ps
T619 /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.24379497 Apr 21 03:10:18 PM PDT 24 Apr 21 03:29:32 PM PDT 24 8482881440 ps
T620 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.584046741 Apr 21 03:16:12 PM PDT 24 Apr 21 03:26:19 PM PDT 24 6554256300 ps
T215 /workspace/coverage/default/66.chip_sw_all_escalation_resets.1803580749 Apr 21 03:37:22 PM PDT 24 Apr 21 03:51:09 PM PDT 24 5085183328 ps
T512 /workspace/coverage/default/27.chip_sw_all_escalation_resets.1471489220 Apr 21 03:36:43 PM PDT 24 Apr 21 03:45:33 PM PDT 24 4064078592 ps
T202 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.2741911698 Apr 21 03:16:32 PM PDT 24 Apr 21 03:20:39 PM PDT 24 2474672722 ps
T260 /workspace/coverage/default/1.chip_sw_flash_init.2310951058 Apr 21 03:07:05 PM PDT 24 Apr 21 03:40:20 PM PDT 24 19955496417 ps
T304 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.1354254259 Apr 21 03:16:15 PM PDT 24 Apr 21 03:26:04 PM PDT 24 3905808074 ps
T359 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3074913557 Apr 21 02:58:34 PM PDT 24 Apr 21 03:29:31 PM PDT 24 11478209674 ps
T360 /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.1537017474 Apr 21 03:23:07 PM PDT 24 Apr 21 03:28:13 PM PDT 24 2839516462 ps
T85 /workspace/coverage/default/0.chip_sw_alert_handler_entropy.3477386090 Apr 21 03:00:37 PM PDT 24 Apr 21 03:05:29 PM PDT 24 3041453325 ps
T621 /workspace/coverage/default/1.chip_sw_uart_smoketest.592717764 Apr 21 03:18:07 PM PDT 24 Apr 21 03:21:48 PM PDT 24 2713956532 ps
T622 /workspace/coverage/default/2.chip_sw_uart_tx_rx.1227305883 Apr 21 03:20:30 PM PDT 24 Apr 21 03:31:10 PM PDT 24 4073320086 ps
T492 /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.947283427 Apr 21 03:42:19 PM PDT 24 Apr 21 03:49:30 PM PDT 24 3562827460 ps
T623 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.2733806731 Apr 21 03:22:33 PM PDT 24 Apr 21 03:36:54 PM PDT 24 4709498045 ps
T285 /workspace/coverage/default/0.chip_sw_rv_timer_irq.3992585614 Apr 21 02:59:06 PM PDT 24 Apr 21 03:04:15 PM PDT 24 3446595894 ps
T624 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.645992374 Apr 21 02:58:44 PM PDT 24 Apr 21 03:08:44 PM PDT 24 4974927226 ps
T625 /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.579403960 Apr 21 03:15:11 PM PDT 24 Apr 21 03:26:30 PM PDT 24 4971729170 ps
T33 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.314923647 Apr 21 03:21:44 PM PDT 24 Apr 21 03:27:04 PM PDT 24 4898457600 ps
T7 /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3617860354 Apr 21 03:06:26 PM PDT 24 Apr 21 03:12:14 PM PDT 24 3035738619 ps
T626 /workspace/coverage/default/2.chip_sw_edn_sw_mode.1815472878 Apr 21 03:24:05 PM PDT 24 Apr 21 04:04:20 PM PDT 24 11063275640 ps
T627 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2882995537 Apr 21 02:59:41 PM PDT 24 Apr 21 03:08:36 PM PDT 24 4387259630 ps
T628 /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.2911671228 Apr 21 03:14:22 PM PDT 24 Apr 21 03:42:39 PM PDT 24 11344565246 ps
T374 /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.489114696 Apr 21 03:12:25 PM PDT 24 Apr 21 03:25:56 PM PDT 24 4290148096 ps
T444 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3596040971 Apr 21 03:10:05 PM PDT 24 Apr 21 03:11:51 PM PDT 24 2010312509 ps
T191 /workspace/coverage/default/2.chip_plic_all_irqs_0.2430766367 Apr 21 03:25:22 PM PDT 24 Apr 21 03:43:03 PM PDT 24 6076882666 ps
T160 /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3979815680 Apr 21 03:27:41 PM PDT 24 Apr 21 03:37:11 PM PDT 24 4517673410 ps
T629 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.2435027835 Apr 21 03:27:47 PM PDT 24 Apr 21 03:30:54 PM PDT 24 2480133626 ps
T476 /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3388892323 Apr 21 03:38:12 PM PDT 24 Apr 21 03:44:51 PM PDT 24 3565523936 ps
T630 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3980441113 Apr 21 03:12:00 PM PDT 24 Apr 21 03:19:27 PM PDT 24 6367633898 ps
T631 /workspace/coverage/default/2.chip_sw_alert_handler_escalation.2157354932 Apr 21 03:23:31 PM PDT 24 Apr 21 03:32:11 PM PDT 24 5751505530 ps
T503 /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.1035222709 Apr 21 03:34:42 PM PDT 24 Apr 21 03:41:30 PM PDT 24 3673457556 ps
T481 /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2986925443 Apr 21 03:41:09 PM PDT 24 Apr 21 03:48:47 PM PDT 24 3976102470 ps
T519 /workspace/coverage/default/16.chip_sw_all_escalation_resets.4182229593 Apr 21 03:32:13 PM PDT 24 Apr 21 03:41:11 PM PDT 24 5903166978 ps
T305 /workspace/coverage/default/2.chip_sw_data_integrity_escalation.1065369951 Apr 21 03:17:58 PM PDT 24 Apr 21 03:28:10 PM PDT 24 5569219656 ps
T632 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.2554023648 Apr 21 02:59:45 PM PDT 24 Apr 21 03:09:48 PM PDT 24 7294929904 ps
T34 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.4091860978 Apr 21 03:11:32 PM PDT 24 Apr 21 03:19:17 PM PDT 24 6019658096 ps
T633 /workspace/coverage/default/2.chip_sw_example_concurrency.3442200074 Apr 21 03:17:15 PM PDT 24 Apr 21 03:21:38 PM PDT 24 2281547148 ps
T634 /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.3309123342 Apr 21 03:29:21 PM PDT 24 Apr 21 03:32:31 PM PDT 24 2785034562 ps
T329 /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.2182543493 Apr 21 03:14:01 PM PDT 24 Apr 21 03:46:50 PM PDT 24 13032856460 ps
T635 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1322170946 Apr 21 03:13:48 PM PDT 24 Apr 21 03:25:33 PM PDT 24 4962917060 ps
T467 /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.547050300 Apr 21 03:36:48 PM PDT 24 Apr 21 03:43:52 PM PDT 24 4225064152 ps
T261 /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.818894755 Apr 21 03:19:16 PM PDT 24 Apr 21 05:07:48 PM PDT 24 49499778190 ps
T636 /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.1050707027 Apr 21 02:59:29 PM PDT 24 Apr 21 03:08:48 PM PDT 24 6831786832 ps
T637 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.3702916070 Apr 21 03:14:56 PM PDT 24 Apr 21 03:18:52 PM PDT 24 2571392303 ps
T217 /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.4247401614 Apr 21 03:08:24 PM PDT 24 Apr 21 03:10:10 PM PDT 24 2695000075 ps
T219 /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.869924940 Apr 21 03:20:06 PM PDT 24 Apr 21 03:22:07 PM PDT 24 2552848888 ps
T520 /workspace/coverage/default/10.chip_sw_all_escalation_resets.3832653399 Apr 21 03:33:10 PM PDT 24 Apr 21 03:43:11 PM PDT 24 5915296224 ps
T638 /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.3132332863 Apr 21 03:33:24 PM PDT 24 Apr 21 03:40:30 PM PDT 24 4102504268 ps
T639 /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3654902079 Apr 21 03:32:37 PM PDT 24 Apr 21 03:54:40 PM PDT 24 10106614688 ps
T361 /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.2022362914 Apr 21 02:57:27 PM PDT 24 Apr 21 03:04:45 PM PDT 24 2992761440 ps
T464 /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.97133947 Apr 21 03:37:07 PM PDT 24 Apr 21 03:44:14 PM PDT 24 3873608600 ps
T640 /workspace/coverage/default/2.chip_tap_straps_dev.3127780784 Apr 21 03:26:48 PM PDT 24 Apr 21 03:56:00 PM PDT 24 13692590284 ps
T403 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.1918193909 Apr 21 03:25:41 PM PDT 24 Apr 21 03:40:12 PM PDT 24 5570973076 ps
T130 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.2507489361 Apr 21 03:16:11 PM PDT 24 Apr 21 04:19:36 PM PDT 24 20775336695 ps
T641 /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.1131816943 Apr 21 02:57:02 PM PDT 24 Apr 21 03:19:12 PM PDT 24 8317119480 ps
T642 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2597528781 Apr 21 03:26:18 PM PDT 24 Apr 21 03:35:54 PM PDT 24 4663548390 ps
T441 /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.4288451985 Apr 21 03:26:36 PM PDT 24 Apr 21 03:36:09 PM PDT 24 5553597750 ps
T643 /workspace/coverage/default/2.chip_sw_csrng_kat_test.3085272294 Apr 21 03:23:36 PM PDT 24 Apr 21 03:27:51 PM PDT 24 2873460132 ps
T644 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.878137054 Apr 21 03:01:03 PM PDT 24 Apr 21 03:21:51 PM PDT 24 7461563972 ps
T466 /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.1011819327 Apr 21 03:42:48 PM PDT 24 Apr 21 03:51:39 PM PDT 24 4008403520 ps
T319 /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.481160727 Apr 21 03:12:43 PM PDT 24 Apr 21 03:18:10 PM PDT 24 3681944516 ps
T645 /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.2764194086 Apr 21 03:01:39 PM PDT 24 Apr 21 03:38:53 PM PDT 24 24301679576 ps
T646 /workspace/coverage/default/4.chip_tap_straps_testunlock0.1297990910 Apr 21 03:30:45 PM PDT 24 Apr 21 03:42:03 PM PDT 24 6414492433 ps
T647 /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.1429875563 Apr 21 03:13:18 PM PDT 24 Apr 21 03:20:57 PM PDT 24 4667686700 ps
T648 /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.1387514196 Apr 21 03:08:38 PM PDT 24 Apr 21 03:13:58 PM PDT 24 2981742380 ps
T649 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.4108184701 Apr 21 03:29:33 PM PDT 24 Apr 21 03:40:22 PM PDT 24 4336226728 ps
T650 /workspace/coverage/default/1.chip_sw_kmac_idle.3414724415 Apr 21 03:13:58 PM PDT 24 Apr 21 03:17:03 PM PDT 24 2328623468 ps
T372 /workspace/coverage/default/96.chip_sw_all_escalation_resets.1005664377 Apr 21 03:40:41 PM PDT 24 Apr 21 03:51:28 PM PDT 24 5050263462 ps
T651 /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1641464016 Apr 21 03:37:09 PM PDT 24 Apr 21 03:44:33 PM PDT 24 3991682918 ps
T652 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.946362287 Apr 21 03:26:26 PM PDT 24 Apr 21 03:38:03 PM PDT 24 3896745560 ps
T653 /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.1266186383 Apr 21 03:29:38 PM PDT 24 Apr 21 03:34:25 PM PDT 24 2375130500 ps
T504 /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.87182962 Apr 21 03:35:18 PM PDT 24 Apr 21 03:42:54 PM PDT 24 3738582560 ps
T654 /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.2312234866 Apr 21 03:32:51 PM PDT 24 Apr 21 04:20:43 PM PDT 24 13326047722 ps
T655 /workspace/coverage/default/1.rom_keymgr_functest.939318410 Apr 21 03:16:47 PM PDT 24 Apr 21 03:25:26 PM PDT 24 3934485732 ps
T656 /workspace/coverage/default/1.chip_sw_example_rom.2386115519 Apr 21 03:05:53 PM PDT 24 Apr 21 03:07:44 PM PDT 24 1968328000 ps
T43 /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.2654333410 Apr 21 03:32:40 PM PDT 24 Apr 21 08:30:09 PM PDT 24 78510368997 ps
T657 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.409013879 Apr 21 02:56:17 PM PDT 24 Apr 21 03:05:19 PM PDT 24 3926393472 ps
T658 /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.2691796348 Apr 21 03:33:07 PM PDT 24 Apr 21 04:22:58 PM PDT 24 13132726272 ps
T81 /workspace/coverage/default/2.chip_jtag_mem_access.3496026252 Apr 21 03:19:08 PM PDT 24 Apr 21 03:41:46 PM PDT 24 13691406288 ps
T659 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.147439900 Apr 21 02:59:52 PM PDT 24 Apr 21 03:05:23 PM PDT 24 3366449895 ps
T517 /workspace/coverage/default/94.chip_sw_all_escalation_resets.3223158241 Apr 21 03:39:32 PM PDT 24 Apr 21 03:48:44 PM PDT 24 5013486992 ps
T660 /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.1475129914 Apr 21 03:36:23 PM PDT 24 Apr 21 03:44:05 PM PDT 24 4443084888 ps
T480 /workspace/coverage/default/1.chip_sw_aes_masking_off.2995445925 Apr 21 03:12:43 PM PDT 24 Apr 21 03:17:28 PM PDT 24 3105171307 ps
T134 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.910356849 Apr 21 03:13:26 PM PDT 24 Apr 21 03:20:26 PM PDT 24 4995549368 ps
T404 /workspace/coverage/default/0.chip_sw_kmac_entropy.741839432 Apr 21 02:57:42 PM PDT 24 Apr 21 03:01:12 PM PDT 24 2918947640 ps
T306 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.2961361432 Apr 21 02:59:55 PM PDT 24 Apr 21 03:09:23 PM PDT 24 4968967972 ps
T465 /workspace/coverage/default/75.chip_sw_all_escalation_resets.602666149 Apr 21 03:38:20 PM PDT 24 Apr 21 03:49:51 PM PDT 24 5742661388 ps
T661 /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.517886842 Apr 21 03:34:36 PM PDT 24 Apr 21 03:43:11 PM PDT 24 3543657970 ps
T662 /workspace/coverage/default/0.chip_sw_csrng_kat_test.4083310099 Apr 21 02:58:54 PM PDT 24 Apr 21 03:01:55 PM PDT 24 2789800888 ps
T345 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.3914008089 Apr 21 03:20:01 PM PDT 24 Apr 21 03:47:48 PM PDT 24 24088670976 ps
T663 /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.192642679 Apr 21 02:58:39 PM PDT 24 Apr 21 03:01:45 PM PDT 24 2720568040 ps
T265 /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.3249749626 Apr 21 03:27:19 PM PDT 24 Apr 21 04:01:36 PM PDT 24 25806278561 ps
T499 /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.4076074848 Apr 21 03:38:16 PM PDT 24 Apr 21 03:42:56 PM PDT 24 3109777208 ps
T664 /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.1944086655 Apr 21 03:17:08 PM PDT 24 Apr 21 03:25:31 PM PDT 24 3618563776 ps
T665 /workspace/coverage/default/2.chip_sw_hmac_enc_idle.2557889937 Apr 21 03:26:12 PM PDT 24 Apr 21 03:30:08 PM PDT 24 3184711256 ps
T405 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1861520478 Apr 21 03:01:36 PM PDT 24 Apr 21 04:14:22 PM PDT 24 24427238566 ps
T102 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2177798992 Apr 21 03:26:26 PM PDT 24 Apr 21 03:34:23 PM PDT 24 7650366006 ps
T666 /workspace/coverage/default/1.chip_tap_straps_prod.680941722 Apr 21 03:14:30 PM PDT 24 Apr 21 03:17:07 PM PDT 24 2716853312 ps
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