Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3652814	1			T81	1577		T82	664		T83	260
values[2]	738800	1			T81	116		T82	128		T83	700
values[3]	113375	1			T81	3		T82	36		T83	411
values[4]	60799	1			T82	29		T83	338		T501	14
values[5]	40762	1			T82	31		T83	247		T501	14
values[6]	29951	1			T82	33		T83	196		T501	14
values[7]	24313	1			T82	38		T83	177		T501	14
values[8]	20244	1			T82	30		T83	139		T501	14
values[9]	17751	1			T82	39		T83	88		T501	14
values[10]	15839	1			T82	29		T83	89		T501	14
values[11]	14795	1			T82	32		T83	88		T501	14
values[12]	13685	1			T82	28		T83	81		T501	14
values[13]	12875	1			T82	16		T83	111		T501	14
values[14]	11938	1			T82	21		T83	102		T501	15
values[15]	11320	1			T82	37		T83	72		T501	15
values[16]	10989	1			T82	39		T83	76		T501	14
values[17]	10610	1			T82	47		T83	45		T501	14
values[18]	10280	1			T82	22		T83	56		T501	14
values[19]	10183	1			T82	20		T83	50		T501	14
values[20]	9519	1			T82	33		T83	40		T501	14
values[21]	9002	1			T82	28		T83	38		T501	14
values[22]	8551	1			T82	21		T83	20		T501	14
values[23]	8472	1			T82	24		T83	24		T501	15
values[24]	7980	1			T82	27		T83	30		T501	15
values[25]	7545	1			T82	16		T83	25		T501	14
values[26]	7239	1			T82	20		T83	12		T501	14
values[27]	7114	1			T82	21		T83	23		T501	15
values[28]	6820	1			T82	21		T83	15		T501	15
values[29]	6462	1			T82	33		T83	10		T501	14
values[30]	6066	1			T82	20		T83	21		T501	14
values[31]	5628	1			T82	26		T83	32		T501	14
values[32]	5206	1			T82	11		T83	11		T501	14
values[33]	4733	1			T82	4		T83	9		T501	14
values[34]	4480	1			T82	1		T83	16		T501	15
values[35]	4238	1			T82	1		T83	21		T501	14
values[36]	3987	1			T82	1		T83	18		T501	15
values[37]	3680	1			T82	1		T83	21		T501	14
values[38]	3580	1			T82	1		T83	9		T501	14
values[39]	3490	1			T82	1		T83	11		T501	15
values[40]	3455	1			T82	1		T83	6		T501	16
values[41]	3353	1			T82	1		T83	9		T501	14
values[42]	3305	1			T82	1		T83	8		T501	14
values[43]	3277	1			T82	1		T83	5		T501	14
values[44]	3178	1			T82	3		T83	7		T501	15
values[45]	3123	1			T82	1		T83	5		T501	14
values[46]	3170	1			T82	3		T83	4		T501	14
values[47]	3057	1			T82	4		T83	10		T501	14
values[48]	2883	1			T82	1		T83	4		T501	14
values[49]	2975	1			T82	2		T83	3		T501	15
values[50]	2924	1			T82	1		T83	2		T501	14
values[51]	2835	1			T82	8		T83	3		T501	14
values[52]	2737	1			T82	3		T83	4		T501	14
values[53]	2782	1			T82	2		T83	6		T501	14
values[54]	2688	1			T82	3		T83	7		T501	15
values[55]	2678	1			T82	6		T83	7		T501	14
values[56]	2571	1			T82	2		T83	5		T501	14
values[57]	2542	1			T82	3		T83	2		T501	14
values[58]	2539	1			T82	3		T83	3		T501	15
values[59]	2482	1			T82	2		T83	3		T501	16
values[60]	2552	1			T82	4		T83	5		T501	14
values[61]	2903	1			T82	3		T83	5		T501	15
values[62]	4753	1			T82	3		T83	3		T501	14
values[63]	18048	1			T82	1		T83	15		T501	85
values[64]	215952	1			T83	82		T501	2522		T403	97

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4734460	1			T81	1537		T82	1503		T83	2943
values[2]	778141	1			T81	80		T82	336		T83	719
values[3]	76859	1			T81	4		T82	6		T83	107
values[4]	13601	1			T83	70		T86	7		T501	57
values[5]	5578	1			T83	69		T86	1		T501	17
values[6]	3517	1			T83	38		T501	7		T403	12
values[7]	2682	1			T83	40		T501	4		T403	12
values[8]	2149	1			T83	28		T501	2		T403	14
values[9]	1821	1			T83	26		T501	1		T403	10
values[10]	1584	1			T83	24		T501	1		T403	16
values[11]	1397	1			T83	13		T501	1		T403	11
values[12]	1347	1			T83	3		T501	1		T403	27
values[13]	1327	1			T83	1		T501	1		T403	15
values[14]	1316	1			T83	1		T501	1		T403	14
values[15]	1225	1			T501	1		T403	2		T677	1
values[16]	1124	1			T501	1		T403	1		T677	1
values[17]	979	1			T501	1		T403	1		T677	2
values[18]	993	1			T501	1		T403	1		T677	3
values[19]	878	1			T501	1		T403	2		T677	2
values[20]	875	1			T501	1		T403	5		T677	3
values[21]	823	1			T501	1		T403	8		T677	1
values[22]	790	1			T501	1		T403	14		T677	1
values[23]	769	1			T501	2		T403	13		T677	1
values[24]	744	1			T501	1		T403	11		T677	3
values[25]	735	1			T501	1		T403	4		T677	2
values[26]	726	1			T501	1		T403	4		T677	1
values[27]	685	1			T501	1		T403	1		T677	1
values[28]	649	1			T501	1		T677	1		T502	4
values[29]	606	1			T501	1		T677	1		T502	2
values[30]	602	1			T501	1		T677	1		T502	1
values[31]	594	1			T501	1		T677	2		T502	2
values[32]	545	1			T501	1		T677	3		T502	1
values[33]	513	1			T501	1		T677	3		T502	2
values[34]	497	1			T501	1		T677	4		T502	3
values[35]	478	1			T501	1		T677	2		T502	2
values[36]	513	1			T501	1		T677	2		T502	1
values[37]	462	1			T501	1		T677	2		T502	2
values[38]	473	1			T501	1		T677	1		T502	3
values[39]	480	1			T501	1		T677	2		T502	3
values[40]	475	1			T501	1		T677	1		T502	1
values[41]	444	1			T501	1		T677	3		T502	3
values[42]	406	1			T501	1		T677	1		T502	1
values[43]	400	1			T501	1		T677	2		T502	1
values[44]	400	1			T501	1		T677	3		T502	3
values[45]	403	1			T501	1		T677	2		T502	1
values[46]	406	1			T501	1		T677	3		T502	2
values[47]	371	1			T501	1		T677	1		T502	3
values[48]	392	1			T501	1		T677	2		T502	1
values[49]	401	1			T501	1		T677	1		T502	1
values[50]	372	1			T501	1		T677	2		T502	1
values[51]	369	1			T501	1		T677	3		T502	1
values[52]	371	1			T501	1		T677	1		T502	3
values[53]	396	1			T501	1		T677	1		T502	3
values[54]	354	1			T501	1		T677	1		T502	3
values[55]	369	1			T501	2		T677	1		T502	6
values[56]	341	1			T501	1		T677	1		T502	2
values[57]	324	1			T501	1		T677	1		T502	1
values[58]	317	1			T501	1		T677	1		T502	2
values[59]	304	1			T501	1		T677	2		T502	1
values[60]	327	1			T501	1		T677	3		T502	1
values[61]	364	1			T501	1		T677	2		T502	3
values[62]	624	1			T501	1		T677	11		T502	14
values[63]	2870	1			T501	15		T677	51		T502	34
values[64]	23141	1			T501	161		T677	87		T502	77

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	632354	1			T81	299		T82	7		T83	19
values[2]	2547960	1			T81	635		T82	665		T83	266
values[3]	1141842	1			T81	627		T82	94		T83	650
values[4]	156650	1			T81	4		T82	29		T83	468
values[5]	81707	1			T82	38		T83	314		T501	14
values[6]	54090	1			T82	43		T83	206		T501	14
values[7]	38589	1			T82	29		T83	237		T501	14
values[8]	30481	1			T82	9		T83	220		T501	14
values[9]	25728	1			T82	19		T83	182		T501	14
values[10]	22219	1			T82	37		T83	146		T501	14
values[11]	19529	1			T82	30		T83	146		T501	14
values[12]	18007	1			T82	35		T83	138		T501	14
values[13]	16739	1			T82	36		T83	91		T501	14
values[14]	15557	1			T82	19		T83	82		T501	14
values[15]	14761	1			T82	15		T83	53		T501	14
values[16]	13797	1			T82	22		T83	56		T501	14
values[17]	12811	1			T82	26		T83	69		T501	14
values[18]	11958	1			T82	53		T83	52		T501	14
values[19]	11586	1			T82	70		T83	48		T501	14
values[20]	11015	1			T82	50		T83	62		T501	14
values[21]	10522	1			T82	29		T83	57		T501	14
values[22]	10190	1			T82	24		T83	72		T501	14
values[23]	9750	1			T82	18		T83	59		T501	14
values[24]	9362	1			T82	24		T83	56		T501	14
values[25]	9021	1			T82	18		T83	63		T501	15
values[26]	8729	1			T82	29		T83	72		T501	14
values[27]	8416	1			T82	23		T83	62		T501	15
values[28]	7780	1			T82	14		T83	45		T501	15
values[29]	7229	1			T82	10		T83	25		T501	14
values[30]	7052	1			T82	18		T83	20		T501	14
values[31]	6348	1			T82	21		T83	15		T501	15
values[32]	5896	1			T82	15		T83	16		T501	14
values[33]	5632	1			T82	19		T83	18		T501	14
values[34]	5107	1			T82	7		T83	10		T501	14
values[35]	4775	1			T82	6		T83	5		T501	14
values[36]	4586	1			T82	8		T83	2		T501	14
values[37]	4190	1			T82	10		T83	1		T501	14
values[38]	3968	1			T82	2		T83	8		T501	14
values[39]	3904	1			T82	3		T83	11		T501	14
values[40]	3860	1			T82	3		T83	6		T501	14
values[41]	3621	1			T82	2		T83	9		T501	14
values[42]	3667	1			T82	3		T83	7		T501	14
values[43]	3523	1			T82	3		T83	7		T501	14
values[44]	3609	1			T82	4		T83	2		T501	14
values[45]	3448	1			T82	3		T83	7		T501	14
values[46]	3429	1			T82	6		T83	8		T501	14
values[47]	3438	1			T82	1		T83	3		T501	14
values[48]	3353	1			T82	2		T83	3		T501	14
values[49]	3216	1			T82	1		T83	1		T501	14
values[50]	3167	1			T82	1		T83	1		T501	14
values[51]	3198	1			T82	2		T83	3		T501	14
values[52]	3244	1			T82	2		T83	1		T501	14
values[53]	3215	1			T82	1		T83	4		T501	14
values[54]	3033	1			T82	2		T83	4		T501	14
values[55]	3030	1			T82	6		T83	3		T501	14
values[56]	2814	1			T82	1		T83	4		T501	14
values[57]	2800	1			T83	4		T501	14		T403	6
values[58]	2840	1			T83	3		T501	14		T403	8
values[59]	2867	1			T83	1		T501	18		T403	11
values[60]	2923	1			T83	1		T501	14		T403	3
values[61]	2950	1			T83	1		T501	14		T403	5
values[62]	4172	1			T83	6		T501	15		T403	5
values[63]	18682	1			T83	5		T501	21		T403	3
values[64]	201839	1			T83	17		T501	2503		T403	49