Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1864730	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

32487548

1

T1

8685

T2

8195

T3

348

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	23025529	1			T1	2486		T2	3898		T3	175
values[0x0]	9866889	1			T1	6199		T2	4297		T3	173
values[0x1]	1459860	1			T1	163		T2	466		T3	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	555301	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

33796977

1

T1

8848

T2

8661

T3

351

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16118134	1			T1	4424		T2	4331		T3	176
valid_sources[0x01]	16117566	1			T1	4424		T2	4330		T3	175
valid_sources[0x02]	34888	1			T17	1		T63	1		T406	1
valid_sources[0x03]	34984	1			T17	1		T143	60		T151	252
valid_sources[0x04]	34374	1			T143	39		T151	120		T152	818
valid_sources[0x05]	34451	1			T17	1		T84	1		T406	2
valid_sources[0x06]	33887	1			T205	1		T143	76		T151	164
valid_sources[0x07]	33666	1			T84	3		T406	1		T143	127
valid_sources[0x08]	33953	1			T63	1		T406	1		T143	40
valid_sources[0x09]	33601	1			T17	1		T63	1		T143	77
valid_sources[0x0a]	33468	1			T17	2		T84	2		T143	73
valid_sources[0x0b]	33814	1			T17	1		T63	2		T84	1
valid_sources[0x0c]	34736	1			T17	1		T63	2		T406	1
valid_sources[0x0d]	33399	1			T406	1		T205	1		T143	82
valid_sources[0x0e]	34341	1			T406	4		T143	102		T151	142
valid_sources[0x0f]	37183	1			T63	1		T84	3		T205	1
valid_sources[0x10]	34608	1			T205	1		T143	33		T151	120
valid_sources[0x11]	34283	1			T205	2		T143	69		T151	171
valid_sources[0x12]	34243	1			T84	1		T406	4		T143	90
valid_sources[0x13]	32737	1			T84	2		T205	1		T143	70
valid_sources[0x14]	33947	1			T17	2		T143	78		T151	119
valid_sources[0x15]	35086	1			T63	1		T205	2		T143	110
valid_sources[0x16]	34135	1			T17	1		T205	1		T143	109
valid_sources[0x17]	34289	1			T84	1		T406	1		T143	88
valid_sources[0x18]	33967	1			T63	2		T84	3		T143	77
valid_sources[0x19]	33940	1			T143	72		T151	124		T152	796
valid_sources[0x1a]	32924	1			T17	1		T63	1		T84	1
valid_sources[0x1b]	34447	1			T63	1		T143	55		T151	139
valid_sources[0x1c]	33303	1			T143	117		T151	174		T152	791
valid_sources[0x1d]	34100	1			T17	2		T63	1		T205	1
valid_sources[0x1e]	34161	1			T17	1		T406	1		T205	2
valid_sources[0x1f]	33755	1			T17	2		T63	1		T84	2
valid_sources[0x20]	34392	1			T17	1		T63	1		T84	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

22416385

1

T1

2486

T2

3898

T3

175

values[0x0]

all_enables

biggest_size

9825469

1

T1

6199

T2

4297

T3

173

values[0x1]

all_enables

biggest_size

245694

1

T17

16

T63

23

T84

16

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2888180	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

456202

1

T81

235

T82

232

T83

526

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1133813	1			T81	570		T82	538		T83	1322
values[0x0]	1079500	1			T81	550		T82	562		T83	1305
values[0x1]	1131069	1			T81	576		T82	592		T83	1318

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2235699	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1108683

1

T81

556

T82

541

T83

1264

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52075	1			T81	8		T82	17		T83	61
valid_sources[0x01]	52440	1			T81	36		T82	18		T83	61
valid_sources[0x02]	51773	1			T81	25		T82	10		T83	63
valid_sources[0x03]	53332	1			T81	5		T82	23		T83	64
valid_sources[0x04]	53024	1			T81	89		T82	15		T83	55
valid_sources[0x05]	51963	1			T81	23		T82	132		T83	59
valid_sources[0x06]	53259	1			T81	68		T82	17		T83	60
valid_sources[0x07]	52327	1			T81	51		T82	17		T83	52
valid_sources[0x08]	53021	1			T81	17		T82	7		T83	63
valid_sources[0x09]	51934	1			T81	23		T82	9		T83	72
valid_sources[0x0a]	52255	1			T82	85		T83	71		T86	37
valid_sources[0x0b]	52740	1			T81	40		T82	20		T83	64
valid_sources[0x0c]	51732	1			T81	62		T82	7		T83	69
valid_sources[0x0d]	52946	1			T81	13		T82	10		T83	71
valid_sources[0x0e]	51708	1			T82	37		T83	59		T86	45
valid_sources[0x0f]	52539	1			T81	2		T82	5		T83	63
valid_sources[0x10]	51238	1			T81	14		T82	3		T83	65
valid_sources[0x11]	52096	1			T81	19		T82	16		T83	56
valid_sources[0x12]	51095	1			T81	57		T82	7		T83	65
valid_sources[0x13]	52215	1			T81	28		T82	12		T83	69
valid_sources[0x14]	52523	1			T81	32		T82	12		T83	67
valid_sources[0x15]	52291	1			T81	57		T82	28		T83	58
valid_sources[0x16]	51157	1			T81	10		T82	143		T83	62
valid_sources[0x17]	52259	1			T81	32		T82	156		T83	52
valid_sources[0x18]	52835	1			T81	19		T82	16		T83	65
valid_sources[0x19]	50824	1			T81	6		T82	19		T83	61
valid_sources[0x1a]	50803	1			T81	34		T82	9		T83	53
valid_sources[0x1b]	52592	1			T81	42		T82	21		T83	72
valid_sources[0x1c]	51767	1			T81	87		T82	13		T83	76
valid_sources[0x1d]	52308	1			T81	58		T82	17		T83	54
valid_sources[0x1e]	52048	1			T81	23		T82	15		T83	62
valid_sources[0x1f]	51232	1			T82	20		T83	66		T85	5
valid_sources[0x20]	51807	1			T81	47		T82	16		T83	48

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

48010

1

T81

28

T82

21

T83

50

values[0x0]

all_enables

biggest_size

360442

1

T81

189

T82

180

T83

420

values[0x1]

all_enables

biggest_size

47750

1

T81

18

T82

31

T83

56

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3082079	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

500976

1

T81

219

T82

282

T83

575

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1226507	1			T81	582		T82	591		T83	1401
values[0x0]	1131690	1			T81	487		T82	619		T83	1330
values[0x1]	1224858	1			T81	552		T82	635		T83	1351

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2366640	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1216415

1

T81

545

T82

631

T83

1384

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	55814	1			T81	29		T82	23		T83	67
valid_sources[0x01]	56286	1			T81	29		T82	38		T83	51
valid_sources[0x02]	55585	1			T81	29		T82	32		T83	63
valid_sources[0x03]	57261	1			T81	30		T82	38		T83	56
valid_sources[0x04]	56824	1			T81	28		T82	19		T83	79
valid_sources[0x05]	56284	1			T81	21		T82	41		T83	61
valid_sources[0x06]	56117	1			T81	19		T82	38		T83	82
valid_sources[0x07]	56027	1			T81	33		T82	42		T83	55
valid_sources[0x08]	55464	1			T81	21		T82	26		T83	65
valid_sources[0x09]	55945	1			T81	11		T82	39		T83	60
valid_sources[0x0a]	56162	1			T81	14		T82	27		T83	70
valid_sources[0x0b]	55713	1			T81	16		T82	7		T83	62
valid_sources[0x0c]	55450	1			T81	16		T82	36		T83	40
valid_sources[0x0d]	56836	1			T81	18		T82	24		T83	65
valid_sources[0x0e]	56086	1			T81	24		T82	31		T83	74
valid_sources[0x0f]	56200	1			T81	37		T82	7		T83	65
valid_sources[0x10]	56296	1			T81	43		T82	32		T83	65
valid_sources[0x11]	55685	1			T81	29		T82	35		T83	74
valid_sources[0x12]	54884	1			T81	34		T82	39		T83	67
valid_sources[0x13]	56886	1			T81	31		T82	17		T83	46
valid_sources[0x14]	55835	1			T81	26		T82	16		T83	42
valid_sources[0x15]	56177	1			T81	13		T82	54		T83	60
valid_sources[0x16]	55805	1			T81	41		T82	40		T83	63
valid_sources[0x17]	55317	1			T81	20		T82	25		T83	53
valid_sources[0x18]	56125	1			T81	28		T82	12		T83	76
valid_sources[0x19]	55791	1			T81	36		T82	50		T83	50
valid_sources[0x1a]	54319	1			T81	24		T82	25		T83	47
valid_sources[0x1b]	55956	1			T81	21		T82	22		T83	72
valid_sources[0x1c]	55655	1			T81	32		T82	20		T83	76
valid_sources[0x1d]	55596	1			T81	31		T82	8		T83	58
valid_sources[0x1e]	56368	1			T81	25		T82	29		T83	44
valid_sources[0x1f]	56670	1			T81	20		T82	68		T83	61
valid_sources[0x20]	56925	1			T81	29		T82	3		T83	61

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

52551

1

T81

32

T82

28

T83

61

values[0x0]

all_enables

biggest_size

396142

1

T81

172

T82

221

T83

454

values[0x1]

all_enables

biggest_size

52283

1

T81

15

T82

33

T83

60

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2911588	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

460510

1

T81

214

T82

229

T83

557

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1139937	1			T81	525		T82	550		T83	1478
values[0x0]	1090571	1			T81	489		T82	547		T83	1346
values[0x1]	1141590	1			T81	551		T82	570		T83	1409

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2254471	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1117627

1

T81

535

T82

554

T83

1390

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52200	1			T81	27		T82	30		T83	59
valid_sources[0x01]	52127	1			T81	18		T82	17		T83	84
valid_sources[0x02]	53619	1			T81	25		T82	36		T83	91
valid_sources[0x03]	53543	1			T81	26		T82	26		T83	67
valid_sources[0x04]	53763	1			T81	17		T82	36		T83	72
valid_sources[0x05]	52555	1			T81	24		T82	24		T83	67
valid_sources[0x06]	52720	1			T81	18		T82	21		T83	59
valid_sources[0x07]	52727	1			T81	34		T82	22		T83	65
valid_sources[0x08]	52971	1			T81	24		T82	42		T83	68
valid_sources[0x09]	53580	1			T81	17		T82	27		T83	69
valid_sources[0x0a]	52774	1			T81	26		T82	27		T83	50
valid_sources[0x0b]	51629	1			T81	29		T82	27		T83	49
valid_sources[0x0c]	51270	1			T81	33		T82	26		T83	58
valid_sources[0x0d]	53054	1			T81	25		T82	25		T83	55
valid_sources[0x0e]	52684	1			T81	19		T82	20		T83	90
valid_sources[0x0f]	53262	1			T81	47		T82	15		T83	70
valid_sources[0x10]	52707	1			T81	24		T82	27		T83	65
valid_sources[0x11]	52100	1			T81	30		T82	30		T83	54
valid_sources[0x12]	52370	1			T81	31		T82	15		T83	72
valid_sources[0x13]	53201	1			T81	29		T82	28		T83	65
valid_sources[0x14]	52229	1			T81	13		T82	39		T83	76
valid_sources[0x15]	52936	1			T81	21		T82	35		T83	66
valid_sources[0x16]	52088	1			T81	20		T82	25		T83	86
valid_sources[0x17]	51525	1			T81	21		T82	20		T83	48
valid_sources[0x18]	52522	1			T81	36		T82	24		T83	31
valid_sources[0x19]	53350	1			T81	28		T82	27		T83	36
valid_sources[0x1a]	52338	1			T81	24		T82	27		T83	88
valid_sources[0x1b]	53765	1			T81	18		T82	20		T83	76
valid_sources[0x1c]	51558	1			T81	16		T82	18		T83	57
valid_sources[0x1d]	52542	1			T81	27		T82	22		T83	52
valid_sources[0x1e]	51914	1			T81	16		T82	24		T83	73
valid_sources[0x1f]	52316	1			T81	20		T82	25		T83	91
valid_sources[0x20]	52904	1			T81	26		T82	25		T83	68

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

48339

1

T81

21

T82

24

T83

58

values[0x0]

all_enables

biggest_size

364148

1

T81

169

T82

187

T83

436

values[0x1]

all_enables

biggest_size

48023

1

T81

24

T82

18

T83

63