Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427974082	41376848	0	0
DepthKnown_A	427974082	427877200	0	0
RvalidKnown_A	427974082	427877200	0	0
WreadyKnown_A	427974082	427877200	0	0
gen_passthru_fifo.paramCheckPass	910	910	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	41376848	0	0
T1	156619	21665	0	0
T2	154292	24901	0	0
T3	358492	3461	0	0
T16	168976	334265	0	0
T31	219172	28377	0	0
T32	242575	31482	0	0
T60	109341	11352	0	0
T61	142330	43799	0	0
T90	92071	10024	0	0
T91	360442	44144	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	427877200	0	0
T1	156619	156503	0	0
T2	154292	154230	0	0
T3	358492	358441	0	0
T16	168976	168971	0	0
T31	219172	219059	0	0
T32	242575	242462	0	0
T60	109341	109290	0	0
T61	142330	142324	0	0
T90	92071	92013	0	0
T91	360442	360387	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	427877200	0	0
T1	156619	156503	0	0
T2	154292	154230	0	0
T3	358492	358441	0	0
T16	168976	168971	0	0
T31	219172	219059	0	0
T32	242575	242462	0	0
T60	109341	109290	0	0
T61	142330	142324	0	0
T90	92071	92013	0	0
T91	360442	360387	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	427877200	0	0
T1	156619	156503	0	0
T2	154292	154230	0	0
T3	358492	358441	0	0
T16	168976	168971	0	0
T31	219172	219059	0	0
T32	242575	242462	0	0
T60	109341	109290	0	0
T61	142330	142324	0	0
T90	92071	92013	0	0
T91	360442	360387	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	910	910	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427974082	31922340	0	0
DepthKnown_A	427974082	427877200	0	0
RvalidKnown_A	427974082	427877200	0	0
WreadyKnown_A	427974082	427877200	0	0
gen_passthru_fifo.paramCheckPass	910	910	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	31922340	0	0
T1	156619	14079	0	0
T2	154292	17575	0	0
T3	358492	1867	0	0
T16	168976	264217	0	0
T31	219172	18881	0	0
T32	242575	21919	0	0
T60	109341	9126	0	0
T61	142330	39695	0	0
T90	92071	8149	0	0
T91	360442	34488	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	427877200	0	0
T1	156619	156503	0	0
T2	154292	154230	0	0
T3	358492	358441	0	0
T16	168976	168971	0	0
T31	219172	219059	0	0
T32	242575	242462	0	0
T60	109341	109290	0	0
T61	142330	142324	0	0
T90	92071	92013	0	0
T91	360442	360387	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	427877200	0	0
T1	156619	156503	0	0
T2	154292	154230	0	0
T3	358492	358441	0	0
T16	168976	168971	0	0
T31	219172	219059	0	0
T32	242575	242462	0	0
T60	109341	109290	0	0
T61	142330	142324	0	0
T90	92071	92013	0	0
T91	360442	360387	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	427877200	0	0
T1	156619	156503	0	0
T2	154292	154230	0	0
T3	358492	358441	0	0
T16	168976	168971	0	0
T31	219172	219059	0	0
T32	242575	242462	0	0
T60	109341	109290	0	0
T61	142330	142324	0	0
T90	92071	92013	0	0
T91	360442	360387	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	910	910	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427974082	33732037	0	0
DepthKnown_A	427974082	427877200	0	0
RvalidKnown_A	427974082	427877200	0	0
WreadyKnown_A	427974082	427877200	0	0
gen_passthru_fifo.paramCheckPass	910	910	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	33732037	0	0
T1	156619	9290	0	0
T2	154292	8935	0	0
T3	358492	459	0	0
T16	168976	287658	0	0
T31	219172	13652	0	0
T32	242575	15839	0	0
T60	109341	6453	0	0
T61	142330	33059	0	0
T90	92071	6282	0	0
T91	360442	43311	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	427877200	0	0
T1	156619	156503	0	0
T2	154292	154230	0	0
T3	358492	358441	0	0
T16	168976	168971	0	0
T31	219172	219059	0	0
T32	242575	242462	0	0
T60	109341	109290	0	0
T61	142330	142324	0	0
T90	92071	92013	0	0
T91	360442	360387	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	427877200	0	0
T1	156619	156503	0	0
T2	154292	154230	0	0
T3	358492	358441	0	0
T16	168976	168971	0	0
T31	219172	219059	0	0
T32	242575	242462	0	0
T60	109341	109290	0	0
T61	142330	142324	0	0
T90	92071	92013	0	0
T91	360442	360387	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	427877200	0	0
T1	156619	156503	0	0
T2	154292	154230	0	0
T3	358492	358441	0	0
T16	168976	168971	0	0
T31	219172	219059	0	0
T32	242575	242462	0	0
T60	109341	109290	0	0
T61	142330	142324	0	0
T90	92071	92013	0	0
T91	360442	360387	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	910	910	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427974082	32277479	0	0
DepthKnown_A	427974082	427877200	0	0
RvalidKnown_A	427974082	427877200	0	0
WreadyKnown_A	427974082	427877200	0	0
gen_passthru_fifo.paramCheckPass	910	910	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	32277479	0	0
T1	156619	8848	0	0
T2	154292	8661	0	0
T3	358492	351	0	0
T16	168976	286781	0	0
T31	219172	13260	0	0
T32	242575	15449	0	0
T60	109341	6313	0	0
T61	142330	32891	0	0
T90	92071	6170	0	0
T91	360442	40704	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	427877200	0	0
T1	156619	156503	0	0
T2	154292	154230	0	0
T3	358492	358441	0	0
T16	168976	168971	0	0
T31	219172	219059	0	0
T32	242575	242462	0	0
T60	109341	109290	0	0
T61	142330	142324	0	0
T90	92071	92013	0	0
T91	360442	360387	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	427877200	0	0
T1	156619	156503	0	0
T2	154292	154230	0	0
T3	358492	358441	0	0
T16	168976	168971	0	0
T31	219172	219059	0	0
T32	242575	242462	0	0
T60	109341	109290	0	0
T61	142330	142324	0	0
T90	92071	92013	0	0
T91	360442	360387	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	427877200	0	0
T1	156619	156503	0	0
T2	154292	154230	0	0
T3	358492	358441	0	0
T16	168976	168971	0	0
T31	219172	219059	0	0
T32	242575	242462	0	0
T60	109341	109290	0	0
T61	142330	142324	0	0
T90	92071	92013	0	0
T91	360442	360387	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	910	910	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	497763091	76343	0	0
DepthKnown_A	497763091	497654749	0	0
RvalidKnown_A	497763091	497654749	0	0
WreadyKnown_A	497763091	497654749	0	0
gen_passthru_fifo.paramCheckPass	2800	2800	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497763091	76343	0	0
T1	156619	71	0	0
T2	154292	26	0	0
T3	358492	8	0	0
T16	168976	20	0	0
T31	219172	151	0	0
T32	242575	151	0	0
T60	109341	19	0	0
T61	142330	29	0	0
T90	92071	13	0	0
T91	360442	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497763091	497654749	0	0
T1	156619	156503	0	0
T2	154292	154230	0	0
T3	358492	358441	0	0
T16	168976	168971	0	0
T31	219172	219059	0	0
T32	242575	242462	0	0
T60	109341	109290	0	0
T61	142330	142324	0	0
T90	92071	92013	0	0
T91	360442	360387	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497763091	497654749	0	0
T1	156619	156503	0	0
T2	154292	154230	0	0
T3	358492	358441	0	0
T16	168976	168971	0	0
T31	219172	219059	0	0
T32	242575	242462	0	0
T60	109341	109290	0	0
T61	142330	142324	0	0
T90	92071	92013	0	0
T91	360442	360387	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497763091	497654749	0	0
T1	156619	156503	0	0
T2	154292	154230	0	0
T3	358492	358441	0	0
T16	168976	168971	0	0
T31	219172	219059	0	0
T32	242575	242462	0	0
T60	109341	109290	0	0
T61	142330	142324	0	0
T90	92071	92013	0	0
T91	360442	360387	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2800	2800	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	497763091	77903	0	0
DepthKnown_A	497763091	497654749	0	0
RvalidKnown_A	497763091	497654749	0	0
WreadyKnown_A	497763091	497654749	0	0
gen_passthru_fifo.paramCheckPass	2800	2800	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497763091	77903	0	0
T1	156619	71	0	0
T2	154292	26	0	0
T3	358492	8	0	0
T16	168976	20	0	0
T31	219172	151	0	0
T32	242575	151	0	0
T60	109341	19	0	0
T61	142330	29	0	0
T90	92071	13	0	0
T91	360442	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497763091	497654749	0	0
T1	156619	156503	0	0
T2	154292	154230	0	0
T3	358492	358441	0	0
T16	168976	168971	0	0
T31	219172	219059	0	0
T32	242575	242462	0	0
T60	109341	109290	0	0
T61	142330	142324	0	0
T90	92071	92013	0	0
T91	360442	360387	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497763091	497654749	0	0
T1	156619	156503	0	0
T2	154292	154230	0	0
T3	358492	358441	0	0
T16	168976	168971	0	0
T31	219172	219059	0	0
T32	242575	242462	0	0
T60	109341	109290	0	0
T61	142330	142324	0	0
T90	92071	92013	0	0
T91	360442	360387	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497763091	497654749	0	0
T1	156619	156503	0	0
T2	154292	154230	0	0
T3	358492	358441	0	0
T16	168976	168971	0	0
T31	219172	219059	0	0
T32	242575	242462	0	0
T60	109341	109290	0	0
T61	142330	142324	0	0
T90	92071	92013	0	0
T91	360442	360387	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2800	2800	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	497763091	49174	0	0
DepthKnown_A	497763091	497654749	0	0
RvalidKnown_A	497763091	497654749	0	0
WreadyKnown_A	497763091	497654749	0	0
gen_passthru_fifo.paramCheckPass	2800	2800	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497763091	49174	0	0
T1	156619	69	0	0
T2	154292	23	0	0
T3	358492	8	0	0
T16	168976	19	0	0
T31	219172	95	0	0
T32	242575	95	0	0
T60	109341	18	0	0
T61	142330	28	0	0
T90	92071	12	0	0
T91	360442	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497763091	497654749	0	0
T1	156619	156503	0	0
T2	154292	154230	0	0
T3	358492	358441	0	0
T16	168976	168971	0	0
T31	219172	219059	0	0
T32	242575	242462	0	0
T60	109341	109290	0	0
T61	142330	142324	0	0
T90	92071	92013	0	0
T91	360442	360387	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497763091	497654749	0	0
T1	156619	156503	0	0
T2	154292	154230	0	0
T3	358492	358441	0	0
T16	168976	168971	0	0
T31	219172	219059	0	0
T32	242575	242462	0	0
T60	109341	109290	0	0
T61	142330	142324	0	0
T90	92071	92013	0	0
T91	360442	360387	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497763091	497654749	0	0
T1	156619	156503	0	0
T2	154292	154230	0	0
T3	358492	358441	0	0
T16	168976	168971	0	0
T31	219172	219059	0	0
T32	242575	242462	0	0
T60	109341	109290	0	0
T61	142330	142324	0	0
T90	92071	92013	0	0
T91	360442	360387	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2800	2800	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	497763091	49174	0	0
DepthKnown_A	497763091	497654749	0	0
RvalidKnown_A	497763091	497654749	0	0
WreadyKnown_A	497763091	497654749	0	0
gen_passthru_fifo.paramCheckPass	2800	2800	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497763091	49174	0	0
T1	156619	69	0	0
T2	154292	23	0	0
T3	358492	8	0	0
T16	168976	19	0	0
T31	219172	95	0	0
T32	242575	95	0	0
T60	109341	18	0	0
T61	142330	28	0	0
T90	92071	12	0	0
T91	360442	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497763091	497654749	0	0
T1	156619	156503	0	0
T2	154292	154230	0	0
T3	358492	358441	0	0
T16	168976	168971	0	0
T31	219172	219059	0	0
T32	242575	242462	0	0
T60	109341	109290	0	0
T61	142330	142324	0	0
T90	92071	92013	0	0
T91	360442	360387	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497763091	497654749	0	0
T1	156619	156503	0	0
T2	154292	154230	0	0
T3	358492	358441	0	0
T16	168976	168971	0	0
T31	219172	219059	0	0
T32	242575	242462	0	0
T60	109341	109290	0	0
T61	142330	142324	0	0
T90	92071	92013	0	0
T91	360442	360387	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497763091	497654749	0	0
T1	156619	156503	0	0
T2	154292	154230	0	0
T3	358492	358441	0	0
T16	168976	168971	0	0
T31	219172	219059	0	0
T32	242575	242462	0	0
T60	109341	109290	0	0
T61	142330	142324	0	0
T90	92071	92013	0	0
T91	360442	360387	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2800	2800	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	497763091	27169	0	0
DepthKnown_A	497763091	497654749	0	0
RvalidKnown_A	497763091	497654749	0	0
WreadyKnown_A	497763091	497654749	0	0
gen_passthru_fifo.paramCheckPass	2800	2800	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497763091	27169	0	0
T1	156619	2	0	0
T2	154292	3	0	0
T3	358492	0	0	0
T16	168976	1	0	0
T31	219172	56	0	0
T32	242575	56	0	0
T60	109341	1	0	0
T61	142330	1	0	0
T90	92071	1	0	0
T91	360442	1	0	0
T158	0	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497763091	497654749	0	0
T1	156619	156503	0	0
T2	154292	154230	0	0
T3	358492	358441	0	0
T16	168976	168971	0	0
T31	219172	219059	0	0
T32	242575	242462	0	0
T60	109341	109290	0	0
T61	142330	142324	0	0
T90	92071	92013	0	0
T91	360442	360387	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497763091	497654749	0	0
T1	156619	156503	0	0
T2	154292	154230	0	0
T3	358492	358441	0	0
T16	168976	168971	0	0
T31	219172	219059	0	0
T32	242575	242462	0	0
T60	109341	109290	0	0
T61	142330	142324	0	0
T90	92071	92013	0	0
T91	360442	360387	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497763091	497654749	0	0
T1	156619	156503	0	0
T2	154292	154230	0	0
T3	358492	358441	0	0
T16	168976	168971	0	0
T31	219172	219059	0	0
T32	242575	242462	0	0
T60	109341	109290	0	0
T61	142330	142324	0	0
T90	92071	92013	0	0
T91	360442	360387	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2800	2800	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	497763091	28729	0	0
DepthKnown_A	497763091	497654749	0	0
RvalidKnown_A	497763091	497654749	0	0
WreadyKnown_A	497763091	497654749	0	0
gen_passthru_fifo.paramCheckPass	2800	2800	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497763091	28729	0	0
T1	156619	2	0	0
T2	154292	3	0	0
T3	358492	0	0	0
T16	168976	1	0	0
T31	219172	56	0	0
T32	242575	56	0	0
T60	109341	1	0	0
T61	142330	1	0	0
T90	92071	1	0	0
T91	360442	1	0	0
T158	0	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497763091	497654749	0	0
T1	156619	156503	0	0
T2	154292	154230	0	0
T3	358492	358441	0	0
T16	168976	168971	0	0
T31	219172	219059	0	0
T32	242575	242462	0	0
T60	109341	109290	0	0
T61	142330	142324	0	0
T90	92071	92013	0	0
T91	360442	360387	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497763091	497654749	0	0
T1	156619	156503	0	0
T2	154292	154230	0	0
T3	358492	358441	0	0
T16	168976	168971	0	0
T31	219172	219059	0	0
T32	242575	242462	0	0
T60	109341	109290	0	0
T61	142330	142324	0	0
T90	92071	92013	0	0
T91	360442	360387	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497763091	497654749	0	0
T1	156619	156503	0	0
T2	154292	154230	0	0
T3	358492	358441	0	0
T16	168976	168971	0	0
T31	219172	219059	0	0
T32	242575	242462	0	0
T60	109341	109290	0	0
T61	142330	142324	0	0
T90	92071	92013	0	0
T91	360442	360387	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2800	2800	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0