Unified Coverage Report :: Module :: rv_core_ibex

Module : rv_core_ibex

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.07	94.12	89.29	98.77		100.00	68.18

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex	90.32	94.12	89.29	100.00		100.00	68.18

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.32	94.12	89.29	100.00		100.00	68.18

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.49	97.42	95.75	98.49		98.66	92.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.46	92.83		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
fifo_d	100.00	100.00	100.00			100.00	100.00
fifo_i	93.75	75.00	100.00			100.00	100.00
gen_alert_senders[0].u_alert_sender	100.00			100.00
gen_alert_senders[1].u_alert_sender	75.00			75.00
gen_alert_senders[2].u_alert_sender	100.00			100.00
gen_alert_senders[3].u_alert_sender	79.17			79.17
tl_adapter_host_d_ibex	91.79	95.35	81.82			90.00	100.00
tl_adapter_host_i_ibex	87.90	90.48	72.22			88.89	100.00
u_alert_nmi_sync	100.00	100.00				100.00
u_core	96.63			96.63
u_core_sleeping_buf	100.00	100.00
u_dbus_trans	96.36	100.00	92.59			100.00	92.86
u_edn_if	89.08	100.00	86.44			94.87	75.00
u_ibus_trans	96.36	100.00	92.59			100.00	92.86
u_intr_timer_sync	100.00	100.00				100.00
u_lc_sync	100.00	100.00				100.00	100.00
u_prim_buf_irq	100.00	100.00
u_prim_esc_receiver	100.00			100.00
u_prim_lc_sender	100.00	100.00				100.00
u_prim_sync_reqack_data	91.67	100.00	66.67			100.00	100.00
u_pwrmgr_sync	100.00	100.00				100.00	100.00
u_reg_cfg	99.20	98.69	98.55			99.58	100.00
u_sim_win_rsp	89.32	77.27	80.00			100.00	100.00
u_tlul_req_buf	100.00	100.00
u_tlul_rsp_buf	100.00	100.00
u_wdog_nmi_sync	100.00	100.00				100.00

Line Coverage for Module : rv_core_ibex

	Line No.	Total	Covered	Percent
TOTAL		85	80	94.12
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
ALWAYS	488	3	3	100.00
CONT_ASSIGN	508	1	1	100.00
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	510	1	1	100.00
CONT_ASSIGN	511	1	1	100.00
ALWAYS	514	8	8	100.00
CONT_ASSIGN	698	1	1	100.00
CONT_ASSIGN	698	1	1	100.00
CONT_ASSIGN	699	1	1	100.00
CONT_ASSIGN	699	1	1	100.00
CONT_ASSIGN	700	1	1	100.00
CONT_ASSIGN	700	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	705	1	1	100.00
CONT_ASSIGN	705	1	1	100.00
CONT_ASSIGN	706	1	1	100.00
CONT_ASSIGN	706	1	1	100.00
CONT_ASSIGN	713	1	1	100.00
CONT_ASSIGN	714	1	1	100.00
CONT_ASSIGN	715	1	1	100.00
CONT_ASSIGN	718	1	1	100.00
CONT_ASSIGN	720	1	1	100.00
CONT_ASSIGN	722	1	1	100.00
CONT_ASSIGN	724	1	1	100.00
CONT_ASSIGN	731	1	1	100.00
CONT_ASSIGN	733	1	1	100.00
CONT_ASSIGN	735	1	1	100.00
CONT_ASSIGN	737	1	1	100.00
CONT_ASSIGN	747	1	1	100.00
CONT_ASSIGN	748	1	0	0.00
CONT_ASSIGN	749	1	1	100.00
CONT_ASSIGN	750	1	1	100.00
CONT_ASSIGN	753	1	1	100.00
CONT_ASSIGN	756	1	0	0.00
ALWAYS	788	11	11	100.00
ALWAYS	804	7	7	100.00
CONT_ASSIGN	815	1	1	100.00
CONT_ASSIGN	834	1	1	100.00
CONT_ASSIGN	835	1	1	100.00
CONT_ASSIGN	836	1	1	100.00
CONT_ASSIGN	839	1	0	0.00
CONT_ASSIGN	843	0	0
CONT_ASSIGN	882	1	1	100.00
ALWAYS	941	0	0
CONT_ASSIGN	982	1	0	0.00
CONT_ASSIGN	984	1	0	0.00
CONT_ASSIGN	986	1	1	100.00
CONT_ASSIGN	988	1	1	100.00
CONT_ASSIGN	990	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
202	1	1
203	1	1
216	1	1
217	1	1
218	1	1
225	1	1
263	1	1
265	1	1
268	1	1
342	1	1
348	1	1
363	1	1
488	1	1
489	1	1
491	1	1
508	1	1
509	1	1
510	1	1
511	1	1
514	1	1
515	1	1
516	1	1
517	1	1
518	1	1
519	1	1
520	1	1
521	1	1
			MISSING_ELSE
698	2	2
699	2	2
700	2	2
704	2	2
705	2	2
706	2	2
713	1	1
714	1	1
715	1	1
718	1	1
720	1	1
722	1	1
724	1	1
731	1	1
733	1	1
735	1	1
737	1	1
747	1	1
748	0	1
749	1	1
750	1	1
753	1	1
756	0	1
788	1	1
789	1	1
790	1	1
792	1	1
793	1	1
794	1	1
795	1	1
796	1	1
797	1	1
798	1	1
799	1	1
			MISSING_ELSE
804	1	1
805	1	1
806	1	1
807	1	1
809	1	1
810	1	1
811	1	1
815	1	1
834	1	1
835	1	1
836	1	1
839	0	1
843		unreachable
882	1	1
941		unreachable
942		unreachable
943		unreachable
944		unreachable
			==> MISSING_ELSE
982	0	1
984	0	1
986	1	1
988	1	1
990	1	1

---

Cond Coverage for Module : rv_core_ibex

	Total	Covered	Percent
Conditions	28	25	89.29
Logical	28	25	89.29
Non-Logical	0	0
Event	0	0

 LINE       216
 EXPRESSION (ibus_intg_err | dbus_intg_err | alert_major_bus)
             ------1------   ------2------   -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T222,T180,T181
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       217
 EXPRESSION (alert_major_internal | double_fault)
             ----------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T179,T223,T224
1	0	Covered	T74,T225,T226

 LINE       348
 EXPRESSION (fatal_core_err ? Off : local_fetch_enable_q)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T179,T74,T225

 LINE       731
 EXPRESSION (reg2hw.alert_test.fatal_sw_err.q & reg2hw.alert_test.fatal_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T62,T74,T76
1	0	Covered	T1,T2,T3
1	1	Covered	T62,T64,T227

 LINE       733
 EXPRESSION (reg2hw.alert_test.recov_sw_err.q & reg2hw.alert_test.recov_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T62,T64,T227
1	0	Covered	T1,T2,T3
1	1	Covered	T62,T74,T76

 LINE       735
 EXPRESSION (reg2hw.alert_test.fatal_hw_err.q & reg2hw.alert_test.fatal_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T62,T74,T76
1	0	Covered	T1,T2,T3
1	1	Covered	T62,T64,T227

 LINE       737
 EXPRESSION (reg2hw.alert_test.recov_hw_err.q & reg2hw.alert_test.recov_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T62,T74,T76
1	0	Covered	T1,T2,T3
1	1	Covered	T62,T64,T227

 LINE       749
 EXPRESSION (intg_err | fatal_intg_err | fatal_core_err)
             ----1---   -------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T179,T74,T225
0	1	0	Covered	T222,T180,T181
1	0	0	Covered	T228,T229,T230

 LINE       796
 EXPRESSION (edn_req && edn_ack)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T31
1	1	Covered	T1,T2,T3

---

Toggle Coverage for Module : rv_core_ibex

	Total	Covered	Percent
Totals	121	117	96.69
Total Bits	1624	1604	98.77
Total Bits 0->1	812	802	98.77
Total Bits 1->0	812	802	98.77

Ports	121	117	96.69
Port Bits	1624	1604	98.77
Port Bits 0->1	812	802	98.77
Port Bits 1->0	812	802	98.77

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
clk_esc_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_esc_ni	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
rst_cpu_n_o	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
hart_id_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
boot_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_o.d_ready	Yes	Yes	T81,T83,T85	Yes	T81,T82,T83	OUTPUT
corei_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
corei_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T85,T86,T231	Yes	T85,T86,T231	OUTPUT
corei_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_data[31:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
corei_tl_h_o.a_mask[3:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
corei_tl_h_o.a_address[31:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
corei_tl_h_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
corei_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_opcode[2:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
corei_tl_h_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_error	Yes	Yes	T31,T32,T173	Yes	T31,T32,T173	INPUT
corei_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T31,T32,T173	Yes	T31,T32,T173	INPUT
corei_tl_h_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
corei_tl_h_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
corei_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_o.d_ready	Yes	Yes	T17,T63,T84	Yes	T17,T63,T84	OUTPUT
cored_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T232,T85,T231	Yes	T232,T85,T231	OUTPUT
cored_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_address[31:0]	Yes	Yes	T232,T81,T82	Yes	T232,T81,T82	OUTPUT
cored_tl_h_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_size[1:0]	Yes	Yes	T232,T81,T82	Yes	T232,T81,T82	OUTPUT
cored_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_error	Yes	Yes	T31,T32,T70	Yes	T31,T32,T70	INPUT
cored_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
cored_tl_h_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
cored_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
irq_software_i	Yes	Yes	T233,T234,T115	Yes	T233,T234,T115	INPUT
irq_timer_i	Yes	Yes	T60,T161,T162	Yes	T60,T161,T162	INPUT
irq_external_i	Yes	Yes	T2,T61,T31	Yes	T2,T61,T31	INPUT
esc_tx_i.esc_n	Yes	Yes	T2,T31,T32	Yes	T2,T31,T32	INPUT
esc_tx_i.esc_p	Yes	Yes	T2,T31,T32	Yes	T2,T31,T32	INPUT
esc_rx_o.resp_n	Yes	Yes	T2,T31,T32	Yes	T2,T31,T32	OUTPUT
esc_rx_o.resp_p	Yes	Yes	T2,T31,T32	Yes	T2,T31,T32	OUTPUT
nmi_wdog_i	Yes	Yes	T159,T235,T190	Yes	T159,T235,T190	INPUT
debug_req_i	Yes	Yes	T75,T236,T237	Yes	T75,T236,T237	INPUT
crash_dump_o.current.exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.last_data_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.next_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.current_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_valid	Unreachable	Unreachable		Unreachable		OUTPUT
lc_cpu_en_i[3:0]	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
pwrmgr_cpu_en_i[3:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T3	INPUT
pwrmgr_o.core_sleeping	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[7:0]	Yes	Yes	*T81,*T85,*T86	Yes	T81,T85,T86	INPUT
cfg_tl_d_i.a_address[15:8]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[20:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[24]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_source[5:0]	Yes	Yes	*T81,*T85,*T86	Yes	T81,T85,T86	INPUT
cfg_tl_d_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_size[1:0]	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
cfg_tl_d_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_opcode[2:0]	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
cfg_tl_d_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_error	Yes	Yes	T81,T82,T85	Yes	T81,T85,T86	OUTPUT
cfg_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T2,T31,T32	Yes	T2,T31,T32	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T60	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_data[31:0]	Yes	Yes	T2,T31,T32	Yes	T2,T31,T32	OUTPUT
cfg_tl_d_o.d_sink	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	OUTPUT
cfg_tl_d_o.d_source[5:0]	Yes	Yes	*T81,*T85,*T86	Yes	T81,T85,T86	OUTPUT
cfg_tl_d_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_size[1:0]	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	OUTPUT
cfg_tl_d_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T60	Yes	T1,T2,T60	OUTPUT
cfg_tl_d_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o.edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T61,T31,T32	Yes	T60,T16,T61	INPUT
edn_i.edn_fips	Yes	Yes	T129,T130,T238	Yes	T129,T130,T119	INPUT
edn_i.edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_otp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_otp_ni	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
icache_otp_key_o.req	Yes	Yes	T113,T182,T183	Yes	T113,T182,T183	OUTPUT
icache_otp_key_i.seed_valid	Yes	Yes	T1,T31,T32	Yes	T1,T2,T60	INPUT
icache_otp_key_i.nonce[127:0]	Yes	Yes	T1,T61,T90	Yes	T1,T60,T61	INPUT
icache_otp_key_i.key[127:0]	Yes	Yes	T2,T60,T16	Yes	T16,T31,T32	INPUT
icache_otp_key_i.ack	Yes	Yes	T113,T182,T183	Yes	T113,T182,T183	INPUT
fpga_info_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T87,T62,T88	Yes	T87,T62,T88	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T87,T62,T74	Yes	T87,T62,T74	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
alert_rx_i[2].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T179,T87,T222	Yes	T179,T87,T222	INPUT
alert_rx_i[2].ping_n	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
alert_rx_i[2].ping_p	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
alert_rx_i[3].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T87,T62,T88	Yes	T87,T62,T88	INPUT
alert_rx_i[3].ping_n	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
alert_rx_i[3].ping_p	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T87,T62,T88	Yes	T87,T62,T88	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T87,T62,T74	Yes	T87,T62,T74	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T179,T87,T222	Yes	T179,T87,T222	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T87,T62,T88	Yes	T87,T62,T88	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : rv_core_ibex

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	348	2	2	100.00
IF	488	2	2	100.00
IF	514	3	3	100.00
IF	792	3	3	100.00
IF	804	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	348	(fatal_core_err) ? 

Branches:

-1-	Status	Tests
1	Covered	T179,T74,T225
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	488	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	514	if ((!rst_ni))
-2-:	518	if (double_fault)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T179,T223,T224
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	792	if (reg2hw.rnd_data.re)
-2-:	796	if ((edn_req && edn_ack))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T31,T32
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	804	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : rv_core_ibex

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	15	68.18
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	15	68.18

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FpvSecCmIbexFetchEnable0_A	427974082	9	0	0
FpvSecCmIbexFetchEnable1_A	427974082	23005150	0	66
FpvSecCmIbexFetchEnable2_A	427974082	60199931	0	58
FpvSecCmIbexFetchEnable3Rev_A	427974082	363105281	0	1812
FpvSecCmIbexFetchEnable3_A	427974082	363107002	0	1733
FpvSecCmIbexInstrIntgErrCheck_A	427974082	150	0	0
FpvSecCmIbexLoadRespIntgErrCheck_A	427974082	583	0	0
FpvSecCmIbexLockstepResetCountAlertCheck_A	427974082	0	0	0
FpvSecCmIbexPcMismatchCheck_A	427974082	0	0	0
FpvSecCmIbexRfEccErrCheck_A	427974082	0	0	0
FpvSecCmIbexStoreRespIntgErrCheck_A	427974082	0	0	0
FpvSecCmRegWeOnehotCheck_A	427974082	6	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A	427974082	0	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A	427974082	0	0	0
FpvSecCmRvCoreRegWeOnehotCheck_A	427974082	0	0	0
g_instr_intg_err_assert_signals.AssertConnected_A	910	910	0	0
g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A	910	910	0	0
g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A	910	910	0	0
g_pc_mismatch_alert_o_assert_signals.AssertConnected_A	910	910	0	0
g_rf_ecc_err_comb_assert_signals.AssertConnected_A	910	910	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A	427974082	103	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A	427974082	187	0	0

FpvSecCmIbexFetchEnable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	9	0	0
T6	239358	0	0	0
T13	244069	0	0	0
T160	288743	0	0	0
T164	144695	0	0	0
T179	208423	1	0	0
T195	112991	0	0	0
T223	0	1	0	0
T224	0	1	0	0
T235	190546	0	0	0
T239	0	1	0	0
T240	0	1	0	0
T241	0	1	0	0
T242	0	1	0	0
T243	0	1	0	0
T244	0	1	0	0
T245	191079	0	0	0
T246	93350	0	0	0
T247	369542	0	0	0

FpvSecCmIbexFetchEnable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	23005150	0	66
T1	156619	19858	0	0
T2	154292	9927	0	0
T3	358492	9919	0	0
T16	168976	9931	0	0
T17	0	0	0	2
T31	219172	40620	0	0
T32	242575	40616	0	0
T43	0	0	0	2
T60	109341	9923	0	0
T61	142330	9931	0	0
T63	0	0	0	2
T67	0	0	0	2
T69	0	0	0	2
T84	0	0	0	2
T90	92071	9927	0	0
T91	360442	9919	0	0
T101	0	0	0	2
T178	0	0	0	2
T248	0	0	0	2
T249	0	0	0	2

FpvSecCmIbexFetchEnable2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	60199931	0	58
T1	156619	69555	0	0
T2	154292	38313	0	0
T3	358492	34775	0	0
T4	0	0	0	2
T7	0	0	0	2
T16	168976	34775	0	0
T17	0	0	0	2
T31	219172	69554	0	0
T32	242575	69555	0	0
T43	0	0	0	2
T60	109341	34775	0	0
T61	142330	34775	0	0
T63	0	0	0	2
T67	0	0	0	2
T84	0	0	0	2
T90	92071	34775	0	0
T91	360442	34775	0	0
T101	0	0	0	2
T178	0	0	0	2
T250	0	0	0	2

FpvSecCmIbexFetchEnable3Rev_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	363105281	0	1812
T1	156619	86942	0	2
T2	154292	115912	0	2
T3	358492	323663	0	2
T16	168976	165493	0	2
T31	219172	128733	0	2
T32	242575	152140	0	2
T60	109341	74512	0	2
T61	142330	138846	0	2
T90	92071	57235	0	2
T91	360442	325609	0	2

FpvSecCmIbexFetchEnable3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	363107002	0	1733
T1	156619	86944	0	2
T2	154292	115915	0	2
T3	358492	323664	0	2
T16	168976	165493	0	2
T31	219172	128735	0	2
T32	242575	152142	0	2
T60	109341	74513	0	2
T61	142330	138846	0	2
T90	92071	57236	0	2
T91	360442	325610	0	2

FpvSecCmIbexInstrIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	150	0	0
T12	250832	0	0	0
T55	105668	0	0	0
T251	263426	75	0	0
T252	0	75	0	0
T253	190508	0	0	0
T254	131584	0	0	0
T255	108730	0	0	0
T256	771666	0	0	0
T257	69458	0	0	0
T258	617702	0	0	0
T259	120066	0	0	0

FpvSecCmIbexLoadRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	583	0	0
T62	89584	0	0	0
T69	38300	0	0	0
T78	969545	0	0	0
T123	0	32	0	0
T124	0	31	0	0
T128	290892	0	0	0
T133	150663	0	0	0
T180	160179	32	0	0
T181	0	31	0	0
T222	319885	1	0	0
T250	275970	0	0	0
T260	0	1	0	0
T261	0	1	0	0
T262	0	99	0	0
T263	0	32	0	0
T264	0	32	0	0
T265	137871	0	0	0
T266	136604	0	0	0

FpvSecCmIbexLockstepResetCountAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	0	0	0

FpvSecCmIbexPcMismatchCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	0	0	0

FpvSecCmIbexRfEccErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	0	0	0

FpvSecCmIbexStoreRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	6	0	0
T77	45132	0	0	0
T181	213348	0	0	0
T194	335950	0	0	0
T228	130340	1	0	0
T229	0	1	0	0
T230	0	1	0	0
T267	0	1	0	0
T268	0	1	0	0
T269	0	1	0	0
T270	194258	0	0	0
T271	168925	0	0	0
T272	133693	0	0	0
T273	264399	0	0	0
T274	259314	0	0	0
T275	347043	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	0	0	0

FpvSecCmRvCoreRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	0	0	0

g_instr_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	910	910	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0

g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	910	910	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0

g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	910	910	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0

g_pc_mismatch_alert_o_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	910	910	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0

g_rf_ecc_err_comb_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	910	910	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	103	0	0
T49	211272	0	0	0
T78	969545	0	0	0
T113	94455	16	0	0
T114	42187	0	0	0
T133	150663	0	0	0
T180	160179	0	0	0
T182	0	21	0	0
T183	0	16	0	0
T222	319885	0	0	0
T250	275970	0	0	0
T265	137871	0	0	0
T266	136604	0	0	0
T276	0	8	0	0
T277	0	18	0	0
T278	0	24	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	187	0	0
T49	211272	0	0	0
T78	969545	0	0	0
T113	94455	42	0	0
T114	42187	0	0	0
T133	150663	0	0	0
T180	160179	0	0	0
T182	0	5	0	0
T183	0	42	0	0
T222	319885	0	0	0
T250	275970	0	0	0
T265	137871	0	0	0
T266	136604	0	0	0
T276	0	2	0	0
T277	0	42	0	0
T278	0	6	0	0
T279	0	16	0	0
T280	0	16	0	0
T281	0	16	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Line No.	Total	Covered	Percent
TOTAL		85	80	94.12
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
ALWAYS	488	3	3	100.00
CONT_ASSIGN	508	1	1	100.00
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	510	1	1	100.00
CONT_ASSIGN	511	1	1	100.00
ALWAYS	514	8	8	100.00
CONT_ASSIGN	698	1	1	100.00
CONT_ASSIGN	698	1	1	100.00
CONT_ASSIGN	699	1	1	100.00
CONT_ASSIGN	699	1	1	100.00
CONT_ASSIGN	700	1	1	100.00
CONT_ASSIGN	700	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	705	1	1	100.00
CONT_ASSIGN	705	1	1	100.00
CONT_ASSIGN	706	1	1	100.00
CONT_ASSIGN	706	1	1	100.00
CONT_ASSIGN	713	1	1	100.00
CONT_ASSIGN	714	1	1	100.00
CONT_ASSIGN	715	1	1	100.00
CONT_ASSIGN	718	1	1	100.00
CONT_ASSIGN	720	1	1	100.00
CONT_ASSIGN	722	1	1	100.00
CONT_ASSIGN	724	1	1	100.00
CONT_ASSIGN	731	1	1	100.00
CONT_ASSIGN	733	1	1	100.00
CONT_ASSIGN	735	1	1	100.00
CONT_ASSIGN	737	1	1	100.00
CONT_ASSIGN	747	1	1	100.00
CONT_ASSIGN	748	1	0	0.00
CONT_ASSIGN	749	1	1	100.00
CONT_ASSIGN	750	1	1	100.00
CONT_ASSIGN	753	1	1	100.00
CONT_ASSIGN	756	1	0	0.00
ALWAYS	788	11	11	100.00
ALWAYS	804	7	7	100.00
CONT_ASSIGN	815	1	1	100.00
CONT_ASSIGN	834	1	1	100.00
CONT_ASSIGN	835	1	1	100.00
CONT_ASSIGN	836	1	1	100.00
CONT_ASSIGN	839	1	0	0.00
CONT_ASSIGN	843	0	0
CONT_ASSIGN	882	1	1	100.00
ALWAYS	941	0	0
CONT_ASSIGN	982	1	0	0.00
CONT_ASSIGN	984	1	0	0.00
CONT_ASSIGN	986	1	1	100.00
CONT_ASSIGN	988	1	1	100.00
CONT_ASSIGN	990	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
202	1	1
203	1	1
216	1	1
217	1	1
218	1	1
225	1	1
263	1	1
265	1	1
268	1	1
342	1	1
348	1	1
363	1	1
488	1	1
489	1	1
491	1	1
508	1	1
509	1	1
510	1	1
511	1	1
514	1	1
515	1	1
516	1	1
517	1	1
518	1	1
519	1	1
520	1	1
521	1	1
			MISSING_ELSE
698	2	2
699	2	2
700	2	2
704	2	2
705	2	2
706	2	2
713	1	1
714	1	1
715	1	1
718	1	1
720	1	1
722	1	1
724	1	1
731	1	1
733	1	1
735	1	1
737	1	1
747	1	1
748	0	1
749	1	1
750	1	1
753	1	1
756	0	1
788	1	1
789	1	1
790	1	1
792	1	1
793	1	1
794	1	1
795	1	1
796	1	1
797	1	1
798	1	1
799	1	1
			MISSING_ELSE
804	1	1
805	1	1
806	1	1
807	1	1
809	1	1
810	1	1
811	1	1
815	1	1
834	1	1
835	1	1
836	1	1
839	0	1
843		unreachable
882	1	1
941		unreachable
942		unreachable
943		unreachable
944		unreachable
			==> MISSING_ELSE
982	0	1
984	0	1
986	1	1
988	1	1
990	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Covered	Percent
Conditions	28	25	89.29
Logical	28	25	89.29
Non-Logical	0	0
Event	0	0

 LINE       216
 EXPRESSION (ibus_intg_err | dbus_intg_err | alert_major_bus)
             ------1------   ------2------   -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T222,T180,T181
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       217
 EXPRESSION (alert_major_internal | double_fault)
             ----------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T179,T223,T224
1	0	Covered	T74,T225,T226

 LINE       348
 EXPRESSION (fatal_core_err ? Off : local_fetch_enable_q)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T179,T74,T225

 LINE       731
 EXPRESSION (reg2hw.alert_test.fatal_sw_err.q & reg2hw.alert_test.fatal_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T62,T74,T76
1	0	Covered	T1,T2,T3
1	1	Covered	T62,T64,T227

 LINE       733
 EXPRESSION (reg2hw.alert_test.recov_sw_err.q & reg2hw.alert_test.recov_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T62,T64,T227
1	0	Covered	T1,T2,T3
1	1	Covered	T62,T74,T76

 LINE       735
 EXPRESSION (reg2hw.alert_test.fatal_hw_err.q & reg2hw.alert_test.fatal_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T62,T74,T76
1	0	Covered	T1,T2,T3
1	1	Covered	T62,T64,T227

 LINE       737
 EXPRESSION (reg2hw.alert_test.recov_hw_err.q & reg2hw.alert_test.recov_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T62,T74,T76
1	0	Covered	T1,T2,T3
1	1	Covered	T62,T64,T227

 LINE       749
 EXPRESSION (intg_err | fatal_intg_err | fatal_core_err)
             ----1---   -------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T179,T74,T225
0	1	0	Covered	T222,T180,T181
1	0	0	Covered	T228,T229,T230

 LINE       796
 EXPRESSION (edn_req && edn_ack)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T31
1	1	Covered	T1,T2,T3

---

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Covered	Percent
Totals	117	117	100.00
Total Bits	1604	1604	100.00
Total Bits 0->1	802	802	100.00
Total Bits 1->0	802	802	100.00

Ports	117	117	100.00
Port Bits	1604	1604	100.00
Port Bits 0->1	802	802	100.00
Port Bits 1->0	802	802	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
clk_esc_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_esc_ni	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
rst_cpu_n_o	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.rf_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
hart_id_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
boot_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_o.d_ready	Yes	Yes	T81,T83,T85	Yes	T81,T82,T83	OUTPUT
corei_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
corei_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T85,T86,T231	Yes	T85,T86,T231	OUTPUT
corei_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_data[31:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
corei_tl_h_o.a_mask[3:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
corei_tl_h_o.a_address[31:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
corei_tl_h_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
corei_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_opcode[2:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
corei_tl_h_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_error	Yes	Yes	T31,T32,T173	Yes	T31,T32,T173	INPUT
corei_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T31,T32,T173	Yes	T31,T32,T173	INPUT
corei_tl_h_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
corei_tl_h_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
corei_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_o.d_ready	Yes	Yes	T17,T63,T84	Yes	T17,T63,T84	OUTPUT
cored_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T232,T85,T231	Yes	T232,T85,T231	OUTPUT
cored_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_address[31:0]	Yes	Yes	T232,T81,T82	Yes	T232,T81,T82	OUTPUT
cored_tl_h_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_size[1:0]	Yes	Yes	T232,T81,T82	Yes	T232,T81,T82	OUTPUT
cored_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_error	Yes	Yes	T31,T32,T70	Yes	T31,T32,T70	INPUT
cored_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
cored_tl_h_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
cored_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
irq_software_i	Yes	Yes	T233,T234,T115	Yes	T233,T234,T115	INPUT
irq_timer_i	Yes	Yes	T60,T161,T162	Yes	T60,T161,T162	INPUT
irq_external_i	Yes	Yes	T2,T61,T31	Yes	T2,T61,T31	INPUT
esc_tx_i.esc_n	Yes	Yes	T2,T31,T32	Yes	T2,T31,T32	INPUT
esc_tx_i.esc_p	Yes	Yes	T2,T31,T32	Yes	T2,T31,T32	INPUT
esc_rx_o.resp_n	Yes	Yes	T2,T31,T32	Yes	T2,T31,T32	OUTPUT
esc_rx_o.resp_p	Yes	Yes	T2,T31,T32	Yes	T2,T31,T32	OUTPUT
nmi_wdog_i	Yes	Yes	T159,T235,T190	Yes	T159,T235,T190	INPUT
debug_req_i	Yes	Yes	T75,T236,T237	Yes	T75,T236,T237	INPUT
crash_dump_o.current.exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.last_data_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.next_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.current_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_valid	Unreachable	Unreachable		Unreachable		OUTPUT
lc_cpu_en_i[3:0]	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
pwrmgr_cpu_en_i[3:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T3	INPUT
pwrmgr_o.core_sleeping	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[7:0]	Yes	Yes	*T81,*T85,*T86	Yes	T81,T85,T86	INPUT
cfg_tl_d_i.a_address[15:8]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[20:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[24]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_source[5:0]	Yes	Yes	*T81,*T85,*T86	Yes	T81,T85,T86	INPUT
cfg_tl_d_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_size[1:0]	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
cfg_tl_d_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_opcode[2:0]	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
cfg_tl_d_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_error	Yes	Yes	T81,T82,T85	Yes	T81,T85,T86	OUTPUT
cfg_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T2,T31,T32	Yes	T2,T31,T32	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T60	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_data[31:0]	Yes	Yes	T2,T31,T32	Yes	T2,T31,T32	OUTPUT
cfg_tl_d_o.d_sink	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	OUTPUT
cfg_tl_d_o.d_source[5:0]	Yes	Yes	*T81,*T85,*T86	Yes	T81,T85,T86	OUTPUT
cfg_tl_d_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_size[1:0]	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	OUTPUT
cfg_tl_d_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T60	Yes	T1,T2,T60	OUTPUT
cfg_tl_d_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o.edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T61,T31,T32	Yes	T60,T16,T61	INPUT
edn_i.edn_fips	Yes	Yes	T129,T130,T238	Yes	T129,T130,T119	INPUT
edn_i.edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_otp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_otp_ni	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
icache_otp_key_o.req	Yes	Yes	T113,T182,T183	Yes	T113,T182,T183	OUTPUT
icache_otp_key_i.seed_valid	Yes	Yes	T1,T31,T32	Yes	T1,T2,T60	INPUT
icache_otp_key_i.nonce[127:0]	Yes	Yes	T1,T61,T90	Yes	T1,T60,T61	INPUT
icache_otp_key_i.key[127:0]	Yes	Yes	T2,T60,T16	Yes	T16,T31,T32	INPUT
icache_otp_key_i.ack	Yes	Yes	T113,T182,T183	Yes	T113,T182,T183	INPUT
fpga_info_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T87,T62,T88	Yes	T87,T62,T88	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T87,T62,T74	Yes	T87,T62,T74	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
alert_rx_i[2].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T179,T87,T222	Yes	T179,T87,T222	INPUT
alert_rx_i[2].ping_n	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
alert_rx_i[2].ping_p	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
alert_rx_i[3].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T87,T62,T88	Yes	T87,T62,T88	INPUT
alert_rx_i[3].ping_n	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
alert_rx_i[3].ping_p	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T87,T62,T88	Yes	T87,T62,T88	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T87,T62,T74	Yes	T87,T62,T74	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T179,T87,T222	Yes	T179,T87,T222	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T87,T62,T88	Yes	T87,T62,T88	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	348	2	2	100.00
IF	488	2	2	100.00
IF	514	3	3	100.00
IF	792	3	3	100.00
IF	804	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	348	(fatal_core_err) ? 

Branches:

-1-	Status	Tests
1	Covered	T179,T74,T225
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	488	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	514	if ((!rst_ni))
-2-:	518	if (double_fault)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T179,T223,T224
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	792	if (reg2hw.rnd_data.re)
-2-:	796	if ((edn_req && edn_ack))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T31,T32
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	804	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	15	68.18
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	15	68.18

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FpvSecCmIbexFetchEnable0_A	427974082	9	0	0
FpvSecCmIbexFetchEnable1_A	427974082	23005150	0	66
FpvSecCmIbexFetchEnable2_A	427974082	60199931	0	58
FpvSecCmIbexFetchEnable3Rev_A	427974082	363105281	0	1812
FpvSecCmIbexFetchEnable3_A	427974082	363107002	0	1733
FpvSecCmIbexInstrIntgErrCheck_A	427974082	150	0	0
FpvSecCmIbexLoadRespIntgErrCheck_A	427974082	583	0	0
FpvSecCmIbexLockstepResetCountAlertCheck_A	427974082	0	0	0
FpvSecCmIbexPcMismatchCheck_A	427974082	0	0	0
FpvSecCmIbexRfEccErrCheck_A	427974082	0	0	0
FpvSecCmIbexStoreRespIntgErrCheck_A	427974082	0	0	0
FpvSecCmRegWeOnehotCheck_A	427974082	6	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A	427974082	0	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A	427974082	0	0	0
FpvSecCmRvCoreRegWeOnehotCheck_A	427974082	0	0	0
g_instr_intg_err_assert_signals.AssertConnected_A	910	910	0	0
g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A	910	910	0	0
g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A	910	910	0	0
g_pc_mismatch_alert_o_assert_signals.AssertConnected_A	910	910	0	0
g_rf_ecc_err_comb_assert_signals.AssertConnected_A	910	910	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A	427974082	103	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A	427974082	187	0	0

FpvSecCmIbexFetchEnable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	9	0	0
T6	239358	0	0	0
T13	244069	0	0	0
T160	288743	0	0	0
T164	144695	0	0	0
T179	208423	1	0	0
T195	112991	0	0	0
T223	0	1	0	0
T224	0	1	0	0
T235	190546	0	0	0
T239	0	1	0	0
T240	0	1	0	0
T241	0	1	0	0
T242	0	1	0	0
T243	0	1	0	0
T244	0	1	0	0
T245	191079	0	0	0
T246	93350	0	0	0
T247	369542	0	0	0

FpvSecCmIbexFetchEnable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	23005150	0	66
T1	156619	19858	0	0
T2	154292	9927	0	0
T3	358492	9919	0	0
T16	168976	9931	0	0
T17	0	0	0	2
T31	219172	40620	0	0
T32	242575	40616	0	0
T43	0	0	0	2
T60	109341	9923	0	0
T61	142330	9931	0	0
T63	0	0	0	2
T67	0	0	0	2
T69	0	0	0	2
T84	0	0	0	2
T90	92071	9927	0	0
T91	360442	9919	0	0
T101	0	0	0	2
T178	0	0	0	2
T248	0	0	0	2
T249	0	0	0	2

FpvSecCmIbexFetchEnable2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	60199931	0	58
T1	156619	69555	0	0
T2	154292	38313	0	0
T3	358492	34775	0	0
T4	0	0	0	2
T7	0	0	0	2
T16	168976	34775	0	0
T17	0	0	0	2
T31	219172	69554	0	0
T32	242575	69555	0	0
T43	0	0	0	2
T60	109341	34775	0	0
T61	142330	34775	0	0
T63	0	0	0	2
T67	0	0	0	2
T84	0	0	0	2
T90	92071	34775	0	0
T91	360442	34775	0	0
T101	0	0	0	2
T178	0	0	0	2
T250	0	0	0	2

FpvSecCmIbexFetchEnable3Rev_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	363105281	0	1812
T1	156619	86942	0	2
T2	154292	115912	0	2
T3	358492	323663	0	2
T16	168976	165493	0	2
T31	219172	128733	0	2
T32	242575	152140	0	2
T60	109341	74512	0	2
T61	142330	138846	0	2
T90	92071	57235	0	2
T91	360442	325609	0	2

FpvSecCmIbexFetchEnable3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	363107002	0	1733
T1	156619	86944	0	2
T2	154292	115915	0	2
T3	358492	323664	0	2
T16	168976	165493	0	2
T31	219172	128735	0	2
T32	242575	152142	0	2
T60	109341	74513	0	2
T61	142330	138846	0	2
T90	92071	57236	0	2
T91	360442	325610	0	2

FpvSecCmIbexInstrIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	150	0	0
T12	250832	0	0	0
T55	105668	0	0	0
T251	263426	75	0	0
T252	0	75	0	0
T253	190508	0	0	0
T254	131584	0	0	0
T255	108730	0	0	0
T256	771666	0	0	0
T257	69458	0	0	0
T258	617702	0	0	0
T259	120066	0	0	0

FpvSecCmIbexLoadRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	583	0	0
T62	89584	0	0	0
T69	38300	0	0	0
T78	969545	0	0	0
T123	0	32	0	0
T124	0	31	0	0
T128	290892	0	0	0
T133	150663	0	0	0
T180	160179	32	0	0
T181	0	31	0	0
T222	319885	1	0	0
T250	275970	0	0	0
T260	0	1	0	0
T261	0	1	0	0
T262	0	99	0	0
T263	0	32	0	0
T264	0	32	0	0
T265	137871	0	0	0
T266	136604	0	0	0

FpvSecCmIbexLockstepResetCountAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	0	0	0

FpvSecCmIbexPcMismatchCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	0	0	0

FpvSecCmIbexRfEccErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	0	0	0

FpvSecCmIbexStoreRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	6	0	0
T77	45132	0	0	0
T181	213348	0	0	0
T194	335950	0	0	0
T228	130340	1	0	0
T229	0	1	0	0
T230	0	1	0	0
T267	0	1	0	0
T268	0	1	0	0
T269	0	1	0	0
T270	194258	0	0	0
T271	168925	0	0	0
T272	133693	0	0	0
T273	264399	0	0	0
T274	259314	0	0	0
T275	347043	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	0	0	0

FpvSecCmRvCoreRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	0	0	0

g_instr_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	910	910	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0

g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	910	910	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0

g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	910	910	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0

g_pc_mismatch_alert_o_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	910	910	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0

g_rf_ecc_err_comb_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	910	910	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	103	0	0
T49	211272	0	0	0
T78	969545	0	0	0
T113	94455	16	0	0
T114	42187	0	0	0
T133	150663	0	0	0
T180	160179	0	0	0
T182	0	21	0	0
T183	0	16	0	0
T222	319885	0	0	0
T250	275970	0	0	0
T265	137871	0	0	0
T266	136604	0	0	0
T276	0	8	0	0
T277	0	18	0	0
T278	0	24	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	187	0	0
T49	211272	0	0	0
T78	969545	0	0	0
T113	94455	42	0	0
T114	42187	0	0	0
T133	150663	0	0	0
T180	160179	0	0	0
T182	0	5	0	0
T183	0	42	0	0
T222	319885	0	0	0
T250	275970	0	0	0
T265	137871	0	0	0
T266	136604	0	0	0
T276	0	2	0	0
T277	0	42	0	0
T278	0	6	0	0
T279	0	16	0	0
T280	0	16	0	0
T281	0	16	0	0