Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.46	92.83		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T81,T83,T85	Yes	T81,T82,T83	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T85,T86,T231	Yes	T85,T86,T231	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T31,T32,T173	Yes	T31,T32,T173	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T31,T32,T173	Yes	T31,T32,T173	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T17,T63,T84	Yes	T17,T63,T84	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T232,T85,T231	Yes	T232,T85,T231	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T232,T81,T82	Yes	T232,T81,T82	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T31,T32,T70	Yes	T31,T32,T70	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T3,T17,T75	Yes	T3,T17,T75	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T3,T31	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T3,T17,T75	Yes	T3,T17,T75	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T3,T17,T75	Yes	T3,T17,T75	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T1,T3,T31	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T3,T17,T75	Yes	T3,T17,T75	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T3,T17,T63	Yes	T3,T17,T63	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T3,T17,T75	Yes	T3,T17,T75	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T3,*T17,*T75	Yes	T3,T17,T75	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T3,T17,T75	Yes	T3,T17,T75	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T81,T83,T85	Yes	T81,T82,T83	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T81,*T83,*T85	Yes	T81,T83,T85	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T75,T236,T237	Yes	T75,T236,T237	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T75,T236,T237	Yes	T75,T236,T237	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T75,T236,T237	Yes	T75,T236,T237	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T75,T236,T237	Yes	T75,T236,T237	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T75,T236,T237	Yes	T75,T236,T237	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T75,*T236,*T237	Yes	T75,T236,T237	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T75,T236,T237	Yes	T75,T236,T237	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T31,T32	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T75,T236,T237	Yes	T75,T236,T237	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T75,T236,T237	Yes	T75,T236,T237	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T31,T32	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T75,*T236,*T237	Yes	T75,T236,T237	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T31,T32	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T75,T236,T237	Yes	T75,T236,T237	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T46,T174,T47	Yes	T46,T174,T47	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T81,*T82,*T83	Yes	T81,T82,T83	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T1,T90,T31	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T62,T64,T227	Yes	T62,T64,T227	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T90,T177,T4	Yes	T90,T177,T4	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T90,T177,T4	Yes	T90,T177,T4	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T62,T64,T227	Yes	T62,T64,T227	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T90,T177,T4	Yes	T90,T177,T4	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T81,*T83,*T85	Yes	T81,T83,T85	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T90,T177,T4	Yes	T90,T177,T4	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T90,T177,T4	Yes	T90,T177,T4	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T90,T4,T250	Yes	T90,T4,T250	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T81,T83,T85	Yes	T62,T64,T227	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T90,T4,T250	Yes	T90,T4,T250	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	T81,*T83,*T85	Yes	T81,T83,T85	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T177,*T4,*T250	Yes	T90,T177,T4	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T90,T177,T4	Yes	T90,T177,T4	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T17,*T75,*T63	Yes	T17,T75,T63	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T17,T63,T84	Yes	T17,T63,T84	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	Yes	Yes	T70,T173,T177	Yes	T70,T173,T177	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T17,*T75,*T63	Yes	T17,T75,T63	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T62,T10,T367	Yes	T62,T10,T367	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T62,T10,T161	Yes	T62,T10,T161	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T62,T10,T367	Yes	T62,T10,T367	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T62,T10,T367	Yes	T62,T10,T367	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T62,T10,T161	Yes	T62,T10,T161	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T62,T10,T367	Yes	T62,T10,T367	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T81,*T85,*T86	Yes	T81,T85,T86	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T11,T12,T204	Yes	T11,T12,T204	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T62,T10,T367	Yes	T62,T10,T367	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T62,T10,T367	Yes	T62,T10,T367	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T81,T82,T85	Yes	T81,T85,T86	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T10,T161,T11	Yes	T10,T161,T11	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T10,T367,T161	Yes	T62,T10,T367	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T10,T161,T11	Yes	T10,T161,T11	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T81,*T85,*T86	Yes	T81,T85,T86	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T81,T82,T85	Yes	T81,T85,T86	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T10,*T367,*T161	Yes	T10,T367,T161	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T62,T10,T367	Yes	T62,T10,T367	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T62,T367,T33	Yes	T62,T367,T33	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T62,T33,T161	Yes	T62,T33,T161	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T62,T367,T33	Yes	T62,T367,T33	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T62,T367,T33	Yes	T62,T367,T33	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T62,T33,T161	Yes	T62,T33,T161	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T62,T367,T33	Yes	T62,T367,T33	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T81,*T85,*T86	Yes	T81,T85,T86	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T62,T367,T33	Yes	T62,T367,T33	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T62,T367,T33	Yes	T62,T367,T33	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T33,T161,T162	Yes	T33,T161,T162	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T367,T33,T161	Yes	T62,T367,T33	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T33,T161,T162	Yes	T33,T161,T162	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T81,*T85,*T86	Yes	T81,T85,T86	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T367,*T33,*T161	Yes	T367,T33,T161	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T62,T367,T33	Yes	T62,T367,T33	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T17,*T81,*T85	Yes	T17,T81,T85	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	INPUT
tl_usbdev_i.d_error	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T16,T17,T365	Yes	T16,T17,T365	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T16,T17,T365	Yes	T16,T17,T365	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T81,T83,T85	Yes	T81,T82,T85	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T17,*T81,*T85	Yes	T17,T81,T85	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T16,*T17,*T18	Yes	T16,T17,T18	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T60	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T60	Yes	T1,T2,T60	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T60	Yes	T1,T2,T60	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T60	Yes	T1,T2,T60	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T60	Yes	T1,T2,T60	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T60	Yes	T1,T2,T60	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T17,*T63,*T205	Yes	T17,T63,T205	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T60	Yes	T1,T2,T60	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T60	Yes	T1,T2,T60	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T31,T32	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T60	Yes	T1,T2,T60	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T60	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T60	Yes	T1,T91,T31	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T17,*T63,*T205	Yes	T17,T63,T205	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T60	Yes	T1,T2,T60	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T60	Yes	T1,T2,T60	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T17,T63,T205	Yes	T17,T63,T205	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T17,T63,T205	Yes	T17,T63,T205	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T17,T63,T205	Yes	T17,T63,T205	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T17,T63,T205	Yes	T17,T63,T205	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T17,T63,T205	Yes	T17,T63,T205	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T17,*T63,*T205	Yes	T17,T63,T205	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T17,T63,T205	Yes	T17,T63,T205	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T17,T63,T205	Yes	T17,T63,T205	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T81,T85,T86	Yes	T81,T82,T85	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T17,T63,T205	Yes	T17,T63,T205	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T17,T63,T205	Yes	T17,T63,T205	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T17,T63,T205	Yes	T17,T63,T205	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T81,T85,T86	Yes	T81,T83,T85	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T17,*T63,*T205	Yes	T17,T63,T205	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T81,T82,T85	Yes	T81,T85,T86	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T17,*T63,*T205	Yes	T17,T63,T205	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T17,T63,T205	Yes	T17,T63,T205	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T1,T2,T60	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T60	Yes	T1,T2,T60	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T60	Yes	T1,T2,T60	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T60	Yes	T1,T2,T60	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T1,T2,T60	Yes	T1,T2,T60	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T1,T2,T60	Yes	T1,T2,T60	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T60	Yes	T1,T2,T60	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T1,T2,T60	Yes	T1,T2,T60	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T60	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T31,T32	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T60	Yes	T1,T2,T60	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T60	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T60	Yes	T1,T2,T60	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T60	Yes	T1,T2,T60	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T81,*T82,*T83	Yes	T81,T82,T83	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T1,T2,T60	Yes	T1,T2,T60	INPUT
tl_hmac_o.d_ready	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T17,T108,T62	Yes	T17,T108,T62	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T17,T108,T62	Yes	T17,T108,T62	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T17,T108,T62	Yes	T17,T108,T62	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T17,T108,T62	Yes	T17,T108,T62	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T17,T108,T62	Yes	T17,T108,T62	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T17,*T63,*T205	Yes	T17,T63,T205	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T108,T304,T334	Yes	T108,T304,T334	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T17,T108,T62	Yes	T17,T108,T62	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T17,T108,T62	Yes	T17,T108,T62	INPUT
tl_hmac_i.d_error	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T17,T108,T225	Yes	T17,T108,T225	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T17,T108,T225	Yes	T17,T108,T225	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T17,T108,T62	Yes	T17,T108,T46	INPUT
tl_hmac_i.d_sink	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T17,*T63,*T205	Yes	T17,T63,T205	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T17,*T108,*T62	Yes	T17,T108,T46	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T17,T108,T62	Yes	T17,T108,T62	INPUT
tl_kmac_o.d_ready	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T246,T17,T62	Yes	T246,T17,T62	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T32,T246	Yes	T1,T32,T246	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T1,T32,T246	Yes	T1,T32,T246	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T246,T17,T62	Yes	T246,T17,T62	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T1,T32,T246	Yes	T1,T32,T246	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T17,*T63,*T205	Yes	T17,T63,T205	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T246,T292,T412	Yes	T246,T292,T412	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T1,T32,T246	Yes	T1,T32,T246	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T1,T32,T246	Yes	T1,T32,T246	INPUT
tl_kmac_i.d_error	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T1,T246,T17	Yes	T1,T32,T246	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T32,T246	Yes	T1,T32,T246	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T1,T32,T246	Yes	T32,T246,T17	INPUT
tl_kmac_i.d_sink	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T17,*T63,*T205	Yes	T17,T63,T205	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T1,*T246,*T17	Yes	T246,T17,T292	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T1,T32,T246	Yes	T1,T32,T246	INPUT
tl_aes_o.d_ready	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T1,T62,T636	Yes	T1,T62,T636	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T62,T636	Yes	T1,T62,T636	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T1,T62,T225	Yes	T1,T62,T225	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T1,T62,T636	Yes	T1,T62,T636	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T1,T62,T225	Yes	T1,T62,T225	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T81,*T82,*T85	Yes	T81,T82,T85	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T1,T62,T225	Yes	T1,T62,T225	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T1,T62,T225	Yes	T1,T62,T225	INPUT
tl_aes_i.d_error	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T1,T225,T636	Yes	T1,T225,T636	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T636,T129	Yes	T1,T62,T636	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T1,T225,T636	Yes	T1,T62,T225	INPUT
tl_aes_i.d_sink	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T81,*T82,*T85	Yes	T81,T82,T85	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T1,*T225,*T636	Yes	T1,T225,T636	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T1,T62,T225	Yes	T1,T62,T225	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T17,*T63,*T205	Yes	T17,T63,T205	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T81,T85,T86	Yes	T81,T82,T85	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T61,T132,T17	Yes	T61,T132,T17	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T61,T31	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T81,T82,T85	Yes	T81,T83,T85	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T17,*T63,*T205	Yes	T17,T63,T205	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T81,T83,T85	Yes	T81,T85,T86	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T61,*T132,*T17	Yes	T61,T132,T17	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T61,T17,T133	Yes	T61,T17,T133	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T17,*T63,*T205	Yes	T17,T63,T205	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_error	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T61,T17,T133	Yes	T61,T17,T133	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T61,T31	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_sink	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T17,*T63,*T205	Yes	T17,T63,T205	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T61,*T17,*T133	Yes	T61,T17,T133	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T61,T17,T133	Yes	T61,T17,T133	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T61,T17,T133	Yes	T61,T17,T133	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T17,*T63,*T205	Yes	T17,T63,T205	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_error	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T61,T17,T133	Yes	T61,T17,T133	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T61,T31	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T1,T61,T31	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_sink	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T17,*T63,*T205	Yes	T17,T63,T205	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T61,*T17,*T133	Yes	T61,T17,T133	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_o.d_ready	Yes	Yes	T1,T61,T31	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T61,T17,T133	Yes	T61,T17,T133	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T61,T17,T133	Yes	T61,T17,T133	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T61,T17,T133	Yes	T61,T17,T133	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T61,T17,T133	Yes	T61,T17,T133	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T61,T17,T133	Yes	T61,T17,T133	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T17,*T63,*T205	Yes	T17,T63,T205	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T61,T17,T133	Yes	T61,T17,T133	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T61,T17,T133	Yes	T61,T17,T133	INPUT
tl_edn1_i.d_error	Yes	Yes	T81,T85,T86	Yes	T81,T82,T85	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T61,T17,T133	Yes	T61,T17,T133	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T61,T17,T133	Yes	T61,T17,T133	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T61,T17,T133	Yes	T61,T17,T133	INPUT
tl_edn1_i.d_sink	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T17,*T63,*T205	Yes	T17,T63,T205	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T81,T85,T86	Yes	T81,T82,T85	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T61,*T17,*T133	Yes	T61,T17,T133	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T61,T17,T133	Yes	T61,T17,T133	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T1,T2,T61	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T2,T61,T31	Yes	T2,T61,T31	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T61,T31	Yes	T2,T61,T31	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T2,T61,T31	Yes	T2,T61,T31	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T2,T61,T31	Yes	T2,T61,T31	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T2,T61,T31	Yes	T2,T61,T31	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T81,*T83,*T85	Yes	T81,T83,T85	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T2,T61,T31	Yes	T2,T61,T31	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T2,T61,T31	Yes	T2,T61,T31	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T61,T31,T32	Yes	T61,T31,T32	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T61,T31	Yes	T2,T61,T31	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T2,T61,T31	Yes	T2,T61,T31	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T81,*T83,*T85	Yes	T81,T83,T85	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T2,*T61,*T31	Yes	T2,T61,T31	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T2,T61,T31	Yes	T2,T61,T31	INPUT
tl_otbn_o.d_ready	Yes	Yes	T1,T61,T31	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T61,T133,T62	Yes	T61,T133,T62	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T61,T133,T62	Yes	T61,T133,T62	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T61,T133,T62	Yes	T61,T133,T62	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T61,T133,T62	Yes	T61,T133,T62	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T61,T133,T62	Yes	T61,T133,T62	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T63,*T84,*T232	Yes	T63,T84,T232	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T61,T133,T62	Yes	T61,T133,T62	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T61,T133,T62	Yes	T61,T133,T62	INPUT
tl_otbn_i.d_error	Yes	Yes	T81,T85,T86	Yes	T81,T83,T85	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T61,T133,T155	Yes	T61,T133,T155	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T61,T133,T155	Yes	T61,T133,T155	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T61,T133,T62	Yes	T61,T133,T155	INPUT
tl_otbn_i.d_sink	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T63,*T84,*T232	Yes	T63,T84,T232	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T81,T85,T86	Yes	T81,T83,T85	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T61,*T133,*T62	Yes	T61,T133,T155	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T61,T133,T62	Yes	T61,T133,T62	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T1,T17,T122	Yes	T1,T17,T122	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T17,T122	Yes	T1,T17,T122	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T1,T17,T122	Yes	T1,T17,T122	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T1,T17,T122	Yes	T1,T17,T122	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T1,T17,T122	Yes	T1,T17,T122	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T17,*T63,*T205	Yes	T17,T63,T205	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T1,T17,T122	Yes	T1,T17,T122	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T1,T17,T122	Yes	T1,T17,T122	INPUT
tl_keymgr_i.d_error	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T1,T17,T122	Yes	T1,T17,T122	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T17,T122	Yes	T1,T17,T122	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T1,T17,T122	Yes	T1,T17,T122	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T81,T83,T85	Yes	T81,T85,T86	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T17,*T63,*T205	Yes	T17,T63,T205	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T1,*T17,*T122	Yes	T1,T17,T122	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T1,T17,T122	Yes	T1,T17,T122	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T81,*T85,*T86	Yes	T81,T85,T86	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T81,T82,T85	Yes	T81,T85,T86	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T2,T31,T32	Yes	T2,T31,T32	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T60	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T2,T31,T32	Yes	T2,T31,T32	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T81,*T85,*T86	Yes	T81,T85,T86	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T60	Yes	T1,T2,T60	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T180,T62,T46	Yes	T180,T62,T46	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T180,T62,T46	Yes	T180,T62,T46	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T180,T62,T46	Yes	T180,T62,T46	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T180,T62,T46	Yes	T180,T62,T46	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T180,T62,T46	Yes	T180,T62,T46	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T81,*T83,*T85	Yes	T81,T83,T85	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T180,T62,T46	Yes	T180,T62,T46	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T180,T62,T46	Yes	T180,T62,T46	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T279,T280,T281	Yes	T279,T280,T281	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T180,T181,T123	Yes	T180,T62,T46	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T180,T181,T123	Yes	T180,T62,T46	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T81,T83,T85	Yes	T81,T82,T83	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T81,*T83,*T85	Yes	T81,T83,T85	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T180,*T181,*T123	Yes	T180,T181,T123	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T180,T62,T46	Yes	T180,T62,T46	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T31,T32	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range