Unified Coverage Report :: Module :: xbar_peri

Module : xbar_peri

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_peri	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.46	92.83		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_peri

	Total	Covered	Percent
Totals	562	562	100.00
Total Bits	7060	7060	100.00
Total Bits 0->1	3530	3530	100.00
Total Bits 1->0	3530	3530	100.00

Ports	562	562	100.00
Port Bits	7060	7060	100.00
Port Bits 0->1	3530	3530	100.00
Port Bits 1->0	3530	3530	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_peri_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_peri_ni	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
tl_main_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_source[5:0]	Yes	Yes	*T17,*T75,*T63	Yes	T17,T75,T63	INPUT
tl_main_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_main_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_opcode[2:0]	Yes	Yes	T17,T63,T84	Yes	T17,T63,T84	INPUT
tl_main_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_error	Yes	Yes	T70,T173,T177	Yes	T70,T173,T177	OUTPUT
tl_main_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_main_o.d_source[5:0]	Yes	Yes	*T17,*T75,*T63	Yes	T17,T75,T63	OUTPUT
tl_main_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_main_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.data_intg[6:0]	Yes	Yes	T200,T17,T74	Yes	T200,T17,T74	OUTPUT
tl_uart0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_data[31:0]	Yes	Yes	T200,T17,T74	Yes	T200,T17,T74	OUTPUT
tl_uart0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_source[5:0]	Yes	Yes	*T17,*T75,*T63	Yes	T17,T75,T63	OUTPUT
tl_uart0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_uart0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_opcode[2:0]	Yes	Yes	T17,T63,T84	Yes	T17,T63,T84	OUTPUT
tl_uart0_o.a_valid	Yes	Yes	T200,T17,T62	Yes	T200,T17,T62	OUTPUT
tl_uart0_i.a_ready	Yes	Yes	T200,T17,T62	Yes	T200,T17,T62	INPUT
tl_uart0_i.d_error	Yes	Yes	T82,T85,T86	Yes	T85,T86,T501	INPUT
tl_uart0_i.d_user.data_intg[6:0]	Yes	Yes	T200,T201,T642	Yes	T200,T201,T642	INPUT
tl_uart0_i.d_user.rsp_intg[6:0]	Yes	Yes	T200,T17,T201	Yes	T200,T17,T62	INPUT
tl_uart0_i.d_data[31:0]	Yes	Yes	T200,T17,T201	Yes	T200,T17,T62	INPUT
tl_uart0_i.d_sink	Yes	Yes	T81,T82,T85	Yes	T81,T85,T86	INPUT
tl_uart0_i.d_source[5:0]	Yes	Yes	*T17,*T81,*T85	Yes	T17,T81,T85	INPUT
tl_uart0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_size[1:0]	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_uart0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_opcode[0]	Yes	Yes	*T200,*T17,*T201	Yes	T200,T17,T201	INPUT
tl_uart0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_valid	Yes	Yes	T200,T17,T62	Yes	T200,T17,T62	INPUT
tl_uart1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.data_intg[6:0]	Yes	Yes	T5,T195,T17	Yes	T5,T195,T17	OUTPUT
tl_uart1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_data[31:0]	Yes	Yes	T5,T195,T17	Yes	T5,T195,T17	OUTPUT
tl_uart1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_source[5:0]	Yes	Yes	*T17,*T75,*T63	Yes	T17,T75,T63	OUTPUT
tl_uart1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_uart1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_opcode[2:0]	Yes	Yes	T17,T63,T84	Yes	T17,T63,T84	OUTPUT
tl_uart1_o.a_valid	Yes	Yes	T5,T195,T17	Yes	T5,T195,T17	OUTPUT
tl_uart1_i.a_ready	Yes	Yes	T5,T195,T17	Yes	T5,T195,T17	INPUT
tl_uart1_i.d_error	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_uart1_i.d_user.data_intg[6:0]	Yes	Yes	T5,T195,T17	Yes	T5,T195,T17	INPUT
tl_uart1_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T195,T17	Yes	T5,T195,T17	INPUT
tl_uart1_i.d_data[31:0]	Yes	Yes	T5,T195,T17	Yes	T5,T195,T17	INPUT
tl_uart1_i.d_sink	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_uart1_i.d_source[5:0]	Yes	Yes	*T17,*T81,*T82	Yes	T17,T81,T82	INPUT
tl_uart1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_size[1:0]	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_uart1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_opcode[0]	Yes	Yes	*T5,*T195,*T17	Yes	T5,T195,T17	INPUT
tl_uart1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_valid	Yes	Yes	T5,T195,T17	Yes	T5,T195,T17	INPUT
tl_uart2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.data_intg[6:0]	Yes	Yes	T17,T112,T189	Yes	T17,T112,T189	OUTPUT
tl_uart2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_data[31:0]	Yes	Yes	T17,T112,T189	Yes	T17,T112,T189	OUTPUT
tl_uart2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_source[5:0]	Yes	Yes	*T17,*T75,*T63	Yes	T17,T75,T63	OUTPUT
tl_uart2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_uart2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_opcode[2:0]	Yes	Yes	T17,T63,T84	Yes	T17,T63,T84	OUTPUT
tl_uart2_o.a_valid	Yes	Yes	T17,T112,T62	Yes	T17,T112,T62	OUTPUT
tl_uart2_i.a_ready	Yes	Yes	T17,T112,T62	Yes	T17,T112,T62	INPUT
tl_uart2_i.d_error	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	INPUT
tl_uart2_i.d_user.data_intg[6:0]	Yes	Yes	T17,T112,T189	Yes	T17,T112,T189	INPUT
tl_uart2_i.d_user.rsp_intg[6:0]	Yes	Yes	T17,T112,T189	Yes	T17,T112,T62	INPUT
tl_uart2_i.d_data[31:0]	Yes	Yes	T17,T112,T189	Yes	T17,T112,T62	INPUT
tl_uart2_i.d_sink	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	INPUT
tl_uart2_i.d_source[5:0]	Yes	Yes	*T17,*T81,*T83	Yes	T17,T81,T83	INPUT
tl_uart2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_size[1:0]	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	INPUT
tl_uart2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_opcode[0]	Yes	Yes	*T17,*T112,*T189	Yes	T17,T112,T189	INPUT
tl_uart2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_valid	Yes	Yes	T17,T112,T62	Yes	T17,T112,T62	INPUT
tl_uart3_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.data_intg[6:0]	Yes	Yes	T13,T17,T14	Yes	T13,T17,T14	OUTPUT
tl_uart3_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_data[31:0]	Yes	Yes	T13,T17,T14	Yes	T13,T17,T14	OUTPUT
tl_uart3_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_source[5:0]	Yes	Yes	*T17,*T75,*T63	Yes	T17,T75,T63	OUTPUT
tl_uart3_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_uart3_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_opcode[2:0]	Yes	Yes	T17,T63,T84	Yes	T17,T63,T84	OUTPUT
tl_uart3_o.a_valid	Yes	Yes	T13,T17,T62	Yes	T13,T17,T62	OUTPUT
tl_uart3_i.a_ready	Yes	Yes	T13,T17,T62	Yes	T13,T17,T62	INPUT
tl_uart3_i.d_error	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	INPUT
tl_uart3_i.d_user.data_intg[6:0]	Yes	Yes	T13,T17,T14	Yes	T13,T17,T14	INPUT
tl_uart3_i.d_user.rsp_intg[6:0]	Yes	Yes	T13,T17,T14	Yes	T13,T17,T62	INPUT
tl_uart3_i.d_data[31:0]	Yes	Yes	T13,T17,T14	Yes	T13,T17,T62	INPUT
tl_uart3_i.d_sink	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	INPUT
tl_uart3_i.d_source[5:0]	Yes	Yes	*T17,*T81,*T83	Yes	T17,T81,T83	INPUT
tl_uart3_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_size[1:0]	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	INPUT
tl_uart3_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_opcode[0]	Yes	Yes	*T13,*T17,*T14	Yes	T13,T17,T14	INPUT
tl_uart3_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_valid	Yes	Yes	T13,T17,T62	Yes	T13,T17,T62	INPUT
tl_i2c0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.data_intg[6:0]	Yes	Yes	T17,T63,T194	Yes	T17,T63,T194	OUTPUT
tl_i2c0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_data[31:0]	Yes	Yes	T17,T63,T194	Yes	T17,T63,T194	OUTPUT
tl_i2c0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_source[5:0]	Yes	Yes	*T17,*T75,*T63	Yes	T17,T75,T63	OUTPUT
tl_i2c0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_i2c0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_opcode[2:0]	Yes	Yes	T17,T63,T84	Yes	T17,T63,T84	OUTPUT
tl_i2c0_o.a_valid	Yes	Yes	T17,T62,T63	Yes	T17,T62,T63	OUTPUT
tl_i2c0_i.a_ready	Yes	Yes	T17,T62,T63	Yes	T17,T62,T63	INPUT
tl_i2c0_i.d_error	Yes	Yes	T81,T83,T85	Yes	T81,T85,T86	INPUT
tl_i2c0_i.d_user.data_intg[6:0]	Yes	Yes	T17,T63,T194	Yes	T17,T63,T194	INPUT
tl_i2c0_i.d_user.rsp_intg[6:0]	Yes	Yes	T17,T63,T194	Yes	T17,T62,T63	INPUT
tl_i2c0_i.d_data[31:0]	Yes	Yes	T17,T63,T194	Yes	T17,T62,T63	INPUT
tl_i2c0_i.d_sink	Yes	Yes	T81,T85,T86	Yes	T81,T83,T85	INPUT
tl_i2c0_i.d_source[5:0]	Yes	Yes	*T17,*T63,*T205	Yes	T17,T63,T205	INPUT
tl_i2c0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_size[1:0]	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_i2c0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_opcode[0]	Yes	Yes	*T17,*T63,*T194	Yes	T17,T63,T194	INPUT
tl_i2c0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_valid	Yes	Yes	T17,T62,T63	Yes	T17,T62,T63	INPUT
tl_i2c1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.data_intg[6:0]	Yes	Yes	T17,T197,T198	Yes	T17,T197,T198	OUTPUT
tl_i2c1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_data[31:0]	Yes	Yes	T17,T197,T198	Yes	T17,T197,T198	OUTPUT
tl_i2c1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_source[5:0]	Yes	Yes	*T17,*T75,*T63	Yes	T17,T75,T63	OUTPUT
tl_i2c1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_i2c1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_opcode[2:0]	Yes	Yes	T17,T63,T84	Yes	T17,T63,T84	OUTPUT
tl_i2c1_o.a_valid	Yes	Yes	T17,T62,T197	Yes	T17,T62,T197	OUTPUT
tl_i2c1_i.a_ready	Yes	Yes	T17,T62,T197	Yes	T17,T62,T197	INPUT
tl_i2c1_i.d_error	Yes	Yes	T81,T85,T86	Yes	T81,T82,T85	INPUT
tl_i2c1_i.d_user.data_intg[6:0]	Yes	Yes	T17,T197,T198	Yes	T17,T197,T198	INPUT
tl_i2c1_i.d_user.rsp_intg[6:0]	Yes	Yes	T17,T197,T198	Yes	T17,T62,T197	INPUT
tl_i2c1_i.d_data[31:0]	Yes	Yes	T17,T197,T198	Yes	T17,T62,T197	INPUT
tl_i2c1_i.d_sink	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_i2c1_i.d_source[5:0]	Yes	Yes	*T17,*T63,*T205	Yes	T17,T63,T205	INPUT
tl_i2c1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_size[1:0]	Yes	Yes	T81,T85,T86	Yes	T81,T82,T85	INPUT
tl_i2c1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_opcode[0]	Yes	Yes	*T17,*T197,*T198	Yes	T17,T197,T198	INPUT
tl_i2c1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_valid	Yes	Yes	T17,T62,T197	Yes	T17,T62,T197	INPUT
tl_i2c2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.data_intg[6:0]	Yes	Yes	T17,T63,T299	Yes	T17,T63,T299	OUTPUT
tl_i2c2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_data[31:0]	Yes	Yes	T17,T63,T299	Yes	T17,T63,T299	OUTPUT
tl_i2c2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_source[5:0]	Yes	Yes	*T17,*T75,*T63	Yes	T17,T75,T63	OUTPUT
tl_i2c2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_i2c2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_opcode[2:0]	Yes	Yes	T17,T63,T84	Yes	T17,T63,T84	OUTPUT
tl_i2c2_o.a_valid	Yes	Yes	T17,T62,T63	Yes	T17,T62,T63	OUTPUT
tl_i2c2_i.a_ready	Yes	Yes	T17,T62,T63	Yes	T17,T62,T63	INPUT
tl_i2c2_i.d_error	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_i2c2_i.d_user.data_intg[6:0]	Yes	Yes	T17,T63,T299	Yes	T17,T63,T299	INPUT
tl_i2c2_i.d_user.rsp_intg[6:0]	Yes	Yes	T17,T63,T299	Yes	T17,T62,T63	INPUT
tl_i2c2_i.d_data[31:0]	Yes	Yes	T17,T63,T299	Yes	T17,T62,T63	INPUT
tl_i2c2_i.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_i2c2_i.d_source[5:0]	Yes	Yes	*T17,*T63,*T205	Yes	T17,T63,T205	INPUT
tl_i2c2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_i2c2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_opcode[0]	Yes	Yes	*T17,*T63,*T299	Yes	T17,T63,T299	INPUT
tl_i2c2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_valid	Yes	Yes	T17,T62,T63	Yes	T17,T62,T63	INPUT
tl_pattgen_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.data_intg[6:0]	Yes	Yes	T63,T161,T162	Yes	T63,T161,T162	OUTPUT
tl_pattgen_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_data[31:0]	Yes	Yes	T63,T161,T162	Yes	T63,T161,T162	OUTPUT
tl_pattgen_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_source[5:0]	Yes	Yes	*T17,*T75,*T63	Yes	T17,T75,T63	OUTPUT
tl_pattgen_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_pattgen_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_opcode[2:0]	Yes	Yes	T17,T63,T84	Yes	T17,T63,T84	OUTPUT
tl_pattgen_o.a_valid	Yes	Yes	T62,T63,T161	Yes	T62,T63,T161	OUTPUT
tl_pattgen_i.a_ready	Yes	Yes	T62,T63,T161	Yes	T62,T63,T161	INPUT
tl_pattgen_i.d_error	Yes	Yes	T81,T82,T85	Yes	T81,T85,T86	INPUT
tl_pattgen_i.d_user.data_intg[6:0]	Yes	Yes	T63,T161,T162	Yes	T63,T161,T162	INPUT
tl_pattgen_i.d_user.rsp_intg[6:0]	Yes	Yes	T63,T161,T162	Yes	T62,T63,T161	INPUT
tl_pattgen_i.d_data[31:0]	Yes	Yes	T63,T161,T162	Yes	T62,T63,T161	INPUT
tl_pattgen_i.d_sink	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_pattgen_i.d_source[5:0]	Yes	Yes	*T63,T81,T85	Yes	T63,T81,T85	INPUT
tl_pattgen_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_size[1:0]	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_pattgen_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_opcode[0]	Yes	Yes	*T63,*T161,*T162	Yes	T63,T161,T162	INPUT
tl_pattgen_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_valid	Yes	Yes	T62,T63,T161	Yes	T62,T63,T161	INPUT
tl_pwm_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.data_intg[6:0]	Yes	Yes	T159,T190,T115	Yes	T159,T190,T115	OUTPUT
tl_pwm_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_data[31:0]	Yes	Yes	T159,T190,T115	Yes	T159,T190,T115	OUTPUT
tl_pwm_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_source[5:0]	Yes	Yes	*T17,*T75,*T63	Yes	T17,T75,T63	OUTPUT
tl_pwm_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_pwm_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_opcode[2:0]	Yes	Yes	T17,T63,T84	Yes	T17,T63,T84	OUTPUT
tl_pwm_aon_o.a_valid	Yes	Yes	T159,T62,T190	Yes	T159,T62,T190	OUTPUT
tl_pwm_aon_i.a_ready	Yes	Yes	T159,T62,T190	Yes	T159,T62,T190	INPUT
tl_pwm_aon_i.d_error	Yes	Yes	T85,T86,T231	Yes	T85,T86,T231	INPUT
tl_pwm_aon_i.d_user.data_intg[6:0]	Yes	Yes	T159,T190,T115	Yes	T159,T190,T115	INPUT
tl_pwm_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T159,T190,T115	Yes	T159,T62,T190	INPUT
tl_pwm_aon_i.d_data[31:0]	Yes	Yes	T159,T190,T115	Yes	T159,T62,T190	INPUT
tl_pwm_aon_i.d_sink	Yes	Yes	T81,T85,T86	Yes	T81,T83,T85	INPUT
tl_pwm_aon_i.d_source[5:0]	Yes	Yes	T81,*T85,*T86	Yes	T81,T85,T86	INPUT
tl_pwm_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_size[1:0]	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_pwm_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_opcode[0]	Yes	Yes	*T159,*T190,*T115	Yes	T159,T190,T115	INPUT
tl_pwm_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_valid	Yes	Yes	T159,T62,T190	Yes	T159,T62,T190	INPUT
tl_gpio_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T60	Yes	T1,T2,T60	OUTPUT
tl_gpio_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_data[31:0]	Yes	Yes	T1,T2,T60	Yes	T1,T2,T60	OUTPUT
tl_gpio_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_source[5:0]	Yes	Yes	*T17,*T75,*T63	Yes	T17,T75,T63	OUTPUT
tl_gpio_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_gpio_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_opcode[2:0]	Yes	Yes	T17,T63,T84	Yes	T17,T63,T84	OUTPUT
tl_gpio_o.a_valid	Yes	Yes	T1,T2,T60	Yes	T1,T2,T60	OUTPUT
tl_gpio_i.a_ready	Yes	Yes	T1,T2,T60	Yes	T1,T2,T60	INPUT
tl_gpio_i.d_error	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	INPUT
tl_gpio_i.d_user.data_intg[6:0]	Yes	Yes	T17,T24,T63	Yes	T17,T24,T63	INPUT
tl_gpio_i.d_user.rsp_intg[6:0]	Yes	Yes	T17,T24,T63	Yes	T159,T17,T62	INPUT
tl_gpio_i.d_data[31:0]	Yes	Yes	T17,T24,T63	Yes	T159,T17,T62	INPUT
tl_gpio_i.d_sink	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	INPUT
tl_gpio_i.d_source[5:0]	Yes	Yes	*T17,*T63,*T205	Yes	T17,T63,T205	INPUT
tl_gpio_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_size[1:0]	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	INPUT
tl_gpio_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_opcode[0]	Yes	Yes	*T1,*T31,*T32	Yes	T1,T2,T60	INPUT
tl_gpio_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_valid	Yes	Yes	T1,T2,T60	Yes	T1,T2,T60	INPUT
tl_spi_device_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.data_intg[6:0]	Yes	Yes	T5,T150,T10	Yes	T5,T150,T10	OUTPUT
tl_spi_device_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_data[31:0]	Yes	Yes	T5,T150,T10	Yes	T5,T150,T10	OUTPUT
tl_spi_device_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_source[5:0]	Yes	Yes	*T17,*T75,*T63	Yes	T17,T75,T63	OUTPUT
tl_spi_device_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_spi_device_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_opcode[2:0]	Yes	Yes	T17,T63,T84	Yes	T17,T63,T84	OUTPUT
tl_spi_device_o.a_valid	Yes	Yes	T5,T150,T62	Yes	T5,T150,T62	OUTPUT
tl_spi_device_i.a_ready	Yes	Yes	T5,T150,T62	Yes	T5,T150,T62	INPUT
tl_spi_device_i.d_error	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_spi_device_i.d_user.data_intg[6:0]	Yes	Yes	T5,T150,T10	Yes	T5,T150,T10	INPUT
tl_spi_device_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T150,T10	Yes	T5,T150,T10	INPUT
tl_spi_device_i.d_data[31:0]	Yes	Yes	T5,T150,T62	Yes	T5,T150,T10	INPUT
tl_spi_device_i.d_sink	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_spi_device_i.d_source[5:0]	Yes	Yes	*T81,*T82,*T85	Yes	T81,T82,T85	INPUT
tl_spi_device_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_size[1:0]	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_spi_device_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_opcode[0]	Yes	Yes	*T5,*T150,*T62	Yes	T5,T150,T10	INPUT
tl_spi_device_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_valid	Yes	Yes	T5,T150,T62	Yes	T5,T150,T62	INPUT
tl_rv_timer_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.data_intg[6:0]	Yes	Yes	T60,T159,T235	Yes	T60,T159,T235	OUTPUT
tl_rv_timer_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_data[31:0]	Yes	Yes	T60,T159,T235	Yes	T60,T159,T235	OUTPUT
tl_rv_timer_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_source[5:0]	Yes	Yes	*T17,*T75,*T63	Yes	T17,T75,T63	OUTPUT
tl_rv_timer_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_rv_timer_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_opcode[2:0]	Yes	Yes	T17,T63,T84	Yes	T17,T63,T84	OUTPUT
tl_rv_timer_o.a_valid	Yes	Yes	T60,T159,T235	Yes	T60,T159,T235	OUTPUT
tl_rv_timer_i.a_ready	Yes	Yes	T60,T159,T235	Yes	T60,T159,T235	INPUT
tl_rv_timer_i.d_error	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_rv_timer_i.d_user.data_intg[6:0]	Yes	Yes	T60,T235,T161	Yes	T60,T235,T161	INPUT
tl_rv_timer_i.d_user.rsp_intg[6:0]	Yes	Yes	T60,T159,T235	Yes	T60,T159,T235	INPUT
tl_rv_timer_i.d_data[31:0]	Yes	Yes	T60,T159,T235	Yes	T60,T159,T235	INPUT
tl_rv_timer_i.d_sink	Yes	Yes	T81,T82,T85	Yes	T81,T85,T86	INPUT
tl_rv_timer_i.d_source[5:0]	Yes	Yes	*T81,*T85,*T86	Yes	T81,T82,T85	INPUT
tl_rv_timer_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_size[1:0]	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_rv_timer_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_opcode[0]	Yes	Yes	*T60,*T159,*T235	Yes	T60,T159,T235	INPUT
tl_rv_timer_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_valid	Yes	Yes	T60,T159,T235	Yes	T60,T159,T235	INPUT
tl_pwrmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T2,T66,T159	Yes	T2,T66,T159	OUTPUT
tl_pwrmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_data[31:0]	Yes	Yes	T2,T66,T159	Yes	T2,T66,T159	OUTPUT
tl_pwrmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_source[5:0]	Yes	Yes	*T17,*T75,*T63	Yes	T17,T75,T63	OUTPUT
tl_pwrmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_pwrmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_opcode[2:0]	Yes	Yes	T17,T63,T84	Yes	T17,T63,T84	OUTPUT
tl_pwrmgr_aon_o.a_valid	Yes	Yes	T2,T66,T159	Yes	T2,T66,T159	OUTPUT
tl_pwrmgr_aon_i.a_ready	Yes	Yes	T2,T66,T159	Yes	T2,T66,T159	INPUT
tl_pwrmgr_aon_i.d_error	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_pwrmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T2,T66,T179	Yes	T2,T66,T179	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T66,T179	Yes	T2,T66,T179	INPUT
tl_pwrmgr_aon_i.d_data[31:0]	Yes	Yes	T2,T66,T179	Yes	T2,T66,T179	INPUT
tl_pwrmgr_aon_i.d_sink	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_pwrmgr_aon_i.d_source[5:0]	Yes	Yes	*T81,*T85,*T86	Yes	T81,T85,T86	INPUT
tl_pwrmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_size[1:0]	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_pwrmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_opcode[0]	Yes	Yes	*T2,*T66,*T179	Yes	T2,T66,T159	INPUT
tl_pwrmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_valid	Yes	Yes	T2,T66,T159	Yes	T2,T66,T159	INPUT
tl_rstmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T60	Yes	T1,T2,T60	OUTPUT
tl_rstmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T60	Yes	T1,T2,T60	OUTPUT
tl_rstmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_source[5:0]	Yes	Yes	*T17,*T75,*T63	Yes	T17,T75,T63	OUTPUT
tl_rstmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_rstmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_opcode[2:0]	Yes	Yes	T17,T63,T84	Yes	T17,T63,T84	OUTPUT
tl_rstmgr_aon_o.a_valid	Yes	Yes	T1,T2,T60	Yes	T1,T2,T60	OUTPUT
tl_rstmgr_aon_i.a_ready	Yes	Yes	T1,T2,T60	Yes	T1,T2,T60	INPUT
tl_rstmgr_aon_i.d_error	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_rstmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T60	Yes	T1,T2,T60	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T31,T32	Yes	T1,T2,T60	INPUT
tl_rstmgr_aon_i.d_data[31:0]	Yes	Yes	T1,T31,T32	Yes	T1,T2,T60	INPUT
tl_rstmgr_aon_i.d_sink	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_rstmgr_aon_i.d_source[5:0]	Yes	Yes	*T81,*T85,*T86	Yes	T81,T85,T86	INPUT
tl_rstmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_size[1:0]	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_rstmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T60	Yes	T1,T2,T60	INPUT
tl_rstmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_valid	Yes	Yes	T1,T2,T60	Yes	T1,T2,T60	INPUT
tl_clkmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T200,T173,T5	Yes	T200,T173,T5	OUTPUT
tl_clkmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_data[31:0]	Yes	Yes	T61,T91,T200	Yes	T61,T91,T200	OUTPUT
tl_clkmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_source[5:0]	Yes	Yes	*T17,*T75,*T63	Yes	T17,T75,T63	OUTPUT
tl_clkmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_clkmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_opcode[2:0]	Yes	Yes	T17,T63,T84	Yes	T17,T63,T84	OUTPUT
tl_clkmgr_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_error	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_clkmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T200,T173,T5	Yes	T200,T173,T5	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_data[31:0]	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_sink	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_clkmgr_aon_i.d_source[5:0]	Yes	Yes	*T81,*T85,*T86	Yes	T81,T85,T86	INPUT
tl_clkmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_size[1:0]	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_clkmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_opcode[0]	Yes	Yes	*T200,*T173,*T5	Yes	T200,T173,T5	INPUT
tl_clkmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_source[5:0]	Yes	Yes	*T17,*T75,*T63	Yes	T17,T75,T63	OUTPUT
tl_pinmux_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_pinmux_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_opcode[2:0]	Yes	Yes	T17,T63,T84	Yes	T17,T63,T84	OUTPUT
tl_pinmux_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_error	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_pinmux_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_sink	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_pinmux_aon_i.d_source[5:0]	Yes	Yes	*T63,*T81,*T85	Yes	T63,T81,T85	INPUT
tl_pinmux_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_size[1:0]	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_pinmux_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_source[5:0]	Yes	Yes	*T17,*T75,*T63	Yes	T17,T75,T63	OUTPUT
tl_otp_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_otp_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T17,T63,T84	Yes	T17,T63,T84	OUTPUT
tl_otp_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_error	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_otp_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_sink	Yes	Yes	T81,T83,T85	Yes	T81,T85,T86	INPUT
tl_otp_ctrl__core_i.d_source[5:0]	Yes	Yes	*T63,*T156,*T157	Yes	T63,T156,T157	INPUT
tl_otp_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_size[1:0]	Yes	Yes	T81,T83,T85	Yes	T81,T85,T86	INPUT
tl_otp_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_opcode[0]	Yes	Yes	*T1,*T158,*T159	Yes	T1,T158,T160	INPUT
tl_otp_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__prim_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T63,T81,T85	Yes	T63,T81,T85	OUTPUT
tl_otp_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_data[31:0]	Yes	Yes	T63,T81,T85	Yes	T63,T81,T85	OUTPUT
tl_otp_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T17,*T75,*T63	Yes	T17,T75,T63	OUTPUT
tl_otp_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_otp_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T17,T63,T84	Yes	T17,T63,T84	OUTPUT
tl_otp_ctrl__prim_o.a_valid	Yes	Yes	T63,T81,T85	Yes	T63,T81,T85	OUTPUT
tl_otp_ctrl__prim_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__prim_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T31,T32	INPUT
tl_otp_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T63,T81,T85	Yes	T63,T81,T85	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T63,T81,T85	Yes	T63,T81,T85	INPUT
tl_otp_ctrl__prim_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T31,T32	INPUT
tl_otp_ctrl__prim_i.d_sink	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_otp_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T63,T81,T85	Yes	T63,T81,T85	INPUT
tl_otp_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_size[1:0]	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_otp_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T31,T32	INPUT
tl_otp_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_valid	Yes	Yes	T63,T81,T85	Yes	T63,T81,T85	INPUT
tl_lc_ctrl_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T150	Yes	T4,T5,T150	OUTPUT
tl_lc_ctrl_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_data[31:0]	Yes	Yes	T4,T5,T150	Yes	T4,T5,T150	OUTPUT
tl_lc_ctrl_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_source[5:0]	Yes	Yes	*T17,*T75,*T63	Yes	T17,T75,T63	OUTPUT
tl_lc_ctrl_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_lc_ctrl_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_opcode[2:0]	Yes	Yes	T17,T63,T84	Yes	T17,T63,T84	OUTPUT
tl_lc_ctrl_o.a_valid	Yes	Yes	T4,T5,T150	Yes	T4,T5,T150	OUTPUT
tl_lc_ctrl_i.a_ready	Yes	Yes	T4,T5,T150	Yes	T4,T5,T150	INPUT
tl_lc_ctrl_i.d_error	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_lc_ctrl_i.d_user.data_intg[6:0]	Yes	Yes	T5,T150,T48	Yes	T5,T150,T48	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[6:0]	Yes	Yes	T48,T68,T125	Yes	T62,T48,T68	INPUT
tl_lc_ctrl_i.d_data[31:0]	Yes	Yes	T4,T5,T150	Yes	T4,T5,T150	INPUT
tl_lc_ctrl_i.d_sink	Yes	Yes	T81,T82,T85	Yes	T81,T85,T86	INPUT
tl_lc_ctrl_i.d_source[5:0]	Yes	Yes	*T75,*T63,*T236	Yes	T75,T63,T236	INPUT
tl_lc_ctrl_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_size[1:0]	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_lc_ctrl_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T150	Yes	T4,T5,T150	INPUT
tl_lc_ctrl_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_valid	Yes	Yes	T4,T5,T150	Yes	T4,T5,T150	INPUT
tl_sensor_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T17,*T75,*T63	Yes	T17,T75,T63	OUTPUT
tl_sensor_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_sensor_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T17,T63,T84	Yes	T17,T63,T84	OUTPUT
tl_sensor_ctrl_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_error	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	INPUT
tl_sensor_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T147,T134,T135	Yes	T147,T134,T135	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T147,T134,T135	Yes	T62,T147,T134	INPUT
tl_sensor_ctrl_aon_i.d_data[31:0]	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_sink	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	INPUT
tl_sensor_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T81,*T83,*T85	Yes	T81,T83,T85	INPUT
tl_sensor_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_size[1:0]	Yes	Yes	T81,T83,T85	Yes	T81,T83,T85	INPUT
tl_sensor_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T1,*T31,*T32	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_alert_handler_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.data_intg[6:0]	Yes	Yes	T2,T31,T32	Yes	T2,T31,T32	OUTPUT
tl_alert_handler_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_data[31:0]	Yes	Yes	T2,T31,T32	Yes	T2,T31,T32	OUTPUT
tl_alert_handler_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_source[5:0]	Yes	Yes	*T17,*T75,*T63	Yes	T17,T75,T63	OUTPUT
tl_alert_handler_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_alert_handler_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_opcode[2:0]	Yes	Yes	T17,T63,T84	Yes	T17,T63,T84	OUTPUT
tl_alert_handler_o.a_valid	Yes	Yes	T2,T31,T32	Yes	T2,T31,T32	OUTPUT
tl_alert_handler_i.a_ready	Yes	Yes	T2,T31,T32	Yes	T2,T31,T32	INPUT
tl_alert_handler_i.d_error	Yes	Yes	T81,T85,T86	Yes	T81,T83,T85	INPUT
tl_alert_handler_i.d_user.data_intg[6:0]	Yes	Yes	T2,T31,T32	Yes	T2,T31,T32	INPUT
tl_alert_handler_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T31,T32	Yes	T2,T31,T32	INPUT
tl_alert_handler_i.d_data[31:0]	Yes	Yes	T2,T31,T32	Yes	T2,T31,T32	INPUT
tl_alert_handler_i.d_sink	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_alert_handler_i.d_source[5:0]	Yes	Yes	*T81,*T85,*T86	Yes	T81,T83,T85	INPUT
tl_alert_handler_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_size[1:0]	Yes	Yes	T81,T83,T85	Yes	T81,T85,T86	INPUT
tl_alert_handler_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_opcode[0]	Yes	Yes	*T2,*T31,*T32	Yes	T2,T31,T32	INPUT
tl_alert_handler_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_valid	Yes	Yes	T2,T31,T32	Yes	T2,T31,T32	INPUT
tl_sram_ctrl_ret_aon__regs_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.data_intg[6:0]	Yes	Yes	T180,T46,T47	Yes	T180,T46,T47	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_data[31:0]	Yes	Yes	T180,T46,T47	Yes	T180,T46,T47	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[5:0]	Yes	Yes	*T17,*T75,*T63	Yes	T17,T75,T63	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[2:0]	Yes	Yes	T17,T63,T84	Yes	T17,T63,T84	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_valid	Yes	Yes	T180,T62,T46	Yes	T180,T62,T46	OUTPUT
tl_sram_ctrl_ret_aon__regs_i.a_ready	Yes	Yes	T180,T62,T46	Yes	T180,T62,T46	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_error	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[6:0]	Yes	Yes	T180,T181,T123	Yes	T180,T181,T123	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T180,T181,T123	Yes	T180,T62,T46	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_data[31:0]	Yes	Yes	T180,T181,T123	Yes	T180,T62,T46	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[5:0]	Yes	Yes	*T81,*T82,*T83	Yes	T81,T82,T83	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[0]	Yes	Yes	*T180,*T181,*T123	Yes	T180,T181,T123	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_valid	Yes	Yes	T180,T62,T46	Yes	T180,T62,T46	INPUT
tl_sram_ctrl_ret_aon__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T60	Yes	T1,T2,T60	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[5:0]	Yes	Yes	*T17,*T75,*T63	Yes	T17,T75,T63	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[2:0]	Yes	Yes	T17,T63,T84	Yes	T17,T63,T84	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_valid	Yes	Yes	T1,T2,T60	Yes	T1,T2,T60	OUTPUT
tl_sram_ctrl_ret_aon__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T31,T32	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_sink	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[5:0]	Yes	Yes	*T84,*T232,*T406	Yes	T84,T232,T406	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[1:0]	Yes	Yes	T81,T85,T86	Yes	T81,T83,T85	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T60	Yes	T1,T2,T60	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_valid	Yes	Yes	T1,T2,T60	Yes	T1,T2,T60	INPUT
tl_aon_timer_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.data_intg[6:0]	Yes	Yes	T2,T31,T32	Yes	T2,T31,T32	OUTPUT
tl_aon_timer_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_data[31:0]	Yes	Yes	T2,T31,T32	Yes	T2,T31,T32	OUTPUT
tl_aon_timer_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_source[5:0]	Yes	Yes	*T17,*T75,*T63	Yes	T17,T75,T63	OUTPUT
tl_aon_timer_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_aon_timer_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_opcode[2:0]	Yes	Yes	T17,T63,T84	Yes	T17,T63,T84	OUTPUT
tl_aon_timer_aon_o.a_valid	Yes	Yes	T2,T31,T32	Yes	T2,T31,T32	OUTPUT
tl_aon_timer_aon_i.a_ready	Yes	Yes	T2,T31,T32	Yes	T2,T31,T32	INPUT
tl_aon_timer_aon_i.d_error	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_aon_timer_aon_i.d_user.data_intg[6:0]	Yes	Yes	T2,T31,T32	Yes	T2,T31,T32	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T31,T32	Yes	T2,T31,T32	INPUT
tl_aon_timer_aon_i.d_data[31:0]	Yes	Yes	T2,T31,T32	Yes	T2,T31,T32	INPUT
tl_aon_timer_aon_i.d_sink	Yes	Yes	T81,T83,T85	Yes	T81,T85,T86	INPUT
tl_aon_timer_aon_i.d_source[5:0]	Yes	Yes	*T81,*T85,*T86	Yes	T81,T85,T86	INPUT
tl_aon_timer_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_size[1:0]	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_aon_timer_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_opcode[0]	Yes	Yes	*T2,*T31,*T32	Yes	T2,T31,T32	INPUT
tl_aon_timer_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_valid	Yes	Yes	T2,T31,T32	Yes	T2,T31,T32	INPUT
tl_sysrst_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T191,T6,T18	Yes	T191,T6,T18	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_data[31:0]	Yes	Yes	T191,T6,T18	Yes	T191,T6,T18	OUTPUT
tl_sysrst_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T17,*T75,*T63	Yes	T17,T75,T63	OUTPUT
tl_sysrst_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_sysrst_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T17,T63,T84	Yes	T17,T63,T84	OUTPUT
tl_sysrst_ctrl_aon_o.a_valid	Yes	Yes	T191,T6,T18	Yes	T191,T6,T18	OUTPUT
tl_sysrst_ctrl_aon_i.a_ready	Yes	Yes	T191,T6,T18	Yes	T191,T6,T18	INPUT
tl_sysrst_ctrl_aon_i.d_error	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_sysrst_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T191,T6,T18	Yes	T191,T6,T18	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T18,T637	Yes	T6,T18,T62	INPUT
tl_sysrst_ctrl_aon_i.d_data[31:0]	Yes	Yes	T191,T6,T192	Yes	T191,T6,T18	INPUT
tl_sysrst_ctrl_aon_i.d_sink	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_sysrst_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T81,*T85,*T86	Yes	T81,T85,T86	INPUT
tl_sysrst_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_size[1:0]	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_sysrst_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T6,*T18,*T637	Yes	T191,T6,T18	INPUT
tl_sysrst_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_valid	Yes	Yes	T191,T6,T18	Yes	T191,T6,T18	INPUT
tl_adc_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T18,T50,T299	Yes	T18,T50,T299	OUTPUT
tl_adc_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_data[31:0]	Yes	Yes	T18,T50,T299	Yes	T18,T50,T299	OUTPUT
tl_adc_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T17,*T75,*T63	Yes	T17,T75,T63	OUTPUT
tl_adc_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_adc_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T17,T63,T84	Yes	T17,T63,T84	OUTPUT
tl_adc_ctrl_aon_o.a_valid	Yes	Yes	T18,T62,T50	Yes	T18,T62,T50	OUTPUT
tl_adc_ctrl_aon_i.a_ready	Yes	Yes	T18,T62,T50	Yes	T18,T62,T50	INPUT
tl_adc_ctrl_aon_i.d_error	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T18,T50,T299	Yes	T18,T50,T299	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T18,T50,T299	Yes	T18,T62,T50	INPUT
tl_adc_ctrl_aon_i.d_data[31:0]	Yes	Yes	T18,T50,T115	Yes	T18,T62,T50	INPUT
tl_adc_ctrl_aon_i.d_sink	Yes	Yes	T81,T82,T85	Yes	T81,T85,T86	INPUT
tl_adc_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T81,*T85,*T86	Yes	T81,T85,T86	INPUT
tl_adc_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_size[1:0]	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_adc_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T18,*T50,*T299	Yes	T18,T50,T299	INPUT
tl_adc_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_valid	Yes	Yes	T18,T62,T50	Yes	T18,T62,T50	INPUT
tl_ast_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_source[5:0]	Yes	Yes	*T17,*T75,*T63	Yes	T17,T75,T63	OUTPUT
tl_ast_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_ast_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_opcode[2:0]	Yes	Yes	T17,T63,T84	Yes	T17,T63,T84	OUTPUT
tl_ast_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_ast_i.d_error	Yes	Yes	T81,T82,T85	Yes	T81,T85,T86	INPUT
tl_ast_i.d_user.data_intg[6:0]	Yes	Yes	T81,T85,T86	Yes	T81,T82,T85	INPUT
tl_ast_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
tl_ast_i.d_data[31:0]	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
tl_ast_i.d_sink	Yes	Yes	T81,T82,T85	Yes	T81,T85,T86	INPUT
tl_ast_i.d_source[5:0]	Yes	Yes	T81,T85,T86	Yes	T81,T85,T86	INPUT
tl_ast_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_size[1:0]	Yes	Yes	T81,T85,T86	Yes	T81,T82,T85	INPUT
tl_ast_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_opcode[0]	Yes	Yes	*T81,*T82,*T85	Yes	T81,T85,T86	INPUT
tl_ast_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range