Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T113,T183,T277
0	1	Covered	T113,T183,T277
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T113,T183,T277
1	Covered	T113,T183,T277

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T113,T183,T277
1	Covered	T113,T183,T277

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T113,T183,T277
1	1	Covered	T113,T183,T277

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T113,T183,T277
1	0	Covered	T113,T183,T277
1	1	Covered	T113,T183,T277

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T113,T183,T277

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T113,T183,T277
0	Covered	T113,T183,T277

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T113,T183,T277
0	Covered	T113,T183,T277

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	855948164	839411980	0	0
CheckNGreaterZero_A	1820	1820	0	0
GntImpliesReady_A	855948164	5439	0	0
GntImpliesValid_A	855948164	5439	0	0
GrantKnown_A	855948164	839411980	0	0
IdxKnown_A	855948164	839411980	0	0
IndexIsCorrect_A	855948164	5439	0	0
NoReadyValidNoGrant_A	855948164	0	0	0
Priority_A	855948164	5439	0	0
ReadyAndValidImplyGrant_A	855948164	5439	0	0
ReqAndReadyImplyGrant_A	855948164	5439	0	0
ReqImpliesValid_A	855948164	5439	0	0
ValidKnown_A	855948164	839411980	0	0
gen_data_port_assertion.DataFlow_A	855948164	5439	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	855948164	839411980	0	0
T1	313238	313006	0	0
T2	308584	308460	0	0
T3	716984	716882	0	0
T16	337952	337942	0	0
T31	438344	438118	0	0
T32	485150	484924	0	0
T60	218682	218580	0	0
T61	284660	284648	0	0
T90	184142	184026	0	0
T91	720884	720774	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1820	1820	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T16	2	2	0	0
T31	2	2	0	0
T32	2	2	0	0
T60	2	2	0	0
T61	2	2	0	0
T90	2	2	0	0
T91	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	855948164	5439	0	0
T49	422544	0	0	0
T78	1939090	0	0	0
T113	188910	1811	0	0
T114	84374	0	0	0
T133	301326	0	0	0
T180	320358	0	0	0
T183	0	1809	0	0
T222	639770	0	0	0
T250	551940	0	0	0
T265	275742	0	0	0
T266	273208	0	0	0
T277	0	1819	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	855948164	5439	0	0
T49	422544	0	0	0
T78	1939090	0	0	0
T113	188910	1811	0	0
T114	84374	0	0	0
T133	301326	0	0	0
T180	320358	0	0	0
T183	0	1809	0	0
T222	639770	0	0	0
T250	551940	0	0	0
T265	275742	0	0	0
T266	273208	0	0	0
T277	0	1819	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	855948164	839411980	0	0
T1	313238	313006	0	0
T2	308584	308460	0	0
T3	716984	716882	0	0
T16	337952	337942	0	0
T31	438344	438118	0	0
T32	485150	484924	0	0
T60	218682	218580	0	0
T61	284660	284648	0	0
T90	184142	184026	0	0
T91	720884	720774	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	855948164	839411980	0	0
T1	313238	313006	0	0
T2	308584	308460	0	0
T3	716984	716882	0	0
T16	337952	337942	0	0
T31	438344	438118	0	0
T32	485150	484924	0	0
T60	218682	218580	0	0
T61	284660	284648	0	0
T90	184142	184026	0	0
T91	720884	720774	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	855948164	5439	0	0
T49	422544	0	0	0
T78	1939090	0	0	0
T113	188910	1811	0	0
T114	84374	0	0	0
T133	301326	0	0	0
T180	320358	0	0	0
T183	0	1809	0	0
T222	639770	0	0	0
T250	551940	0	0	0
T265	275742	0	0	0
T266	273208	0	0	0
T277	0	1819	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	855948164	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	855948164	5439	0	0
T49	422544	0	0	0
T78	1939090	0	0	0
T113	188910	1811	0	0
T114	84374	0	0	0
T133	301326	0	0	0
T180	320358	0	0	0
T183	0	1809	0	0
T222	639770	0	0	0
T250	551940	0	0	0
T265	275742	0	0	0
T266	273208	0	0	0
T277	0	1819	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	855948164	5439	0	0
T49	422544	0	0	0
T78	1939090	0	0	0
T113	188910	1811	0	0
T114	84374	0	0	0
T133	301326	0	0	0
T180	320358	0	0	0
T183	0	1809	0	0
T222	639770	0	0	0
T250	551940	0	0	0
T265	275742	0	0	0
T266	273208	0	0	0
T277	0	1819	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	855948164	5439	0	0
T49	422544	0	0	0
T78	1939090	0	0	0
T113	188910	1811	0	0
T114	84374	0	0	0
T133	301326	0	0	0
T180	320358	0	0	0
T183	0	1809	0	0
T222	639770	0	0	0
T250	551940	0	0	0
T265	275742	0	0	0
T266	273208	0	0	0
T277	0	1819	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	855948164	5439	0	0
T49	422544	0	0	0
T78	1939090	0	0	0
T113	188910	1811	0	0
T114	84374	0	0	0
T133	301326	0	0	0
T180	320358	0	0	0
T183	0	1809	0	0
T222	639770	0	0	0
T250	551940	0	0	0
T265	275742	0	0	0
T266	273208	0	0	0
T277	0	1819	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	855948164	839411980	0	0
T1	313238	313006	0	0
T2	308584	308460	0	0
T3	716984	716882	0	0
T16	337952	337942	0	0
T31	438344	438118	0	0
T32	485150	484924	0	0
T60	218682	218580	0	0
T61	284660	284648	0	0
T90	184142	184026	0	0
T91	720884	720774	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	855948164	5439	0	0
T49	422544	0	0	0
T78	1939090	0	0	0
T113	188910	1811	0	0
T114	84374	0	0	0
T133	301326	0	0	0
T180	320358	0	0	0
T183	0	1809	0	0
T222	639770	0	0	0
T250	551940	0	0	0
T265	275742	0	0	0
T266	273208	0	0	0
T277	0	1819	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T113,T183,T277
0	1	Covered	T113,T183,T277
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T113,T183,T277
1	Covered	T113,T183,T277

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T113,T183,T277
1	Covered	T113,T183,T277

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T113,T183,T277
1	1	Covered	T113,T183,T277

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T113,T183,T277
1	0	Covered	T113,T183,T277
1	1	Covered	T113,T183,T277

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T113,T183,T277

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T113,T183,T277
0	Covered	T113,T183,T277

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T113,T183,T277
0	Covered	T113,T183,T277

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427974082	419705990	0	0
CheckNGreaterZero_A	910	910	0	0
GntImpliesReady_A	427974082	4401	0	0
GntImpliesValid_A	427974082	4401	0	0
GrantKnown_A	427974082	419705990	0	0
IdxKnown_A	427974082	419705990	0	0
IndexIsCorrect_A	427974082	4401	0	0
NoReadyValidNoGrant_A	427974082	0	0	0
Priority_A	427974082	4401	0	0
ReadyAndValidImplyGrant_A	427974082	4401	0	0
ReqAndReadyImplyGrant_A	427974082	4401	0	0
ReqImpliesValid_A	427974082	4401	0	0
ValidKnown_A	427974082	419705990	0	0
gen_data_port_assertion.DataFlow_A	427974082	4401	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	419705990	0	0
T1	156619	156503	0	0
T2	154292	154230	0	0
T3	358492	358441	0	0
T16	168976	168971	0	0
T31	219172	219059	0	0
T32	242575	242462	0	0
T60	109341	109290	0	0
T61	142330	142324	0	0
T90	92071	92013	0	0
T91	360442	360387	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	910	910	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	4401	0	0
T49	211272	0	0	0
T78	969545	0	0	0
T113	94455	1465	0	0
T114	42187	0	0	0
T133	150663	0	0	0
T180	160179	0	0	0
T183	0	1463	0	0
T222	319885	0	0	0
T250	275970	0	0	0
T265	137871	0	0	0
T266	136604	0	0	0
T277	0	1473	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	4401	0	0
T49	211272	0	0	0
T78	969545	0	0	0
T113	94455	1465	0	0
T114	42187	0	0	0
T133	150663	0	0	0
T180	160179	0	0	0
T183	0	1463	0	0
T222	319885	0	0	0
T250	275970	0	0	0
T265	137871	0	0	0
T266	136604	0	0	0
T277	0	1473	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	419705990	0	0
T1	156619	156503	0	0
T2	154292	154230	0	0
T3	358492	358441	0	0
T16	168976	168971	0	0
T31	219172	219059	0	0
T32	242575	242462	0	0
T60	109341	109290	0	0
T61	142330	142324	0	0
T90	92071	92013	0	0
T91	360442	360387	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	419705990	0	0
T1	156619	156503	0	0
T2	154292	154230	0	0
T3	358492	358441	0	0
T16	168976	168971	0	0
T31	219172	219059	0	0
T32	242575	242462	0	0
T60	109341	109290	0	0
T61	142330	142324	0	0
T90	92071	92013	0	0
T91	360442	360387	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	4401	0	0
T49	211272	0	0	0
T78	969545	0	0	0
T113	94455	1465	0	0
T114	42187	0	0	0
T133	150663	0	0	0
T180	160179	0	0	0
T183	0	1463	0	0
T222	319885	0	0	0
T250	275970	0	0	0
T265	137871	0	0	0
T266	136604	0	0	0
T277	0	1473	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	4401	0	0
T49	211272	0	0	0
T78	969545	0	0	0
T113	94455	1465	0	0
T114	42187	0	0	0
T133	150663	0	0	0
T180	160179	0	0	0
T183	0	1463	0	0
T222	319885	0	0	0
T250	275970	0	0	0
T265	137871	0	0	0
T266	136604	0	0	0
T277	0	1473	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	4401	0	0
T49	211272	0	0	0
T78	969545	0	0	0
T113	94455	1465	0	0
T114	42187	0	0	0
T133	150663	0	0	0
T180	160179	0	0	0
T183	0	1463	0	0
T222	319885	0	0	0
T250	275970	0	0	0
T265	137871	0	0	0
T266	136604	0	0	0
T277	0	1473	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	4401	0	0
T49	211272	0	0	0
T78	969545	0	0	0
T113	94455	1465	0	0
T114	42187	0	0	0
T133	150663	0	0	0
T180	160179	0	0	0
T183	0	1463	0	0
T222	319885	0	0	0
T250	275970	0	0	0
T265	137871	0	0	0
T266	136604	0	0	0
T277	0	1473	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	4401	0	0
T49	211272	0	0	0
T78	969545	0	0	0
T113	94455	1465	0	0
T114	42187	0	0	0
T133	150663	0	0	0
T180	160179	0	0	0
T183	0	1463	0	0
T222	319885	0	0	0
T250	275970	0	0	0
T265	137871	0	0	0
T266	136604	0	0	0
T277	0	1473	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	419705990	0	0
T1	156619	156503	0	0
T2	154292	154230	0	0
T3	358492	358441	0	0
T16	168976	168971	0	0
T31	219172	219059	0	0
T32	242575	242462	0	0
T60	109341	109290	0	0
T61	142330	142324	0	0
T90	92071	92013	0	0
T91	360442	360387	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	4401	0	0
T49	211272	0	0	0
T78	969545	0	0	0
T113	94455	1465	0	0
T114	42187	0	0	0
T133	150663	0	0	0
T180	160179	0	0	0
T183	0	1463	0	0
T222	319885	0	0	0
T250	275970	0	0	0
T265	137871	0	0	0
T266	136604	0	0	0
T277	0	1473	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T113,T183,T277
0	1	Covered	T113,T183,T277
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T113,T183,T277
1	Covered	T113,T183,T277

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T113,T183,T277
1	Covered	T113,T183,T277

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T113,T183,T277
1	1	Covered	T113,T183,T277

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T113,T183,T277
1	0	Covered	T113,T183,T277
1	1	Covered	T113,T183,T277

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T113,T183,T277

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T113,T183,T277
0	Covered	T113,T183,T277

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T113,T183,T277
0	Covered	T113,T183,T277

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427974082	419705990	0	0
CheckNGreaterZero_A	910	910	0	0
GntImpliesReady_A	427974082	1038	0	0
GntImpliesValid_A	427974082	1038	0	0
GrantKnown_A	427974082	419705990	0	0
IdxKnown_A	427974082	419705990	0	0
IndexIsCorrect_A	427974082	1038	0	0
NoReadyValidNoGrant_A	427974082	0	0	0
Priority_A	427974082	1038	0	0
ReadyAndValidImplyGrant_A	427974082	1038	0	0
ReqAndReadyImplyGrant_A	427974082	1038	0	0
ReqImpliesValid_A	427974082	1038	0	0
ValidKnown_A	427974082	419705990	0	0
gen_data_port_assertion.DataFlow_A	427974082	1038	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	419705990	0	0
T1	156619	156503	0	0
T2	154292	154230	0	0
T3	358492	358441	0	0
T16	168976	168971	0	0
T31	219172	219059	0	0
T32	242575	242462	0	0
T60	109341	109290	0	0
T61	142330	142324	0	0
T90	92071	92013	0	0
T91	360442	360387	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	910	910	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	1038	0	0
T49	211272	0	0	0
T78	969545	0	0	0
T113	94455	346	0	0
T114	42187	0	0	0
T133	150663	0	0	0
T180	160179	0	0	0
T183	0	346	0	0
T222	319885	0	0	0
T250	275970	0	0	0
T265	137871	0	0	0
T266	136604	0	0	0
T277	0	346	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	1038	0	0
T49	211272	0	0	0
T78	969545	0	0	0
T113	94455	346	0	0
T114	42187	0	0	0
T133	150663	0	0	0
T180	160179	0	0	0
T183	0	346	0	0
T222	319885	0	0	0
T250	275970	0	0	0
T265	137871	0	0	0
T266	136604	0	0	0
T277	0	346	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	419705990	0	0
T1	156619	156503	0	0
T2	154292	154230	0	0
T3	358492	358441	0	0
T16	168976	168971	0	0
T31	219172	219059	0	0
T32	242575	242462	0	0
T60	109341	109290	0	0
T61	142330	142324	0	0
T90	92071	92013	0	0
T91	360442	360387	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	419705990	0	0
T1	156619	156503	0	0
T2	154292	154230	0	0
T3	358492	358441	0	0
T16	168976	168971	0	0
T31	219172	219059	0	0
T32	242575	242462	0	0
T60	109341	109290	0	0
T61	142330	142324	0	0
T90	92071	92013	0	0
T91	360442	360387	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	1038	0	0
T49	211272	0	0	0
T78	969545	0	0	0
T113	94455	346	0	0
T114	42187	0	0	0
T133	150663	0	0	0
T180	160179	0	0	0
T183	0	346	0	0
T222	319885	0	0	0
T250	275970	0	0	0
T265	137871	0	0	0
T266	136604	0	0	0
T277	0	346	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	1038	0	0
T49	211272	0	0	0
T78	969545	0	0	0
T113	94455	346	0	0
T114	42187	0	0	0
T133	150663	0	0	0
T180	160179	0	0	0
T183	0	346	0	0
T222	319885	0	0	0
T250	275970	0	0	0
T265	137871	0	0	0
T266	136604	0	0	0
T277	0	346	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	1038	0	0
T49	211272	0	0	0
T78	969545	0	0	0
T113	94455	346	0	0
T114	42187	0	0	0
T133	150663	0	0	0
T180	160179	0	0	0
T183	0	346	0	0
T222	319885	0	0	0
T250	275970	0	0	0
T265	137871	0	0	0
T266	136604	0	0	0
T277	0	346	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	1038	0	0
T49	211272	0	0	0
T78	969545	0	0	0
T113	94455	346	0	0
T114	42187	0	0	0
T133	150663	0	0	0
T180	160179	0	0	0
T183	0	346	0	0
T222	319885	0	0	0
T250	275970	0	0	0
T265	137871	0	0	0
T266	136604	0	0	0
T277	0	346	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	1038	0	0
T49	211272	0	0	0
T78	969545	0	0	0
T113	94455	346	0	0
T114	42187	0	0	0
T133	150663	0	0	0
T180	160179	0	0	0
T183	0	346	0	0
T222	319885	0	0	0
T250	275970	0	0	0
T265	137871	0	0	0
T266	136604	0	0	0
T277	0	346	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	419705990	0	0
T1	156619	156503	0	0
T2	154292	154230	0	0
T3	358492	358441	0	0
T16	168976	168971	0	0
T31	219172	219059	0	0
T32	242575	242462	0	0
T60	109341	109290	0	0
T61	142330	142324	0	0
T90	92071	92013	0	0
T91	360442	360387	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427974082	1038	0	0
T49	211272	0	0	0
T78	969545	0	0	0
T113	94455	346	0	0
T114	42187	0	0	0
T133	150663	0	0	0
T180	160179	0	0	0
T183	0	346	0	0
T222	319885	0	0	0
T250	275970	0	0	0
T265	137871	0	0	0
T266	136604	0	0	0
T277	0	346	0	0