Unified Coverage Report :: Module :: prim_mubi4_sync

Module : prim_mubi4_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync	100.00						100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.41	99.34	100.00			98.31	100.00	u_pinmux_strap_sampling

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : prim_mubi4_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	910	910	0	0
OutputsKnown_A	106873323	106259440	0	0
gen_no_flops.OutputDelay_A	106873323	106259440	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	910	910	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106873323	106259440	0	0
T1	38803	38336	0	0
T2	41836	41276	0	0
T3	87198	86412	0	0
T16	406422	405937	0	0
T31	54137	53340	0	0
T32	59448	58959	0	0
T60	26889	26612	0	0
T61	544314	543727	0	0
T90	22802	22465	0	0
T91	134574	133867	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106873323	106259440	0	0
T1	38803	38336	0	0
T2	41836	41276	0	0
T3	87198	86412	0	0
T16	406422	405937	0	0
T31	54137	53340	0	0
T32	59448	58959	0	0
T60	26889	26612	0	0
T61	544314	543727	0	0
T90	22802	22465	0	0
T91	134574	133867	0	0

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	910	910	0	0
OutputsKnown_A	106873323	106259440	0	0
gen_no_flops.OutputDelay_A	106873323	106259440	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	910	910	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106873323	106259440	0	0
T1	38803	38336	0	0
T2	41836	41276	0	0
T3	87198	86412	0	0
T16	406422	405937	0	0
T31	54137	53340	0	0
T32	59448	58959	0	0
T60	26889	26612	0	0
T61	544314	543727	0	0
T90	22802	22465	0	0
T91	134574	133867	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106873323	106259440	0	0
T1	38803	38336	0	0
T2	41836	41276	0	0
T3	87198	86412	0	0
T16	406422	405937	0	0
T31	54137	53340	0	0
T32	59448	58959	0	0
T60	26889	26612	0	0
T61	544314	543727	0	0
T90	22802	22465	0	0
T91	134574	133867	0	0