Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1114055	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

25429356

1

T1

5542

T2

15228

T3

13201

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	17210304	1			T1	1942		T2	5824		T3	5379
values[0x0]	8218112	1			T1	3600		T2	9404		T3	7822
values[0x1]	1114995	1			T1	136		T2	870		T3	903

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	10187	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

26533224

1

T1

5678

T2

16098

T3

14104

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	13255828	1			T1	2839		T2	8049		T3	7053
valid_sources[0x01]	13254970	1			T1	2839		T2	8049		T3	7051
valid_sources[0x02]	490	1			T56	3		T28	53		T29	104
valid_sources[0x03]	470	1			T46	2		T23	1		T28	45
valid_sources[0x04]	410	1			T28	45		T30	56		T412	55
valid_sources[0x05]	387	1			T28	36		T29	21		T30	22
valid_sources[0x06]	450	1			T23	5		T164	39		T28	39
valid_sources[0x07]	488	1			T56	3		T28	44		T29	119
valid_sources[0x08]	386	1			T46	2		T56	1		T28	47
valid_sources[0x09]	398	1			T28	64		T29	17		T30	19
valid_sources[0x0a]	426	1			T28	34		T29	16		T30	30
valid_sources[0x0b]	446	1			T46	2		T56	1		T28	48
valid_sources[0x0c]	677	1			T28	58		T29	250		T30	30
valid_sources[0x0d]	498	1			T28	48		T29	85		T30	45
valid_sources[0x0e]	668	1			T56	2		T28	44		T29	261
valid_sources[0x0f]	411	1			T46	1		T28	54		T29	16
valid_sources[0x10]	540	1			T23	2		T28	39		T29	111
valid_sources[0x11]	385	1			T46	1		T28	46		T30	14
valid_sources[0x12]	421	1			T46	1		T56	1		T28	47
valid_sources[0x13]	425	1			T28	57		T29	17		T30	28
valid_sources[0x14]	499	1			T56	1		T23	1		T28	44
valid_sources[0x15]	419	1			T28	47		T30	32		T412	56
valid_sources[0x16]	476	1			T46	1		T23	1		T28	48
valid_sources[0x17]	641	1			T28	58		T29	241		T30	19
valid_sources[0x18]	416	1			T46	1		T56	1		T23	2
valid_sources[0x19]	406	1			T46	2		T28	45		T29	16
valid_sources[0x1a]	454	1			T28	52		T29	41		T30	37
valid_sources[0x1b]	566	1			T28	54		T29	138		T30	54
valid_sources[0x1c]	390	1			T46	4		T56	2		T28	43
valid_sources[0x1d]	462	1			T46	1		T23	1		T28	43
valid_sources[0x1e]	454	1			T28	54		T29	49		T30	24
valid_sources[0x1f]	611	1			T28	52		T29	157		T30	28
valid_sources[0x20]	418	1			T28	42		T29	23		T30	21

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

17210304

1

T1

1942

T2

5824

T3

5379

values[0x0]

all_enables

biggest_size

8212841

1

T1

3600

T2

9404

T3

7822

values[0x1]

all_enables

biggest_size

6211

1

T46

20

T55

27

T56

22