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Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio168

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
86.88 90.18 60.26 97.06 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio169

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
86.88 90.18 60.26 97.06 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio170

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
86.88 90.18 60.26 97.06 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio171

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
86.88 90.18 60.26 97.06 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio172

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
86.88 90.18 60.26 97.06 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio173

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
86.88 90.18 60.26 97.06 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio174

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
86.88 90.18 60.26 97.06 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio175

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
86.88 90.18 60.26 97.06 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio176

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
86.88 90.18 60.26 97.06 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio177

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
86.88 90.18 60.26 97.06 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio178

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
86.88 90.18 60.26 97.06 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio179

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
86.88 90.18 60.26 97.06 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio180

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
86.88 90.18 60.26 97.06 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio181

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
86.88 90.18 60.26 97.06 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
72.38 57.14 100.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
68.15 44.44 100.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
86.88 90.18 60.26 97.06 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 0.00 0.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
81.90 85.71 100.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.26 77.78 100.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
86.88 90.18 60.26 97.06 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 50.00 50.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
81.90 85.71 100.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.26 77.78 100.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
86.88 90.18 60.26 97.06 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 50.00 50.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_3

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
81.90 85.71 100.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.26 77.78 100.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
86.88 90.18 60.26 97.06 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 50.00 50.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_4

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
81.90 85.71 100.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.26 77.78 100.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
86.88 90.18 60.26 97.06 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 50.00 50.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_5

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
81.90 85.71 100.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.26 77.78 100.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
86.88 90.18 60.26 97.06 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 50.00 50.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_6

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
81.90 85.71 100.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.26 77.78 100.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
86.88 90.18 60.26 97.06 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 50.00 50.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_7

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
81.90 85.71 100.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.26 77.78 100.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
86.88 90.18 60.26 97.06 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 50.00 50.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_8

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
81.90 85.71 100.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.26 77.78 100.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
86.88 90.18 60.26 97.06 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 50.00 50.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_9

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
81.90 85.71 100.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.26 77.78 100.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
86.88 90.18 60.26 97.06 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 50.00 50.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_10

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
81.90 85.71 100.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.26 77.78 100.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
86.88 90.18 60.26 97.06 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 50.00 50.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_11

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
81.90 85.71 100.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.26 77.78 100.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
86.88 90.18 60.26 97.06 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 50.00 50.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_12

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
81.90 85.71 100.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.26 77.78 100.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
86.88 90.18 60.26 97.06 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 50.00 50.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_13

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
81.90 85.71 100.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.26 77.78 100.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
86.88 90.18 60.26 97.06 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 50.00 50.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_14

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
81.90 85.71 100.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.26 77.78 100.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
86.88 90.18 60.26 97.06 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 50.00 50.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_15

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
81.90 85.71 100.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.26 77.78 100.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
86.88 90.18 60.26 97.06 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 50.00 50.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_16

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
81.90 85.71 100.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.26 77.78 100.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
86.88 90.18 60.26 97.06 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 50.00 50.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_17

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
81.90 85.71 100.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.26 77.78 100.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
86.88 90.18 60.26 97.06 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 50.00 50.00

Go back
Module Instances:
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio168
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio169
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio170
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio171
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio172
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio173
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio174
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio175
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio176
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio177
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio178
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio179
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio180
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio181
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_0
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_1
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_2
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_3
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_4
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_5
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_6
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_7
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_8
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_9
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_10
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_11
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_12
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_13
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_14
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_15
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_16
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_17
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio168
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio168
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT78,T151,T80

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio168
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T78,T151,T80
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T78,T151,T80
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio169
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio169
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT151,T152,T145

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio169
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T151,T152,T145
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T151,T152,T145
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio170
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio170
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT151,T152,T145

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio170
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T151,T152,T145
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T151,T152,T145
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio171
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio171
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT151,T152,T145

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio171
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T151,T152,T145
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T151,T152,T145
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio172
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio172
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT151,T152,T145

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio172
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T151,T152,T145
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T151,T152,T145
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio173
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio173
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT151,T152,T145

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio173
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T151,T152,T145
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T151,T152,T145
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio174
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio174
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT151,T152,T145

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio174
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T151,T152,T145
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T151,T152,T145
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio175
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio175
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT151,T152,T145

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio175
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T151,T152,T145
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T151,T152,T145
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio176
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio176
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT151,T152,T145

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio176
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T151,T152,T145
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T151,T152,T145
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio177
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio177
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT151,T152,T145

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio177
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T151,T152,T145
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T151,T152,T145
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio178
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio178
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT151,T152,T145

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio178
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T151,T152,T145
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T151,T152,T145
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio179
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio179
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT151,T152,T145

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio179
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T151,T152,T145
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T151,T152,T145
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio180
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio180
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT151,T152,T145

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio180
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T151,T152,T145
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T151,T152,T145
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio181
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio181
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT151,T152,T145

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio181
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T151,T152,T145
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T151,T152,T145
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_0
Line No.TotalCoveredPercent
TOTAL7457.14
ALWAYS5644100.00
CONT_ASSIGN64100.00
CONT_ASSIGN65100.00
CONT_ASSIGN72100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
==> MISSING_ELSE
64 0 1
65 0 1
72 0 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_0
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTestsExclude Annotation
0Excluded [UNR] Tied off
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_0
Line No.TotalCoveredPercent
Branches 5 3 60.00
TERNARY 64 2 1 50.00
IF 56 3 2 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_1
Line No.TotalCoveredPercent
TOTAL7685.71
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN65100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
==> MISSING_ELSE
64 1 1
65 0 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_1
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTestsExclude Annotation
0Excluded [UNR] Tied off
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_1
Line No.TotalCoveredPercent
Branches 5 3 60.00
TERNARY 64 2 1 50.00
IF 56 3 2 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_2
Line No.TotalCoveredPercent
TOTAL7685.71
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN65100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
==> MISSING_ELSE
64 1 1
65 0 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_2
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTestsExclude Annotation
0Excluded [UNR] Tied off
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_2
Line No.TotalCoveredPercent
Branches 5 3 60.00
TERNARY 64 2 1 50.00
IF 56 3 2 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_3
Line No.TotalCoveredPercent
TOTAL7685.71
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN65100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
==> MISSING_ELSE
64 1 1
65 0 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_3
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTestsExclude Annotation
0Excluded [UNR] Tied off
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_3
Line No.TotalCoveredPercent
Branches 5 3 60.00
TERNARY 64 2 1 50.00
IF 56 3 2 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_4
Line No.TotalCoveredPercent
TOTAL7685.71
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN65100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
==> MISSING_ELSE
64 1 1
65 0 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_4
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTestsExclude Annotation
0Excluded [UNR] Tied off
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_4
Line No.TotalCoveredPercent
Branches 5 3 60.00
TERNARY 64 2 1 50.00
IF 56 3 2 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_5
Line No.TotalCoveredPercent
TOTAL7685.71
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN65100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
==> MISSING_ELSE
64 1 1
65 0 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_5
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTestsExclude Annotation
0Excluded [UNR] Tied off
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_5
Line No.TotalCoveredPercent
Branches 5 3 60.00
TERNARY 64 2 1 50.00
IF 56 3 2 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_6
Line No.TotalCoveredPercent
TOTAL7685.71
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN65100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
==> MISSING_ELSE
64 1 1
65 0 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_6
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTestsExclude Annotation
0Excluded [UNR] Tied off
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_6
Line No.TotalCoveredPercent
Branches 5 3 60.00
TERNARY 64 2 1 50.00
IF 56 3 2 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_7
Line No.TotalCoveredPercent
TOTAL7685.71
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN65100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
==> MISSING_ELSE
64 1 1
65 0 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_7
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTestsExclude Annotation
0Excluded [UNR] Tied off
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_7
Line No.TotalCoveredPercent
Branches 5 3 60.00
TERNARY 64 2 1 50.00
IF 56 3 2 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_8
Line No.TotalCoveredPercent
TOTAL7685.71
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN65100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
==> MISSING_ELSE
64 1 1
65 0 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_8
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTestsExclude Annotation
0Excluded [UNR] Tied off
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_8
Line No.TotalCoveredPercent
Branches 5 3 60.00
TERNARY 64 2 1 50.00
IF 56 3 2 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_9
Line No.TotalCoveredPercent
TOTAL7685.71
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN65100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
==> MISSING_ELSE
64 1 1
65 0 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_9
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTestsExclude Annotation
0Excluded [UNR] Tied off
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_9
Line No.TotalCoveredPercent
Branches 5 3 60.00
TERNARY 64 2 1 50.00
IF 56 3 2 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_10
Line No.TotalCoveredPercent
TOTAL7685.71
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN65100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
==> MISSING_ELSE
64 1 1
65 0 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_10
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTestsExclude Annotation
0Excluded [UNR] Tied off
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_10
Line No.TotalCoveredPercent
Branches 5 3 60.00
TERNARY 64 2 1 50.00
IF 56 3 2 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_11
Line No.TotalCoveredPercent
TOTAL7685.71
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN65100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
==> MISSING_ELSE
64 1 1
65 0 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_11
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTestsExclude Annotation
0Excluded [UNR] Tied off
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_11
Line No.TotalCoveredPercent
Branches 5 3 60.00
TERNARY 64 2 1 50.00
IF 56 3 2 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_12
Line No.TotalCoveredPercent
TOTAL7685.71
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN65100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
==> MISSING_ELSE
64 1 1
65 0 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_12
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTestsExclude Annotation
0Excluded [UNR] Tied off
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_12
Line No.TotalCoveredPercent
Branches 5 3 60.00
TERNARY 64 2 1 50.00
IF 56 3 2 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_13
Line No.TotalCoveredPercent
TOTAL7685.71
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN65100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
==> MISSING_ELSE
64 1 1
65 0 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_13
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTestsExclude Annotation
0Excluded [UNR] Tied off
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_13
Line No.TotalCoveredPercent
Branches 5 3 60.00
TERNARY 64 2 1 50.00
IF 56 3 2 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_14
Line No.TotalCoveredPercent
TOTAL7685.71
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN65100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
==> MISSING_ELSE
64 1 1
65 0 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_14
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTestsExclude Annotation
0Excluded [UNR] Tied off
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_14
Line No.TotalCoveredPercent
Branches 5 3 60.00
TERNARY 64 2 1 50.00
IF 56 3 2 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_15
Line No.TotalCoveredPercent
TOTAL7685.71
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN65100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
==> MISSING_ELSE
64 1 1
65 0 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_15
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTestsExclude Annotation
0Excluded [UNR] Tied off
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_15
Line No.TotalCoveredPercent
Branches 5 3 60.00
TERNARY 64 2 1 50.00
IF 56 3 2 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_16
Line No.TotalCoveredPercent
TOTAL7685.71
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN65100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
==> MISSING_ELSE
64 1 1
65 0 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_16
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTestsExclude Annotation
0Excluded [UNR] Tied off
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_16
Line No.TotalCoveredPercent
Branches 5 3 60.00
TERNARY 64 2 1 50.00
IF 56 3 2 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_17
Line No.TotalCoveredPercent
TOTAL7685.71
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN65100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
==> MISSING_ELSE
64 1 1
65 0 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_17
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTestsExclude Annotation
0Excluded [UNR] Tied off
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_0_p_17
Line No.TotalCoveredPercent
Branches 5 3 60.00
TERNARY 64 2 1 50.00
IF 56 3 2 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Not Covered

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%