Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	406578375	40635151	0	0
DepthKnown_A	406578375	406480042	0	0
RvalidKnown_A	406578375	406480042	0	0
WreadyKnown_A	406578375	406480042	0	0
gen_passthru_fifo.paramCheckPass	908	908	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	40635151	0	0
T1	132079	14071	0	0
T2	288539	31221	0	0
T3	227982	29589	0	0
T31	244799	17001	0	0
T63	464900	58509	0	0
T65	154347	24740	0	0
T66	143790	22119	0	0
T67	343540	41878	0	0
T99	271503	27761	0	0
T108	210552	22626	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	406480042	0	0
T1	132079	132017	0	0
T2	288539	288383	0	0
T3	227982	227869	0	0
T31	244799	244675	0	0
T63	464900	464784	0	0
T65	154347	154289	0	0
T66	143790	143732	0	0
T67	343540	343485	0	0
T99	271503	271379	0	0
T108	210552	210490	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	406480042	0	0
T1	132079	132017	0	0
T2	288539	288383	0	0
T3	227982	227869	0	0
T31	244799	244675	0	0
T63	464900	464784	0	0
T65	154347	154289	0	0
T66	143790	143732	0	0
T67	343540	343485	0	0
T99	271503	271379	0	0
T108	210552	210490	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	406480042	0	0
T1	132079	132017	0	0
T2	288539	288383	0	0
T3	227982	227869	0	0
T31	244799	244675	0	0
T63	464900	464784	0	0
T65	154347	154289	0	0
T66	143790	143732	0	0
T67	343540	343485	0	0
T99	271503	271379	0	0
T108	210552	210490	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	908	908	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T31	1	1	0	0
T63	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0
T67	1	1	0	0
T99	1	1	0	0
T108	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	406578375	31148524	0	0
DepthKnown_A	406578375	406480042	0	0
RvalidKnown_A	406578375	406480042	0	0
WreadyKnown_A	406578375	406480042	0	0
gen_passthru_fifo.paramCheckPass	908	908	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	31148524	0	0
T1	132079	9420	0	0
T2	288539	23556	0	0
T3	227982	20074	0	0
T31	244799	12935	0	0
T63	464900	53973	0	0
T65	154347	17423	0	0
T66	143790	15403	0	0
T67	343540	32222	0	0
T99	271503	21552	0	0
T108	210552	18706	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	406480042	0	0
T1	132079	132017	0	0
T2	288539	288383	0	0
T3	227982	227869	0	0
T31	244799	244675	0	0
T63	464900	464784	0	0
T65	154347	154289	0	0
T66	143790	143732	0	0
T67	343540	343485	0	0
T99	271503	271379	0	0
T108	210552	210490	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	406480042	0	0
T1	132079	132017	0	0
T2	288539	288383	0	0
T3	227982	227869	0	0
T31	244799	244675	0	0
T63	464900	464784	0	0
T65	154347	154289	0	0
T66	143790	143732	0	0
T67	343540	343485	0	0
T99	271503	271379	0	0
T108	210552	210490	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	406480042	0	0
T1	132079	132017	0	0
T2	288539	288383	0	0
T3	227982	227869	0	0
T31	244799	244675	0	0
T63	464900	464784	0	0
T65	154347	154289	0	0
T66	143790	143732	0	0
T67	343540	343485	0	0
T99	271503	271379	0	0
T108	210552	210490	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	908	908	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T31	1	1	0	0
T63	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0
T67	1	1	0	0
T99	1	1	0	0
T108	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	406578375	27456862	0	0
DepthKnown_A	406578375	406480042	0	0
RvalidKnown_A	406578375	406480042	0	0
WreadyKnown_A	406578375	406480042	0	0
gen_passthru_fifo.paramCheckPass	908	908	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	27456862	0	0
T1	132079	5963	0	0
T2	288539	16561	0	0
T3	227982	14497	0	0
T31	244799	9920	0	0
T63	464900	8513	0	0
T65	154347	8843	0	0
T66	143790	7921	0	0
T67	343540	41663	0	0
T99	271503	12767	0	0
T108	210552	18376	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	406480042	0	0
T1	132079	132017	0	0
T2	288539	288383	0	0
T3	227982	227869	0	0
T31	244799	244675	0	0
T63	464900	464784	0	0
T65	154347	154289	0	0
T66	143790	143732	0	0
T67	343540	343485	0	0
T99	271503	271379	0	0
T108	210552	210490	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	406480042	0	0
T1	132079	132017	0	0
T2	288539	288383	0	0
T3	227982	227869	0	0
T31	244799	244675	0	0
T63	464900	464784	0	0
T65	154347	154289	0	0
T66	143790	143732	0	0
T67	343540	343485	0	0
T99	271503	271379	0	0
T108	210552	210490	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	406480042	0	0
T1	132079	132017	0	0
T2	288539	288383	0	0
T3	227982	227869	0	0
T31	244799	244675	0	0
T63	464900	464784	0	0
T65	154347	154289	0	0
T66	143790	143732	0	0
T67	343540	343485	0	0
T99	271503	271379	0	0
T108	210552	210490	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	908	908	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T31	1	1	0	0
T63	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0
T67	1	1	0	0
T99	1	1	0	0
T108	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	406578375	26610429	0	0
DepthKnown_A	406578375	406480042	0	0
RvalidKnown_A	406578375	406480042	0	0
WreadyKnown_A	406578375	406480042	0	0
gen_passthru_fifo.paramCheckPass	908	908	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	26610429	0	0
T1	132079	5678	0	0
T2	288539	16098	0	0
T3	227982	14104	0	0
T31	244799	9668	0	0
T63	464900	8242	0	0
T65	154347	8570	0	0
T66	143790	7650	0	0
T67	343540	39056	0	0
T99	271503	12481	0	0
T108	210552	17515	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	406480042	0	0
T1	132079	132017	0	0
T2	288539	288383	0	0
T3	227982	227869	0	0
T31	244799	244675	0	0
T63	464900	464784	0	0
T65	154347	154289	0	0
T66	143790	143732	0	0
T67	343540	343485	0	0
T99	271503	271379	0	0
T108	210552	210490	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	406480042	0	0
T1	132079	132017	0	0
T2	288539	288383	0	0
T3	227982	227869	0	0
T31	244799	244675	0	0
T63	464900	464784	0	0
T65	154347	154289	0	0
T66	143790	143732	0	0
T67	343540	343485	0	0
T99	271503	271379	0	0
T108	210552	210490	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	406480042	0	0
T1	132079	132017	0	0
T2	288539	288383	0	0
T3	227982	227869	0	0
T31	244799	244675	0	0
T63	464900	464784	0	0
T65	154347	154289	0	0
T66	143790	143732	0	0
T67	343540	343485	0	0
T99	271503	271379	0	0
T108	210552	210490	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	908	908	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T31	1	1	0	0
T63	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0
T67	1	1	0	0
T99	1	1	0	0
T108	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	406578375	60264	0	0
DepthKnown_A	406578375	406480042	0	0
RvalidKnown_A	406578375	406480042	0	0
WreadyKnown_A	406578375	406480042	0	0
gen_passthru_fifo.paramCheckPass	908	908	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	60264	0	0
T1	132079	39	0	0
T2	288539	68	0	0
T3	227982	151	0	0
T31	244799	29	0	0
T63	464900	30	0	0
T65	154347	26	0	0
T66	143790	26	0	0
T67	343540	14	0	0
T99	271503	35	0	0
T108	210552	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	406480042	0	0
T1	132079	132017	0	0
T2	288539	288383	0	0
T3	227982	227869	0	0
T31	244799	244675	0	0
T63	464900	464784	0	0
T65	154347	154289	0	0
T66	143790	143732	0	0
T67	343540	343485	0	0
T99	271503	271379	0	0
T108	210552	210490	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	406480042	0	0
T1	132079	132017	0	0
T2	288539	288383	0	0
T3	227982	227869	0	0
T31	244799	244675	0	0
T63	464900	464784	0	0
T65	154347	154289	0	0
T66	143790	143732	0	0
T67	343540	343485	0	0
T99	271503	271379	0	0
T108	210552	210490	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	406480042	0	0
T1	132079	132017	0	0
T2	288539	288383	0	0
T3	227982	227869	0	0
T31	244799	244675	0	0
T63	464900	464784	0	0
T65	154347	154289	0	0
T66	143790	143732	0	0
T67	343540	343485	0	0
T99	271503	271379	0	0
T108	210552	210490	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	908	908	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T31	1	1	0	0
T63	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0
T67	1	1	0	0
T99	1	1	0	0
T108	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	406578375	60264	0	0
DepthKnown_A	406578375	406480042	0	0
RvalidKnown_A	406578375	406480042	0	0
WreadyKnown_A	406578375	406480042	0	0
gen_passthru_fifo.paramCheckPass	908	908	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	60264	0	0
T1	132079	39	0	0
T2	288539	68	0	0
T3	227982	151	0	0
T31	244799	29	0	0
T63	464900	30	0	0
T65	154347	26	0	0
T66	143790	26	0	0
T67	343540	14	0	0
T99	271503	35	0	0
T108	210552	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	406480042	0	0
T1	132079	132017	0	0
T2	288539	288383	0	0
T3	227982	227869	0	0
T31	244799	244675	0	0
T63	464900	464784	0	0
T65	154347	154289	0	0
T66	143790	143732	0	0
T67	343540	343485	0	0
T99	271503	271379	0	0
T108	210552	210490	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	406480042	0	0
T1	132079	132017	0	0
T2	288539	288383	0	0
T3	227982	227869	0	0
T31	244799	244675	0	0
T63	464900	464784	0	0
T65	154347	154289	0	0
T66	143790	143732	0	0
T67	343540	343485	0	0
T99	271503	271379	0	0
T108	210552	210490	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	406480042	0	0
T1	132079	132017	0	0
T2	288539	288383	0	0
T3	227982	227869	0	0
T31	244799	244675	0	0
T63	464900	464784	0	0
T65	154347	154289	0	0
T66	143790	143732	0	0
T67	343540	343485	0	0
T99	271503	271379	0	0
T108	210552	210490	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	908	908	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T31	1	1	0	0
T63	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0
T67	1	1	0	0
T99	1	1	0	0
T108	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	406578375	49416	0	0
DepthKnown_A	406578375	406480042	0	0
RvalidKnown_A	406578375	406480042	0	0
WreadyKnown_A	406578375	406480042	0	0
gen_passthru_fifo.paramCheckPass	908	908	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	49416	0	0
T1	132079	32	0	0
T2	288539	63	0	0
T3	227982	95	0	0
T31	244799	25	0	0
T63	464900	28	0	0
T65	154347	23	0	0
T66	143790	23	0	0
T67	343540	13	0	0
T99	271503	29	0	0
T108	210552	19	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	406480042	0	0
T1	132079	132017	0	0
T2	288539	288383	0	0
T3	227982	227869	0	0
T31	244799	244675	0	0
T63	464900	464784	0	0
T65	154347	154289	0	0
T66	143790	143732	0	0
T67	343540	343485	0	0
T99	271503	271379	0	0
T108	210552	210490	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	406480042	0	0
T1	132079	132017	0	0
T2	288539	288383	0	0
T3	227982	227869	0	0
T31	244799	244675	0	0
T63	464900	464784	0	0
T65	154347	154289	0	0
T66	143790	143732	0	0
T67	343540	343485	0	0
T99	271503	271379	0	0
T108	210552	210490	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	406480042	0	0
T1	132079	132017	0	0
T2	288539	288383	0	0
T3	227982	227869	0	0
T31	244799	244675	0	0
T63	464900	464784	0	0
T65	154347	154289	0	0
T66	143790	143732	0	0
T67	343540	343485	0	0
T99	271503	271379	0	0
T108	210552	210490	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	908	908	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T31	1	1	0	0
T63	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0
T67	1	1	0	0
T99	1	1	0	0
T108	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	406578375	49416	0	0
DepthKnown_A	406578375	406480042	0	0
RvalidKnown_A	406578375	406480042	0	0
WreadyKnown_A	406578375	406480042	0	0
gen_passthru_fifo.paramCheckPass	908	908	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	49416	0	0
T1	132079	32	0	0
T2	288539	63	0	0
T3	227982	95	0	0
T31	244799	25	0	0
T63	464900	28	0	0
T65	154347	23	0	0
T66	143790	23	0	0
T67	343540	13	0	0
T99	271503	29	0	0
T108	210552	19	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	406480042	0	0
T1	132079	132017	0	0
T2	288539	288383	0	0
T3	227982	227869	0	0
T31	244799	244675	0	0
T63	464900	464784	0	0
T65	154347	154289	0	0
T66	143790	143732	0	0
T67	343540	343485	0	0
T99	271503	271379	0	0
T108	210552	210490	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	406480042	0	0
T1	132079	132017	0	0
T2	288539	288383	0	0
T3	227982	227869	0	0
T31	244799	244675	0	0
T63	464900	464784	0	0
T65	154347	154289	0	0
T66	143790	143732	0	0
T67	343540	343485	0	0
T99	271503	271379	0	0
T108	210552	210490	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	406480042	0	0
T1	132079	132017	0	0
T2	288539	288383	0	0
T3	227982	227869	0	0
T31	244799	244675	0	0
T63	464900	464784	0	0
T65	154347	154289	0	0
T66	143790	143732	0	0
T67	343540	343485	0	0
T99	271503	271379	0	0
T108	210552	210490	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	908	908	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T31	1	1	0	0
T63	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0
T67	1	1	0	0
T99	1	1	0	0
T108	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	406578375	10848	0	0
DepthKnown_A	406578375	406480042	0	0
RvalidKnown_A	406578375	406480042	0	0
WreadyKnown_A	406578375	406480042	0	0
gen_passthru_fifo.paramCheckPass	908	908	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	10848	0	0
T1	132079	7	0	0
T2	288539	5	0	0
T3	227982	56	0	0
T31	244799	4	0	0
T63	464900	2	0	0
T65	154347	3	0	0
T66	143790	3	0	0
T67	343540	1	0	0
T99	271503	6	0	0
T108	210552	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	406480042	0	0
T1	132079	132017	0	0
T2	288539	288383	0	0
T3	227982	227869	0	0
T31	244799	244675	0	0
T63	464900	464784	0	0
T65	154347	154289	0	0
T66	143790	143732	0	0
T67	343540	343485	0	0
T99	271503	271379	0	0
T108	210552	210490	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	406480042	0	0
T1	132079	132017	0	0
T2	288539	288383	0	0
T3	227982	227869	0	0
T31	244799	244675	0	0
T63	464900	464784	0	0
T65	154347	154289	0	0
T66	143790	143732	0	0
T67	343540	343485	0	0
T99	271503	271379	0	0
T108	210552	210490	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	406480042	0	0
T1	132079	132017	0	0
T2	288539	288383	0	0
T3	227982	227869	0	0
T31	244799	244675	0	0
T63	464900	464784	0	0
T65	154347	154289	0	0
T66	143790	143732	0	0
T67	343540	343485	0	0
T99	271503	271379	0	0
T108	210552	210490	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	908	908	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T31	1	1	0	0
T63	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0
T67	1	1	0	0
T99	1	1	0	0
T108	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	406578375	10848	0	0
DepthKnown_A	406578375	406480042	0	0
RvalidKnown_A	406578375	406480042	0	0
WreadyKnown_A	406578375	406480042	0	0
gen_passthru_fifo.paramCheckPass	908	908	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	10848	0	0
T1	132079	7	0	0
T2	288539	5	0	0
T3	227982	56	0	0
T31	244799	4	0	0
T63	464900	2	0	0
T65	154347	3	0	0
T66	143790	3	0	0
T67	343540	1	0	0
T99	271503	6	0	0
T108	210552	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	406480042	0	0
T1	132079	132017	0	0
T2	288539	288383	0	0
T3	227982	227869	0	0
T31	244799	244675	0	0
T63	464900	464784	0	0
T65	154347	154289	0	0
T66	143790	143732	0	0
T67	343540	343485	0	0
T99	271503	271379	0	0
T108	210552	210490	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	406480042	0	0
T1	132079	132017	0	0
T2	288539	288383	0	0
T3	227982	227869	0	0
T31	244799	244675	0	0
T63	464900	464784	0	0
T65	154347	154289	0	0
T66	143790	143732	0	0
T67	343540	343485	0	0
T99	271503	271379	0	0
T108	210552	210490	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	406480042	0	0
T1	132079	132017	0	0
T2	288539	288383	0	0
T3	227982	227869	0	0
T31	244799	244675	0	0
T63	464900	464784	0	0
T65	154347	154289	0	0
T66	143790	143732	0	0
T67	343540	343485	0	0
T99	271503	271379	0	0
T108	210552	210490	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	908	908	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T31	1	1	0	0
T63	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0
T67	1	1	0	0
T99	1	1	0	0
T108	1	1	0	0