Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : sram_ctrl
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.96 93.96

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_sram_ctrl_main 88.85 88.85
tb.dut.top_earlgrey.u_sram_ctrl_ret_aon 94.53 94.53


Module Instance : tb.dut.top_earlgrey.u_sram_ctrl_main

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.85 88.85


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.85 88.85


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.60 92.83 90.98 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_sram_ctrl_ret_aon

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.53 94.53


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.53 94.53


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.60 92.83 90.98 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : sram_ctrl
TotalCoveredPercent
Totals 64 45 70.31
Total Bits 1158 1088 93.96
Total Bits 0->1 579 544 93.96
Total Bits 1->0 579 544 93.96

Ports 64 45 70.31
Port Bits 1158 1088 93.96
Port Bits 0->1 579 544 93.96
Port Bits 1->0 579 544 93.96

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T31 Yes T1,T2,T3 INPUT
clk_otp_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_otp_ni Yes Yes T2,T3,T31 Yes T1,T2,T3 INPUT
ram_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[1:0] No No No INPUT
ram_tl_i.a_address[16:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[20:17] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[22:21] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[27:23] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[28] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[29] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_source[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_size[1:0] Yes Yes T28,T29,T30 Yes T28,T29,T30 INPUT
ram_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_opcode[1] No No No INPUT
ram_tl_i.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_error Yes Yes T1,T2,T3 Yes T2,T3,T31 OUTPUT
ram_tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_user.rsp_intg[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_user.rsp_intg[3] No No No OUTPUT
ram_tl_o.d_user.rsp_intg[5:4] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_user.rsp_intg[6] No No No OUTPUT
ram_tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_sink No No No OUTPUT
ram_tl_o.d_source[4:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_source[5] No No No OUTPUT
ram_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_size[0] No No No OUTPUT
ram_tl_o.d_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
regs_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.data_intg[6:0] Yes Yes T2,T70,T94 Yes T2,T70,T94 INPUT
regs_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.instr_type[2:1] No No No INPUT
regs_tl_i.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_data[31:0] Yes Yes T2,T70,T94 Yes T2,T70,T94 INPUT
regs_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[1:0] No No No INPUT
regs_tl_i.a_address[4:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[17:5] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[20:18] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[21] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[22] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[23] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[24] Yes Yes *T133,*T70,*T94 Yes T133,T70,T94 INPUT
regs_tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_source[5:0] Yes Yes *T54,*T46,*T55 Yes T54,T46,T55 INPUT
regs_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_size[1:0] Yes Yes T28,T29,T30 Yes T28,T29,T30 INPUT
regs_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_opcode[0] Yes Yes *T46,*T55,*T56 Yes T46,T55,T56 INPUT
regs_tl_i.a_opcode[1] No No No INPUT
regs_tl_i.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_valid Yes Yes T2,T133,T70 Yes T2,T133,T70 INPUT
regs_tl_o.a_ready Yes Yes T2,T133,T70 Yes T2,T133,T70 OUTPUT
regs_tl_o.d_error No No No OUTPUT
regs_tl_o.d_user.data_intg[5:0] Yes Yes T2,T70,T206 Yes T2,T70,T206 OUTPUT
regs_tl_o.d_user.data_intg[6] No No No OUTPUT
regs_tl_o.d_user.rsp_intg[1:0] Yes Yes T2,T70,T206 Yes T2,T70,T94 OUTPUT
regs_tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
regs_tl_o.d_user.rsp_intg[5:4] Yes Yes T2,T70,T206 Yes T2,T133,T70 OUTPUT
regs_tl_o.d_user.rsp_intg[6] No No No OUTPUT
regs_tl_o.d_data[31:0] Yes Yes T2,T70,T206 Yes T2,T70,T94 OUTPUT
regs_tl_o.d_sink No No No OUTPUT
regs_tl_o.d_source[0] No No No OUTPUT
regs_tl_o.d_source[1] Yes Yes *T2,*T70,*T206 Yes T2,T70,T116 OUTPUT
regs_tl_o.d_source[5:2] No No No OUTPUT
regs_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_size[0] No No No OUTPUT
regs_tl_o.d_size[1] Yes Yes T2,T70,T206 Yes T2,T133,T70 OUTPUT
regs_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_opcode[0] Yes Yes *T2,*T70,*T206 Yes T2,T133,T70 OUTPUT
regs_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_valid Yes Yes T2,T133,T70 Yes T2,T133,T70 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T133,T94,T106 Yes T133,T94,T106 INPUT
alert_rx_i[0].ping_n Yes Yes T106,T328,T107 Yes T106,T328,T107 INPUT
alert_rx_i[0].ping_p Yes Yes T106,T328,T107 Yes T106,T328,T107 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T133,T94,T106 Yes T133,T94,T106 OUTPUT
lc_escalate_en_i[3:0] Yes Yes T3,T31,T99 Yes T3,T31,T99 INPUT
lc_hw_debug_en_i[3:0] Yes Yes T2,T3,T31 Yes T1,T2,T3 INPUT
otp_en_sram_ifetch_i[7:0] Yes Yes T1,T2,T3 Yes T2,T3,T31 INPUT
sram_otp_key_o.req Yes Yes T2,T70,T206 Yes T2,T70,T206 OUTPUT
sram_otp_key_i.seed_valid Yes Yes T2,T3,T31 Yes T1,T2,T3 INPUT
sram_otp_key_i.nonce[127:0] Yes Yes T1,T2,T31 Yes T1,T2,T67 INPUT
sram_otp_key_i.key[127:0] Yes Yes T1,T2,T3 Yes T2,T3,T31 INPUT
sram_otp_key_i.ack Yes Yes T2,T70,T206 Yes T2,T70,T206 INPUT
cfg_i.rf_cfg.cfg[3:0] No No No INPUT
cfg_i.rf_cfg.cfg_en No No No INPUT
cfg_i.ram_cfg.cfg[3:0] No No No INPUT
cfg_i.ram_cfg.cfg_en No No No INPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_sram_ctrl_main
TotalCoveredPercent
Totals 60 39 65.00
Total Bits 1130 1004 88.85
Total Bits 0->1 565 502 88.85
Total Bits 1->0 565 502 88.85

Ports 60 39 65.00
Port Bits 1130 1004 88.85
Port Bits 0->1 565 502 88.85
Port Bits 1->0 565 502 88.85

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T31 Yes T1,T2,T3 INPUT
clk_otp_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_otp_ni Yes Yes T2,T3,T31 Yes T1,T2,T3 INPUT
ram_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[1:0] No No No INPUT
ram_tl_i.a_address[16:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[27:17] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[28] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[31:29] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_source[4:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_source[5] No No No INPUT
ram_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_size[0] No No No INPUT
ram_tl_i.a_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_opcode[1] No No No INPUT
ram_tl_i.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_error Yes Yes T1,T2,T3 Yes T2,T3,T31 OUTPUT
ram_tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_user.rsp_intg[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_user.rsp_intg[3] No No No OUTPUT
ram_tl_o.d_user.rsp_intg[5:4] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_user.rsp_intg[6] No No No OUTPUT
ram_tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_sink No No No OUTPUT
ram_tl_o.d_source[4:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_source[5] No No No OUTPUT
ram_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_size[0] No No No OUTPUT
ram_tl_o.d_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
regs_tl_i.d_ready Yes Yes T2,T3,T31 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.data_intg[6:0] Yes Yes T70,T94,T95 Yes T70,T94,T95 INPUT
regs_tl_i.a_user.cmd_intg[0] Yes Yes *T133,*T70,*T94 Yes T133,T70,T94 INPUT
regs_tl_i.a_user.cmd_intg[1] No No No INPUT
regs_tl_i.a_user.cmd_intg[6:2] Yes Yes T133,T70,T116 Yes T133,T70,T116 INPUT
regs_tl_i.a_user.instr_type[0] Yes Yes *T133,*T70,*T94 Yes T133,T70,T94 INPUT
regs_tl_i.a_user.instr_type[2:1] No No No INPUT
regs_tl_i.a_user.instr_type[3] Yes Yes T133,T70,T94 Yes T133,T70,T94 INPUT
regs_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_data[3:0] Yes Yes *T70,*T94,*T95 Yes T70,T94,T95 INPUT
regs_tl_i.a_data[31:4] No No No INPUT
regs_tl_i.a_mask[3:0] Yes Yes T133,T70,T94 Yes T133,T70,T94 INPUT
regs_tl_i.a_address[1:0] No No No INPUT
regs_tl_i.a_address[4:2] Yes Yes *T133,*T70,*T116 Yes T133,T70,T116 INPUT
regs_tl_i.a_address[17:5] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[20:18] Yes Yes T133,T70,T94 Yes T133,T70,T94 INPUT
regs_tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[24] Yes Yes *T133,*T70,*T94 Yes T133,T70,T94 INPUT
regs_tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[30] Yes Yes *T133,*T70,*T94 Yes T133,T70,T94 INPUT
regs_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_source[0] No No No INPUT
regs_tl_i.a_source[1] Yes Yes *T70,*T116,*T169 Yes T70,T116,T169 INPUT
regs_tl_i.a_source[5:2] No No No INPUT
regs_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_size[0] No No No INPUT
regs_tl_i.a_size[1] Yes Yes T133,T70,T94 Yes T133,T70,T94 INPUT
regs_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_opcode[1:0] No No No INPUT
regs_tl_i.a_opcode[2] Yes Yes T133,T70,T116 Yes T133,T70,T116 INPUT
regs_tl_i.a_valid Yes Yes T133,T70,T94 Yes T133,T70,T94 INPUT
regs_tl_o.a_ready Yes Yes T133,T70,T94 Yes T133,T70,T94 OUTPUT
regs_tl_o.d_error No No No OUTPUT
regs_tl_o.d_user.data_intg[5:0] Yes Yes *T170,*T171,*T172 Yes T170,T171,T172 OUTPUT
regs_tl_o.d_user.data_intg[6] No No No OUTPUT
regs_tl_o.d_user.rsp_intg[1:0] Yes Yes T70,T169,T170 Yes T70,T94,T95 OUTPUT
regs_tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
regs_tl_o.d_user.rsp_intg[5:4] Yes Yes T70,T169,T170 Yes T133,T70,T94 OUTPUT
regs_tl_o.d_user.rsp_intg[6] No No No OUTPUT
regs_tl_o.d_data[31:0] Yes Yes T70,T169,T170 Yes T70,T94,T95 OUTPUT
regs_tl_o.d_sink No No No OUTPUT
regs_tl_o.d_source[0] No No No OUTPUT
regs_tl_o.d_source[1] Yes Yes *T70,*T169,*T170 Yes T70,T116,T169 OUTPUT
regs_tl_o.d_source[5:2] No No No OUTPUT
regs_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_size[0] No No No OUTPUT
regs_tl_o.d_size[1] Yes Yes T70,T169,T170 Yes T133,T70,T94 OUTPUT
regs_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_opcode[0] Yes Yes *T70,*T169,*T170 Yes T133,T70,T116 OUTPUT
regs_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_valid Yes Yes T133,T70,T94 Yes T133,T70,T94 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T133,T94,T106 Yes T133,T94,T106 INPUT
alert_rx_i[0].ping_n Yes Yes T106,T328,T107 Yes T106,T328,T107 INPUT
alert_rx_i[0].ping_p Yes Yes T106,T328,T107 Yes T106,T328,T107 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T133,T94,T106 Yes T133,T94,T106 OUTPUT
lc_escalate_en_i[3:0] Yes Yes T3,T31,T99 Yes T3,T31,T99 INPUT
lc_hw_debug_en_i[3:0] Yes Yes T2,T3,T31 Yes T1,T2,T3 INPUT
otp_en_sram_ifetch_i[7:0] Yes Yes T1,T2,T3 Yes T2,T3,T31 INPUT
sram_otp_key_o.req Yes Yes T70,T169,T205 Yes T70,T169,T205 OUTPUT
sram_otp_key_i.seed_valid Yes Yes T2,T3,T31 Yes T1,T2,T3 INPUT
sram_otp_key_i.nonce[127:0] Yes Yes T1,T2,T31 Yes T1,T2,T67 INPUT
sram_otp_key_i.key[127:0] Yes Yes T1,T2,T3 Yes T2,T3,T31 INPUT
sram_otp_key_i.ack Yes Yes T70,T169,T205 Yes T70,T169,T205 INPUT
cfg_i.rf_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.rf_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_sram_ctrl_ret_aon
TotalCoveredPercent
Totals 58 42 72.41
Total Bits 1096 1036 94.53
Total Bits 0->1 548 518 94.53
Total Bits 1->0 548 518 94.53

Ports 58 42 72.41
Port Bits 1096 1036 94.53
Port Bits 0->1 548 518 94.53
Port Bits 1->0 548 518 94.53

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T31 Yes T1,T2,T3 INPUT
clk_otp_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_otp_ni Yes Yes T2,T3,T31 Yes T1,T2,T3 INPUT
ram_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.data_intg[6:0] Yes Yes T2,T3,T31 Yes T2,T3,T31 INPUT
ram_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.instr_type[2:1] No No No INPUT
ram_tl_i.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[1:0] No No No INPUT
ram_tl_i.a_address[11:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[20:12] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[22:21] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[29:23] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_source[5:0] Yes Yes *T54,*T46,*T55 Yes T54,T46,T55 INPUT
ram_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_size[1:0] Yes Yes T28,T29,T30 Yes T28,T29,T30 INPUT
ram_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_opcode[0] Yes Yes *T46,*T55,*T56 Yes T46,T55,T56 INPUT
ram_tl_i.a_opcode[1] No No No INPUT
ram_tl_i.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_error Yes Yes T1,T2,T3 Yes T2,T3,T31 OUTPUT
ram_tl_o.d_user.data_intg[6:0] Yes Yes T2,T3,T31 Yes T2,T3,T31 OUTPUT
ram_tl_o.d_user.rsp_intg[2:0] Yes Yes T2,T3,T31 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_user.rsp_intg[3] No No No OUTPUT
ram_tl_o.d_user.rsp_intg[5:4] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_user.rsp_intg[6] No No No OUTPUT
ram_tl_o.d_data[31:0] Yes Yes T2,T3,T31 Yes T2,T3,T31 OUTPUT
ram_tl_o.d_sink No No No OUTPUT
ram_tl_o.d_source[1:0] Yes Yes *T55,*T56,*T132 Yes T55,T56,T132 OUTPUT
ram_tl_o.d_source[5:2] No No No OUTPUT
ram_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_size[0] No No No OUTPUT
ram_tl_o.d_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
regs_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.data_intg[6:0] Yes Yes T2,T70,T116 Yes T2,T70,T116 INPUT
regs_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.instr_type[2:1] No No No INPUT
regs_tl_i.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_data[31:0] Yes Yes T2,T70,T116 Yes T2,T70,T116 INPUT
regs_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[1:0] No No No INPUT
regs_tl_i.a_address[4:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[19:5] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[20] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[21] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[22] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[29:23] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_source[5:0] Yes Yes *T54,*T46,*T55 Yes T54,T46,T55 INPUT
regs_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_size[1:0] Yes Yes T28,T29,T30 Yes T28,T29,T30 INPUT
regs_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_opcode[0] Yes Yes *T46,*T55,*T56 Yes T46,T55,T56 INPUT
regs_tl_i.a_opcode[1] No No No INPUT
regs_tl_i.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_valid Yes Yes T2,T70,T94 Yes T2,T70,T94 INPUT
regs_tl_o.a_ready Yes Yes T2,T70,T94 Yes T2,T70,T94 OUTPUT
regs_tl_o.d_error No No No OUTPUT
regs_tl_o.d_user.data_intg[5:0] Yes Yes T2,*T70,T206 Yes T2,T70,T206 OUTPUT
regs_tl_o.d_user.data_intg[6] No No No OUTPUT
regs_tl_o.d_user.rsp_intg[1:0] Yes Yes T2,T70,T206 Yes T2,T70,T94 OUTPUT
regs_tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
regs_tl_o.d_user.rsp_intg[5:4] Yes Yes T2,T206,T298 Yes T2,T70,T94 OUTPUT
regs_tl_o.d_user.rsp_intg[6] No No No OUTPUT
regs_tl_o.d_data[31:0] Yes Yes T2,T70,T206 Yes T2,T70,T94 OUTPUT
regs_tl_o.d_sink No No No OUTPUT
regs_tl_o.d_source[0] No No No OUTPUT
regs_tl_o.d_source[1] Yes Yes *T2,*T70,*T206 Yes T2,T70,T206 OUTPUT
regs_tl_o.d_source[5:2] No No No OUTPUT
regs_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_size[0] No No No OUTPUT
regs_tl_o.d_size[1] Yes Yes T2,T206,T298 Yes T2,T70,T94 OUTPUT
regs_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_opcode[0] Yes Yes *T2,*T70,*T206 Yes T2,T70,T116 OUTPUT
regs_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_valid Yes Yes T2,T70,T94 Yes T2,T70,T94 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T94,T106,T95 Yes T94,T106,T95 INPUT
alert_rx_i[0].ping_n Yes Yes T106,T107,T175 Yes T106,T107,T175 INPUT
alert_rx_i[0].ping_p Yes Yes T106,T107,T175 Yes T106,T107,T175 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T94,T106,T95 Yes T94,T106,T95 OUTPUT
lc_escalate_en_i[3:0] Yes Yes T3,T31,T99 Yes T3,T31,T99 INPUT
lc_hw_debug_en_i[3:0] Unreachable Unreachable Unreachable INPUT
otp_en_sram_ifetch_i[7:0] Unreachable Unreachable Unreachable INPUT
sram_otp_key_o.req Yes Yes T2,T70,T206 Yes T2,T70,T206 OUTPUT
sram_otp_key_i.seed_valid Yes Yes T2,T3,T31 Yes T1,T2,T3 INPUT
sram_otp_key_i.nonce[127:0] Yes Yes T1,T2,T31 Yes T1,T2,T67 INPUT
sram_otp_key_i.key[127:0] Yes Yes T1,T2,T3 Yes T2,T3,T31 INPUT
sram_otp_key_i.ack Yes Yes T2,T70,T206 Yes T2,T70,T206 INPUT
cfg_i.rf_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.rf_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%