Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.20			90.20

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	90.07			90.07
tb.dut.top_earlgrey.u_uart1	90.13			90.13
tb.dut.top_earlgrey.u_uart2	90.13			90.13
tb.dut.top_earlgrey.u_uart3	90.20			90.20

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.07			90.07

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.07			90.07

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.60	92.83		90.98			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.13			90.13

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.13			90.13

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.60	92.83		90.98			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.13			90.13

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.13			90.13

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.60	92.83		90.98			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.20			90.20

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.20			90.20

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.60	92.83		90.98			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	39	31	79.49
Total Bits	306	276	90.20
Total Bits 0->1	153	138	90.20
Total Bits 1->0	153	138	90.20

Ports	39	31	79.49
Port Bits	306	276	90.20
Port Bits 0->1	153	138	90.20
Port Bits 1->0	153	138	90.20

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T31	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T31,T244,T125	Yes	T31,T244,T125	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T31,T244,T125	Yes	T31,T244,T125	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T54,*T46,*T55	Yes	T54,T46,T55	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T46,*T55,*T56	Yes	T46,T55,T56	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T31,T244,T125	Yes	T31,T244,T125	INPUT
tl_o.a_ready	Yes	Yes	T244,T125,T245	Yes	T244,T125,T245	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T244,T125,T247	Yes	T244,T125,T247	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T244,T125,T245	Yes	T244,T125,T245	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T144,*T104,*T150	Yes	T244,T125,T245	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T244,T125,T245	Yes	T244,T125,T245	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T23,*T244,*T125	Yes	T23,T244,T125	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T144,T104,T150	Yes	T244,T125,T245	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T244,*T125,*T245	Yes	T244,T125,T245	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T244,T125,T245	Yes	T244,T125,T245	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T65,T338,T339	Yes	T65,T338,T339	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T106,T328,T107	Yes	T106,T328,T107	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T106,T328,T107	Yes	T106,T328,T107	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T65,T338,T339	Yes	T65,T338,T339	OUTPUT
cio_rx_i	Yes	Yes	T2,T3,T31	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T244,T125,T247	Yes	T244,T125,T247	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T244,T125,T247	Yes	T244,T125,T247	OUTPUT
intr_rx_watermark_o	Yes	Yes	T244,T125,T247	Yes	T244,T125,T247	OUTPUT
intr_tx_empty_o	Yes	Yes	T244,T125,T245	Yes	T244,T125,T245	OUTPUT
intr_rx_overflow_o	Yes	Yes	T244,T125,T245	Yes	T244,T125,T245	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T151,T214,T215	Yes	T151,T214,T215	OUTPUT
intr_rx_break_err_o	Yes	Yes	T151,T214,T215	Yes	T151,T214,T215	OUTPUT
intr_rx_timeout_o	Yes	Yes	T151,T214,T215	Yes	T151,T214,T215	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T151,T214,T215	Yes	T151,T214,T215	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	39	31	79.49
Total Bits	302	272	90.07
Total Bits 0->1	151	136	90.07
Total Bits 1->0	151	136	90.07

Ports	39	31	79.49
Port Bits	302	272	90.07
Port Bits 0->1	151	136	90.07
Port Bits 1->0	151	136	90.07

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T31	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T31,T244,T125	Yes	T31,T244,T125	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T31,T244,T125	Yes	T31,T244,T125	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T54,*T46,*T55	Yes	T54,T46,T55	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T46,*T55,*T56	Yes	T46,T55,T56	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T31,T244,T125	Yes	T31,T244,T125	INPUT
tl_o.a_ready	Yes	Yes	T244,T125,T245	Yes	T244,T125,T245	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T244,T125,T151	Yes	T244,T125,T151	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T244,T125,T245	Yes	T244,T125,T245	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T144,*T104,*T150	Yes	T244,T125,T245	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T244,T125,T245	Yes	T244,T125,T245	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T23,*T244,*T125	Yes	T23,T244,T125	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T144,T104,T150	Yes	T244,T125,T245	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T244,*T125,*T245	Yes	T244,T125,T245	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T244,T125,T245	Yes	T244,T125,T245	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T65,T94,T104	Yes	T65,T94,T104	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T106,T328,T107	Yes	T106,T328,T107	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T106,T328,T107	Yes	T106,T328,T107	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T65,T94,T104	Yes	T65,T94,T104	OUTPUT
cio_rx_i	Yes	Yes	T2,T3,T31	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T244,T125,T264	Yes	T244,T125,T264	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T244,T125,T151	Yes	T244,T125,T151	OUTPUT
intr_rx_watermark_o	Yes	Yes	T244,T125,T151	Yes	T244,T125,T151	OUTPUT
intr_tx_empty_o	Yes	Yes	T244,T125,T245	Yes	T244,T125,T245	OUTPUT
intr_rx_overflow_o	Yes	Yes	T244,T125,T245	Yes	T244,T125,T245	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T151,T214,T215	Yes	T151,T214,T215	OUTPUT
intr_rx_break_err_o	Yes	Yes	T151,T214,T215	Yes	T151,T214,T215	OUTPUT
intr_rx_timeout_o	Yes	Yes	T151,T214,T215	Yes	T151,T214,T215	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T151,T214,T215	Yes	T151,T214,T215	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	39	31	79.49
Total Bits	304	274	90.13
Total Bits 0->1	152	137	90.13
Total Bits 1->0	152	137	90.13

Ports	39	31	79.49
Port Bits	304	274	90.13
Port Bits 0->1	152	137	90.13
Port Bits 1->0	152	137	90.13

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T31	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T151,T246,T119	Yes	T151,T246,T119	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T151,T246,T119	Yes	T151,T246,T119	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T54,*T46,*T55	Yes	T54,T46,T55	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T46,*T55,*T56	Yes	T46,T55,T56	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T151,T94,T104	Yes	T151,T94,T104	INPUT
tl_o.a_ready	Yes	Yes	T151,T94,T104	Yes	T151,T94,T104	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T151,T246,T119	Yes	T151,T246,T119	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T151,T104,T246	Yes	T151,T94,T104	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T104,*T150,T23	Yes	T151,T94,T104	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T151,T104,T246	Yes	T151,T94,T104	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T23,*T151,*T246	Yes	T23,T151,T246	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T104,T150,T23	Yes	T151,T94,T104	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T151,*T246,*T119	Yes	T151,T246,T119	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T151,T94,T104	Yes	T151,T94,T104	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T339,T94,T104	Yes	T339,T94,T104	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T106,T328,T107	Yes	T106,T328,T107	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T106,T328,T107	Yes	T106,T328,T107	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T339,T94,T104	Yes	T339,T94,T104	OUTPUT
cio_rx_i	Yes	Yes	T246,T119,T260	Yes	T246,T119,T260	INPUT
cio_tx_o	Yes	Yes	T246,T119,T260	Yes	T246,T119,T260	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T151,T246,T119	Yes	T151,T246,T119	OUTPUT
intr_rx_watermark_o	Yes	Yes	T151,T246,T119	Yes	T151,T246,T119	OUTPUT
intr_tx_empty_o	Yes	Yes	T151,T246,T119	Yes	T151,T246,T119	OUTPUT
intr_rx_overflow_o	Yes	Yes	T151,T246,T119	Yes	T151,T246,T119	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T151,T214,T215	Yes	T151,T214,T215	OUTPUT
intr_rx_break_err_o	Yes	Yes	T151,T214,T215	Yes	T151,T214,T215	OUTPUT
intr_rx_timeout_o	Yes	Yes	T151,T214,T215	Yes	T151,T214,T215	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T151,T214,T215	Yes	T151,T214,T215	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	39	31	79.49
Total Bits	304	274	90.13
Total Bits 0->1	152	137	90.13
Total Bits 1->0	152	137	90.13

Ports	39	31	79.49
Port Bits	304	274	90.13
Port Bits 0->1	152	137	90.13
Port Bits 1->0	152	137	90.13

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T31	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T247,T151,T248	Yes	T247,T151,T248	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T247,T151,T248	Yes	T247,T151,T248	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T54,*T46,*T55	Yes	T54,T46,T55	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T46,*T55,*T56	Yes	T46,T55,T56	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T247,T151,T248	Yes	T247,T151,T248	INPUT
tl_o.a_ready	Yes	Yes	T247,T151,T248	Yes	T247,T151,T248	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T247,T151,T248	Yes	T247,T151,T248	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T247,T151,T248	Yes	T247,T151,T248	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T104,*T150,T23	Yes	T247,T151,T248	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T247,T151,T248	Yes	T247,T151,T248	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T23,*T247,*T151	Yes	T23,T247,T151	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T104,T150,T23	Yes	T247,T151,T248	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T247,*T151,*T248	Yes	T247,T151,T248	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T247,T151,T248	Yes	T247,T151,T248	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T94,T104,T340	Yes	T94,T104,T340	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T106,T107,T175	Yes	T106,T107,T175	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T106,T107,T175	Yes	T106,T107,T175	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T94,T104,T340	Yes	T94,T104,T340	OUTPUT
cio_rx_i	Yes	Yes	T247,T46,T248	Yes	T247,T46,T248	INPUT
cio_tx_o	Yes	Yes	T247,T248,T341	Yes	T247,T248,T341	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T247,T151,T248	Yes	T247,T151,T248	OUTPUT
intr_rx_watermark_o	Yes	Yes	T247,T151,T248	Yes	T247,T151,T248	OUTPUT
intr_tx_empty_o	Yes	Yes	T247,T151,T248	Yes	T247,T151,T248	OUTPUT
intr_rx_overflow_o	Yes	Yes	T247,T151,T248	Yes	T247,T151,T248	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T151,T214,T215	Yes	T151,T214,T215	OUTPUT
intr_rx_break_err_o	Yes	Yes	T151,T214,T215	Yes	T151,T214,T215	OUTPUT
intr_rx_timeout_o	Yes	Yes	T151,T214,T215	Yes	T151,T214,T215	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T151,T214,T215	Yes	T151,T214,T215	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	39	31	79.49
Total Bits	306	276	90.20
Total Bits 0->1	153	138	90.20
Total Bits 1->0	153	138	90.20

Ports	39	31	79.49
Port Bits	306	276	90.20
Port Bits 0->1	153	138	90.20
Port Bits 1->0	153	138	90.20

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T31	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T151,T249,T250	Yes	T151,T249,T250	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T151,T249,T250	Yes	T151,T249,T250	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T54,*T46,*T55	Yes	T54,T46,T55	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T46,*T55,*T56	Yes	T46,T55,T56	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T151,T249,T250	Yes	T151,T249,T250	INPUT
tl_o.a_ready	Yes	Yes	T151,T249,T250	Yes	T151,T249,T250	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T151,T249,T250	Yes	T151,T249,T250	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T151,T249,T250	Yes	T151,T249,T250	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T104,*T150,T23	Yes	T151,T249,T250	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T151,T249,T250	Yes	T151,T249,T250	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T23,*T151,*T249	Yes	T23,T151,T249	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T104,T150,T23	Yes	T151,T249,T250	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T151,*T249,*T250	Yes	T151,T249,T250	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T151,T249,T250	Yes	T151,T249,T250	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T338,T94,T104	Yes	T338,T94,T104	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T106,T107,T175	Yes	T106,T107,T175	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T106,T107,T175	Yes	T106,T107,T175	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T338,T94,T104	Yes	T338,T94,T104	OUTPUT
cio_rx_i	Yes	Yes	T249,T250,T342	Yes	T249,T250,T342	INPUT
cio_tx_o	Yes	Yes	T249,T250,T342	Yes	T249,T250,T342	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T151,T249,T250	Yes	T151,T249,T250	OUTPUT
intr_rx_watermark_o	Yes	Yes	T151,T249,T250	Yes	T151,T249,T250	OUTPUT
intr_tx_empty_o	Yes	Yes	T151,T249,T250	Yes	T151,T249,T250	OUTPUT
intr_rx_overflow_o	Yes	Yes	T151,T249,T250	Yes	T151,T249,T250	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T151,T214,T215	Yes	T151,T214,T215	OUTPUT
intr_rx_break_err_o	Yes	Yes	T151,T214,T215	Yes	T151,T214,T215	OUTPUT
intr_rx_timeout_o	Yes	Yes	T151,T214,T215	Yes	T151,T214,T215	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T151,T214,T215	Yes	T151,T214,T215	OUTPUT

*Tests covering at least one bit in the range