dashboard | hierarchy | modlist | groups | tests | asserts

Module Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[5].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[6].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[7].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[8].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[9].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[10].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[11].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[12].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[13].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[14].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[15].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[16].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[17].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[18].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[19].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[20].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[21].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[22].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[22].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[23].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[23].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[24].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[24].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[25].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[25].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[26].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[26].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[27].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[27].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[28].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[28].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[29].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[29].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[30].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[30].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[31].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[31].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[32].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[32].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[33].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[33].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[22].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[23].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[24].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[25].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[26].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[27].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[28].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[29].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[30].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[31].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[32].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[33].u_mio_pad.gen_generic.u_impl_generic
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT14,T15,T16
01CoveredT14,T15,T16
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T29,T30
10CoveredT14,T15,T16
11CoveredT28,T29,T30

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT14,T15,T16

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT28,T29,T30
01CoveredT1,T2,T3
10CoveredT28,T29,T30

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT28,T29,T30
10CoveredT14,T15,T16
11CoveredT28,T29,T30

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT14,T15,T16

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT14,T15,T16

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T14,T15,T16
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 908 908 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 908 908 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T31 1 1 0 0
T63 1 1 0 0
T65 1 1 0 0
T66 1 1 0 0
T67 1 1 0 0
T99 1 1 0 0
T108 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT14,T15,T16
01CoveredT14,T15,T16
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T29,T30
10CoveredT14,T15,T16
11CoveredT28,T29,T30

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT14,T15,T16

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT28,T29,T30
01CoveredT1,T2,T3
10CoveredT28,T29,T30

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT28,T29,T30
10CoveredT14,T15,T16
11CoveredT28,T29,T30

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT14,T15,T16

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT14,T15,T16

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T14,T15,T16
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 908 908 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 908 908 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T31 1 1 0 0
T63 1 1 0 0
T65 1 1 0 0
T66 1 1 0 0
T67 1 1 0 0
T99 1 1 0 0
T108 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT14,T15,T16
01CoveredT14,T15,T16
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T29,T30
10CoveredT14,T15,T16
11CoveredT28,T29,T30

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT14,T15,T16

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT28,T29,T30
01CoveredT1,T2,T3
10CoveredT28,T29,T30

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT29,T30,T412

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT28,T29,T30
10CoveredT14,T15,T16
11CoveredT29,T30,T412

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT14,T15,T16

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT29,T30,T412
11CoveredT14,T15,T16

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT38,T39,T40

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T29,T30,T412
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T14,T15,T16
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T38,T39,T40
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 908 908 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 908 908 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T31 1 1 0 0
T63 1 1 0 0
T65 1 1 0 0
T66 1 1 0 0
T67 1 1 0 0
T99 1 1 0 0
T108 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT14,T15,T16
01CoveredT14,T15,T16
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T29,T30
10CoveredT16,T7,T25
11CoveredT28,T29,T30

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT16,T7,T220

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT28,T29,T30
01CoveredT1,T2,T3
10CoveredT28,T29,T30

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT28,T29,T30
10CoveredT16,T7,T220
11CoveredT28,T29,T30

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT16,T7,T220

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT16,T7,T220

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T16,T7,T220
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 908 908 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 908 908 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T31 1 1 0 0
T63 1 1 0 0
T65 1 1 0 0
T66 1 1 0 0
T67 1 1 0 0
T99 1 1 0 0
T108 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT46,T55,T7
01CoveredT32,T33,T9
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T29,T30
10CoveredT32,T33,T10
11CoveredT28,T29,T30

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT7,T32,T33

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT28,T29,T30
01CoveredT1,T2,T3
10CoveredT28,T29,T30

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT28,T29,T30
10CoveredT7,T32,T33
11CoveredT28,T29,T30

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T32,T33

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT7,T32,T33

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT32,T33,T34

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T7,T32,T33
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T32,T33,T34
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 908 908 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 908 908 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T31 1 1 0 0
T63 1 1 0 0
T65 1 1 0 0
T66 1 1 0 0
T67 1 1 0 0
T99 1 1 0 0
T108 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT46,T55,T56
01CoveredT7,T32,T33
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T29,T30
10CoveredT7,T32,T33
11CoveredT28,T29,T30

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT7,T32,T33

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT28,T29,T30
01CoveredT1,T2,T3
10CoveredT28,T29,T30

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT28,T29,T30
10CoveredT7,T32,T33
11CoveredT28,T29,T30

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T32,T33

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT7,T32,T33

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT32,T33,T10

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T7,T32,T33
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T32,T33,T10
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 908 908 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 908 908 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T31 1 1 0 0
T63 1 1 0 0
T65 1 1 0 0
T66 1 1 0 0
T67 1 1 0 0
T99 1 1 0 0
T108 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT46,T55,T7
01CoveredT7,T8,T28
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T29,T30
10CoveredT8,T28,T29
11CoveredT28,T29,T30

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT8,T9,T28

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT28,T29,T30
01CoveredT1,T2,T3
10CoveredT28,T29,T30

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT28,T29,T30
10CoveredT8,T9,T28
11CoveredT28,T29,T30

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T9,T28

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT8,T9,T28

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T8,T9,T28
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 908 908 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 908 908 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T31 1 1 0 0
T63 1 1 0 0
T65 1 1 0 0
T66 1 1 0 0
T67 1 1 0 0
T99 1 1 0 0
T108 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT46,T55,T56
01CoveredT7,T20,T21
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T29,T30
10CoveredT7,T32,T33
11CoveredT28,T29,T30

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT7,T32,T33

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT28,T29,T30
01CoveredT1,T2,T3
10CoveredT28,T29,T30

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT28,T29,T30
10CoveredT7,T32,T33
11CoveredT28,T29,T30

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T32,T33

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT7,T32,T33

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT32,T33,T10

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T7,T32,T33
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T32,T33,T10
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 908 908 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 908 908 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T31 1 1 0 0
T63 1 1 0 0
T65 1 1 0 0
T66 1 1 0 0
T67 1 1 0 0
T99 1 1 0 0
T108 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT46,T55,T246
01CoveredT246,T119,T260
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T29,T30
10CoveredT8,T28,T29
11CoveredT28,T29,T30

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT7,T8,T9

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT28,T29,T30
01CoveredT1,T2,T3
10CoveredT28,T29,T30

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT28,T29,T30
10CoveredT7,T8,T9
11CoveredT28,T29,T30

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T8,T9

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT7,T8,T9

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT32,T33,T34

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T32,T33,T34
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 908 908 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 908 908 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T31 1 1 0 0
T63 1 1 0 0
T65 1 1 0 0
T66 1 1 0 0
T67 1 1 0 0
T99 1 1 0 0
T108 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT46,T55,T246
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T29,T30
10CoveredT1,T2,T3
11CoveredT28,T29,T30

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT1,T2,T3

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT28,T29,T30
01CoveredT1,T2,T3
10CoveredT28,T29,T30

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT28,T29,T30
10CoveredT1,T2,T3
11CoveredT28,T29,T30

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT1,T2,T3

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT32,T33,T34

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T32,T33,T34
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 908 908 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 908 908 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T31 1 1 0 0
T63 1 1 0 0
T65 1 1 0 0
T66 1 1 0 0
T67 1 1 0 0
T99 1 1 0 0
T108 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT16,T46,T55
01CoveredT16,T7,T25
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T29,T30
10CoveredT16,T7,T25
11CoveredT28,T29,T30

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT16,T7,T25

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT28,T29,T30
01CoveredT1,T2,T3
10CoveredT28,T29,T30

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT28,T29,T30
10CoveredT16,T7,T25
11CoveredT28,T29,T30

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT16,T7,T25

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT16,T7,T25

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT32,T33,T34

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T16,T7,T25
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T32,T33,T34
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 908 908 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 908 908 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T31 1 1 0 0
T63 1 1 0 0
T65 1 1 0 0
T66 1 1 0 0
T67 1 1 0 0
T99 1 1 0 0
T108 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT16,T46,T55
01CoveredT16,T18,T25
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T29,T30
10CoveredT16,T25,T35
11CoveredT28,T29,T30

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT16,T7,T25

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT28,T29,T30
01CoveredT1,T2,T3
10CoveredT28,T29,T30

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT28,T29,T30
10CoveredT16,T7,T25
11CoveredT28,T29,T30

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT16,T7,T25

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT16,T7,T25

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T16,T7,T25
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 908 908 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 908 908 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T31 1 1 0 0
T63 1 1 0 0
T65 1 1 0 0
T66 1 1 0 0
T67 1 1 0 0
T99 1 1 0 0
T108 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT16,T46,T55
01CoveredT16,T7,T25
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T29,T30
10CoveredT16,T7,T25
11CoveredT28,T29,T30

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT16,T7,T25

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT28,T29,T30
01CoveredT1,T2,T3
10CoveredT28,T29,T30

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT28,T29,T30
10CoveredT16,T7,T25
11CoveredT28,T29,T30

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT16,T7,T25

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT16,T7,T25

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T16,T7,T25
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 908 908 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 908 908 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T31 1 1 0 0
T63 1 1 0 0
T65 1 1 0 0
T66 1 1 0 0
T67 1 1 0 0
T99 1 1 0 0
T108 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT108,T16,T46
01CoveredT108,T16,T7
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T29,T30
10CoveredT16,T7,T25
11CoveredT28,T29,T30

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT16,T7,T118

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT28,T29,T30
01CoveredT1,T2,T3
10CoveredT28,T29,T30

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT28,T29,T30
10CoveredT16,T7,T118
11CoveredT28,T29,T30

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT16,T7,T118

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT16,T7,T118

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T16,T7,T118
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 908 908 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 908 908 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T31 1 1 0 0
T63 1 1 0 0
T65 1 1 0 0
T66 1 1 0 0
T67 1 1 0 0
T99 1 1 0 0
T108 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT1,T63,T108
01CoveredT1,T63,T108
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T29,T30
10CoveredT1,T63,T261
11CoveredT28,T29,T30

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT29,T30,T412
11CoveredT1,T63,T108

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT28,T29,T30
01CoveredT1,T2,T3
10CoveredT28,T29,T30

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT28,T29,T30
10CoveredT1,T63,T108
11CoveredT28,T29,T30

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T63,T108

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT1,T63,T108

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T1,T63,T108
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 908 908 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 908 908 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T31 1 1 0 0
T63 1 1 0 0
T65 1 1 0 0
T66 1 1 0 0
T67 1 1 0 0
T99 1 1 0 0
T108 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT1,T63,T261
01CoveredT1,T63,T261
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T29,T30
10CoveredT1,T63,T261
11CoveredT28,T29,T30

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT29,T30,T412
11CoveredT1,T63,T261

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT28,T29,T30
01CoveredT1,T2,T3
10CoveredT28,T29,T30

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT28,T29,T30
10CoveredT1,T63,T261
11CoveredT28,T29,T30

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T63,T261

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT1,T63,T261

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T1,T63,T261
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 908 908 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 908 908 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T31 1 1 0 0
T63 1 1 0 0
T65 1 1 0 0
T66 1 1 0 0
T67 1 1 0 0
T99 1 1 0 0
T108 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT1,T63,T261
01CoveredT1,T63,T261
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T29,T30
10CoveredT1,T63,T261
11CoveredT28,T29,T30

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT29,T30,T412
11CoveredT1,T63,T261

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT28,T29,T30
01CoveredT1,T2,T3
10CoveredT28,T29,T30

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT28,T29,T30
10CoveredT1,T63,T261
11CoveredT28,T29,T30

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T63,T261

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT1,T63,T261

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T1,T63,T261
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 908 908 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 908 908 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T31 1 1 0 0
T63 1 1 0 0
T65 1 1 0 0
T66 1 1 0 0
T67 1 1 0 0
T99 1 1 0 0
T108 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[22].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[22].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT58,T59,T262
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T29,T30
10CoveredT8,T28,T29
11CoveredT29,T30,T412

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT7,T8,T28

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT28,T29,T30
01CoveredT1,T2,T3
10CoveredT28,T29,T30

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT28,T29,T30
10CoveredT7,T8,T28
11CoveredT28,T29,T30

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T8,T28

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT7,T8,T28

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT41,T42,T43

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[22].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T28
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T41,T42,T43
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[22].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 908 908 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 908 908 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T31 1 1 0 0
T63 1 1 0 0
T65 1 1 0 0
T66 1 1 0 0
T67 1 1 0 0
T99 1 1 0 0
T108 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[23].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[23].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT7,T58,T59
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T29,T30
10CoveredT7,T28,T29
11CoveredT28,T29,T30

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT7,T8,T9

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT28,T29,T30
01CoveredT1,T2,T3
10CoveredT28,T29,T30

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT28,T29,T30
10CoveredT7,T8,T9
11CoveredT28,T29,T30

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T8,T9

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT7,T8,T9

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT41,T42,T43

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[23].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T41,T42,T43
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[23].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 908 908 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 908 908 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T31 1 1 0 0
T63 1 1 0 0
T65 1 1 0 0
T66 1 1 0 0
T67 1 1 0 0
T99 1 1 0 0
T108 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[24].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[24].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT58,T59,T262
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T29,T30
10CoveredT8,T29,T30
11CoveredT28,T29,T30

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT7,T8,T9

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT28,T29,T30
01CoveredT1,T2,T3
10CoveredT28,T29,T30

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT28,T29,T30
10CoveredT7,T8,T9
11CoveredT28,T29,T30

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T8,T9

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT7,T8,T9

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT41,T42,T43

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[24].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T41,T42,T43
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[24].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 908 908 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 908 908 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T31 1 1 0 0
T63 1 1 0 0
T65 1 1 0 0
T66 1 1 0 0
T67 1 1 0 0
T99 1 1 0 0
T108 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[25].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[25].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT244,T125,T46
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T29,T30
10CoveredT7,T29,T30
11CoveredT28,T29,T30

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT7,T8,T9

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT28,T29,T30
01CoveredT1,T2,T3
10CoveredT28,T29,T30

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT28,T29,T30
10CoveredT7,T8,T9
11CoveredT28,T29,T30

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T8,T9

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT7,T8,T9

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[25].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[25].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 908 908 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 908 908 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T31 1 1 0 0
T63 1 1 0 0
T65 1 1 0 0
T66 1 1 0 0
T67 1 1 0 0
T99 1 1 0 0
T108 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[26].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[26].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT244,T125,T46
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T29,T30
10CoveredT1,T2,T3
11CoveredT28,T29,T30

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT1,T2,T3

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT28,T29,T30
01CoveredT1,T2,T3
10CoveredT28,T29,T30

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT28,T29,T30
10CoveredT1,T2,T3
11CoveredT28,T29,T30

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT1,T2,T3

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[26].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[26].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 908 908 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 908 908 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T31 1 1 0 0
T63 1 1 0 0
T65 1 1 0 0
T66 1 1 0 0
T67 1 1 0 0
T99 1 1 0 0
T108 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[27].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[27].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT31,T54,T46
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T29,T30
10CoveredT7,T28,T29
11CoveredT28,T29,T30

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT7,T8,T9

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT28,T29,T30
01CoveredT1,T2,T3
10CoveredT28,T29,T30

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT29,T30,T412

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT28,T29,T30
10CoveredT7,T8,T9
11CoveredT29,T30,T412

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T8,T9

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT29,T30,T412
11CoveredT7,T8,T9

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[27].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T29,T30,T412
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[27].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 908 908 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 908 908 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T31 1 1 0 0
T63 1 1 0 0
T65 1 1 0 0
T66 1 1 0 0
T67 1 1 0 0
T99 1 1 0 0
T108 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[28].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[28].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT45,T6,T57
01CoveredT45,T6,T57
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T29,T30
10CoveredT8,T28,T29
11CoveredT28,T29,T30

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT7,T8,T28

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT28,T29,T30
01CoveredT1,T2,T3
10CoveredT28,T29,T30

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT28,T29,T30
10CoveredT7,T8,T28
11CoveredT28,T29,T30

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T8,T28

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT7,T8,T28

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[28].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T28
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[28].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 908 908 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 908 908 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T31 1 1 0 0
T63 1 1 0 0
T65 1 1 0 0
T66 1 1 0 0
T67 1 1 0 0
T99 1 1 0 0
T108 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[29].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[29].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT17,T46,T55
01CoveredT17,T7,T20
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T29,T30
10CoveredT7,T413,T8
11CoveredT28,T29,T30

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT7,T413,T8

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT28,T29,T30
01CoveredT1,T2,T3
10CoveredT28,T29,T30

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT28,T29,T30
10CoveredT7,T413,T8
11CoveredT28,T29,T30

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T413,T8

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT7,T413,T8

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[29].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T7,T413,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[29].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 908 908 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 908 908 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T31 1 1 0 0
T63 1 1 0 0
T65 1 1 0 0
T66 1 1 0 0
T67 1 1 0 0
T99 1 1 0 0
T108 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[30].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[30].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT45,T6,T57
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T29,T30
10CoveredT7,T28,T29
11CoveredT28,T29,T30

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT7,T9,T28

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT28,T29,T30
01CoveredT1,T2,T3
10CoveredT28,T29,T30

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT28,T29,T30
10CoveredT7,T9,T28
11CoveredT28,T29,T30

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T9,T28

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT7,T9,T28

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[30].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T7,T9,T28
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[30].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 908 908 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 908 908 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T31 1 1 0 0
T63 1 1 0 0
T65 1 1 0 0
T66 1 1 0 0
T67 1 1 0 0
T99 1 1 0 0
T108 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[31].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[31].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT16,T46,T55
01CoveredT16,T25,T20
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T29,T30
10CoveredT16,T25,T26
11CoveredT28,T29,T30

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT16,T7,T25

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT28,T29,T30
01CoveredT1,T2,T3
10CoveredT28,T29,T30

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT28,T29,T30
10CoveredT16,T7,T25
11CoveredT28,T29,T30

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT16,T7,T25

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT16,T7,T25

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[31].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T16,T7,T25
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[31].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 908 908 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 908 908 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T31 1 1 0 0
T63 1 1 0 0
T65 1 1 0 0
T66 1 1 0 0
T67 1 1 0 0
T99 1 1 0 0
T108 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[32].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[32].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT1,T63,T261
01CoveredT1,T63,T261
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T29,T30
10CoveredT1,T63,T261
11CoveredT28,T29,T30

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT1,T63,T261

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT28,T29,T30
01CoveredT1,T2,T3
10CoveredT28,T29,T30

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT28,T29,T30
10CoveredT1,T63,T261
11CoveredT28,T29,T30

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T63,T261

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT1,T63,T261

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[32].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T1,T63,T261
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[32].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 908 908 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 908 908 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T31 1 1 0 0
T63 1 1 0 0
T65 1 1 0 0
T66 1 1 0 0
T67 1 1 0 0
T99 1 1 0 0
T108 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[33].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[33].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT1,T63,T261
01CoveredT1,T63,T261
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T29,T30
10CoveredT1,T63,T261
11CoveredT28,T29,T30

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT1,T63,T261

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT28,T29,T30
01CoveredT1,T2,T3
10CoveredT28,T29,T30

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT28,T29,T30
10CoveredT1,T63,T261
11CoveredT28,T29,T30

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T63,T261

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT1,T63,T261

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[33].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T1,T63,T261
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[33].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 908 908 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 908 908 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T31 1 1 0 0
T63 1 1 0 0
T65 1 1 0 0
T66 1 1 0 0
T67 1 1 0 0
T99 1 1 0 0
T108 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%