Unified Coverage Report :: Module :: prim_sync_reqack_data

Module : prim_sync_reqack_data

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data	100.00	100.00					100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	66.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
88.32	96.47	89.29	87.66		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_sync_reqack	91.67	100.00	66.67			100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	66.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	84.62			100.00	100.00	u_edn_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_sync_reqack	91.67	100.00	66.67			100.00	100.00

Line Coverage for Module : prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Module : prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	813156750	3100	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	813156750	3100	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	813156750	3100	0	0
T1	132079	1	0	0
T2	288539	4	0	0
T3	227982	4	0	0
T31	244799	2	0	0
T63	464900	2	0	0
T65	154347	2	0	0
T66	143790	2	0	0
T67	343540	1	0	0
T99	271503	4	0	0
T108	210552	2	0	0
T131	107241	4	0	0
T154	219794	0	0	0
T178	159864	0	0	0
T179	158650	0	0	0
T182	268260	0	0	0
T207	0	4	0	0
T208	0	7	0	0
T236	200962	0	0	0
T265	254318	0	0	0
T271	0	4	0	0
T272	0	4	0	0
T275	700936	0	0	0
T299	200274	0	0	0
T311	0	3	0	0
T312	358822	0	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	813156750	3100	0	0
T1	132079	1	0	0
T2	288539	4	0	0
T3	227982	4	0	0
T31	244799	2	0	0
T63	464900	2	0	0
T65	154347	2	0	0
T66	143790	2	0	0
T67	343540	1	0	0
T99	271503	4	0	0
T108	210552	2	0	0
T131	107241	4	0	0
T154	219794	0	0	0
T178	159864	0	0	0
T179	158650	0	0	0
T182	268260	0	0	0
T207	0	4	0	0
T208	0	7	0	0
T236	200962	0	0	0
T265	254318	0	0	0
T271	0	4	0	0
T272	0	4	0	0
T275	700936	0	0	0
T299	200274	0	0	0
T311	0	3	0	0
T312	358822	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	406578375	26	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	406578375	26	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	26	0	0
T131	107241	4	0	0
T154	219794	0	0	0
T178	159864	0	0	0
T179	158650	0	0	0
T182	268260	0	0	0
T207	0	4	0	0
T208	0	7	0	0
T236	200962	0	0	0
T265	254318	0	0	0
T271	0	4	0	0
T272	0	4	0	0
T275	700936	0	0	0
T299	200274	0	0	0
T311	0	3	0	0
T312	358822	0	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	26	0	0
T131	107241	4	0	0
T154	219794	0	0	0
T178	159864	0	0	0
T179	158650	0	0	0
T182	268260	0	0	0
T207	0	4	0	0
T208	0	7	0	0
T236	200962	0	0	0
T265	254318	0	0	0
T271	0	4	0	0
T272	0	4	0	0
T275	700936	0	0	0
T299	200274	0	0	0
T311	0	3	0	0
T312	358822	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	406578375	3074	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	406578375	3074	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	3074	0	0
T1	132079	1	0	0
T2	288539	4	0	0
T3	227982	4	0	0
T31	244799	2	0	0
T63	464900	2	0	0
T65	154347	2	0	0
T66	143790	2	0	0
T67	343540	1	0	0
T99	271503	4	0	0
T108	210552	2	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	3074	0	0
T1	132079	1	0	0
T2	288539	4	0	0
T3	227982	4	0	0
T31	244799	2	0	0
T63	464900	2	0	0
T65	154347	2	0	0
T66	143790	2	0	0
T67	343540	1	0	0
T99	271503	4	0	0
T108	210552	2	0	0