Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rom_ctrl
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.69 94.69

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_rom_ctrl 97.33 97.33



Module Instance : tb.dut.top_earlgrey.u_rom_ctrl

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.33 97.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.33 97.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.60 92.83 90.98 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : rom_ctrl
TotalCoveredPercent
Totals 65 40 61.54
Total Bits 2808 2659 94.69
Total Bits 0->1 1404 1330 94.73
Total Bits 1->0 1404 1329 94.66

Ports 65 40 61.54
Port Bits 2808 2659 94.69
Port Bits 0->1 1404 1330 94.73
Port Bits 1->0 1404 1329 94.66

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T31 Yes T1,T2,T3 INPUT
rom_cfg_i.cfg[3:0] No No No INPUT
rom_cfg_i.cfg_en No No No INPUT
rom_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rom_tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rom_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rom_tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rom_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
rom_tl_i.a_data[31:0] Yes Yes T4,T137,T55 Yes T4,T137,T55 INPUT
rom_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rom_tl_i.a_address[1:0] No No No INPUT
rom_tl_i.a_address[15:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rom_tl_i.a_address[31:16] Unreachable Unreachable Unreachable INPUT
rom_tl_i.a_source[4:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
rom_tl_i.a_source[5] No No No INPUT
rom_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
rom_tl_i.a_size[0] No No No INPUT
rom_tl_i.a_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rom_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
rom_tl_i.a_opcode[1:0] No No No INPUT
rom_tl_i.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rom_tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rom_tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
rom_tl_o.d_error No No No OUTPUT
rom_tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
rom_tl_o.d_user.rsp_intg[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
rom_tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
rom_tl_o.d_user.rsp_intg[4] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
rom_tl_o.d_user.rsp_intg[6:5] No No No OUTPUT
rom_tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
rom_tl_o.d_sink No No No OUTPUT
rom_tl_o.d_source[4:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
rom_tl_o.d_source[5] No No No OUTPUT
rom_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
rom_tl_o.d_size[0] No No No OUTPUT
rom_tl_o.d_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
rom_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
rom_tl_o.d_opcode[0] No No No OUTPUT
rom_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
rom_tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
regs_tl_i.d_ready Yes Yes T2,T3,T31 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.data_intg[6:0] Yes Yes T46,T94,T95 Yes T46,T94,T95 INPUT
regs_tl_i.a_user.cmd_intg[6:0] Yes Yes T138,T46,T94 Yes T138,T46,T94 INPUT
regs_tl_i.a_user.instr_type[0] Yes Yes *T138,*T46,*T94 Yes T138,T46,T94 INPUT
regs_tl_i.a_user.instr_type[2:1] No No No INPUT
regs_tl_i.a_user.instr_type[3] Yes Yes T138,T46,T94 Yes T138,T46,T94 INPUT
regs_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_data[31:0] Yes Yes T46,T94,T95 Yes T46,T94,T95 INPUT
regs_tl_i.a_mask[3:0] Yes Yes T138,T46,T94 Yes T138,T46,T94 INPUT
regs_tl_i.a_address[1:0] No No No INPUT
regs_tl_i.a_address[6:2] Yes Yes T138,T46,T139 Yes T138,T46,T139 INPUT
regs_tl_i.a_address[16:7] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[20:17] Yes Yes T138,T46,T94 Yes T138,T46,T94 INPUT
regs_tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[24] Yes Yes *T138,*T46,*T94 Yes T138,T46,T94 INPUT
regs_tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[30] Yes Yes *T138,*T46,*T94 Yes T138,T46,T94 INPUT
regs_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_source[1:0] Yes Yes *T46,*T138,*T94 Yes T46,T138,T94 INPUT
regs_tl_i.a_source[5:2] No No No INPUT
regs_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_size[0] No No No INPUT
regs_tl_i.a_size[1] Yes Yes T138,T46,T94 Yes T138,T46,T94 INPUT
regs_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_opcode[1:0] No No No INPUT
regs_tl_i.a_opcode[2] Yes Yes T138,T46,T139 Yes T138,T46,T139 INPUT
regs_tl_i.a_valid Yes Yes T138,T46,T94 Yes T138,T46,T94 INPUT
regs_tl_o.a_ready Yes Yes T138,T46,T94 Yes T138,T46,T94 OUTPUT
regs_tl_o.d_error No No No OUTPUT
regs_tl_o.d_user.data_intg[6:0] Yes Yes T138,T139,T140 Yes T138,T139,T140 OUTPUT
regs_tl_o.d_user.rsp_intg[1:0] Yes Yes T46,*T94,*T95 Yes T46,T94,T95 OUTPUT
regs_tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
regs_tl_o.d_user.rsp_intg[5:4] Yes Yes T46,T141,T142 Yes T138,T46,T94 OUTPUT
regs_tl_o.d_user.rsp_intg[6] No No No OUTPUT
regs_tl_o.d_data[31:0] Yes Yes T138,T46,T139 Yes T138,T46,T94 OUTPUT
regs_tl_o.d_sink No No No OUTPUT
regs_tl_o.d_source[1:0] Yes Yes *T46,*T138,*T139 Yes T46,T138,T94 OUTPUT
regs_tl_o.d_source[5:2] No No No OUTPUT
regs_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_size[0] No No No OUTPUT
regs_tl_o.d_size[1] Yes Yes T46,T141,T142 Yes T138,T46,T94 OUTPUT
regs_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_opcode[0] Yes Yes *T46,*T141,*T142 Yes T138,T46,T139 OUTPUT
regs_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_valid Yes Yes T138,T46,T94 Yes T138,T46,T94 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T46,T94,T106 Yes T46,T94,T106 INPUT
alert_rx_i[0].ping_n Yes Yes T106,T107,T175 Yes T106,T107,T175 INPUT
alert_rx_i[0].ping_p Yes Yes T106,T107,T175 Yes T106,T107,T175 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T46,T94,T106 Yes T46,T94,T106 OUTPUT
pwrmgr_data_o.good[3:0] Yes Yes T1,T2,T3 Yes T2,T3,T31 OUTPUT
pwrmgr_data_o.done[3:0] Yes Yes T1,T2,T3 Yes T2,T3,T31 OUTPUT
keymgr_data_o.valid Yes Yes T2,T3,T31 Yes T1,T2,T3 OUTPUT
keymgr_data_o.data[255:0] Yes Yes T2,T3,T31 Yes T1,T2,T3 OUTPUT
kmac_data_i.error No No Yes T6,T202,T204 INPUT
kmac_data_i.digest_share1[383:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
kmac_data_i.digest_share0[383:0] Yes Yes T4,T137,T210 Yes T4,T137,T210 INPUT
kmac_data_i.done Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
kmac_data_i.ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
kmac_data_o.last Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
kmac_data_o.strb[7:0] No No No OUTPUT
kmac_data_o.data[38:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
kmac_data_o.data[63:39] No No No OUTPUT
kmac_data_o.valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rom_ctrl
TotalCoveredPercent
Totals 62 41 66.13
Total Bits 2732 2659 97.33
Total Bits 0->1 1366 1330 97.36
Total Bits 1->0 1366 1329 97.29

Ports 62 41 66.13
Port Bits 2732 2659 97.33
Port Bits 0->1 1366 1330 97.36
Port Bits 1->0 1366 1329 97.29

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T31 Yes T1,T2,T3 INPUT
rom_cfg_i.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
rom_cfg_i.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
rom_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rom_tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rom_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rom_tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rom_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
rom_tl_i.a_data[31:0] Yes Yes T4,T137,T55 Yes T4,T137,T55 INPUT
rom_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rom_tl_i.a_address[1:0] No No No INPUT
rom_tl_i.a_address[15:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rom_tl_i.a_address[31:16] Unreachable Unreachable Unreachable INPUT
rom_tl_i.a_source[4:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
rom_tl_i.a_source[5] No No No INPUT
rom_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
rom_tl_i.a_size[0] No No No INPUT
rom_tl_i.a_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rom_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
rom_tl_i.a_opcode[1:0] No No No INPUT
rom_tl_i.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rom_tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rom_tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
rom_tl_o.d_error No No No OUTPUT
rom_tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
rom_tl_o.d_user.rsp_intg[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
rom_tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
rom_tl_o.d_user.rsp_intg[4] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
rom_tl_o.d_user.rsp_intg[6:5] No No No OUTPUT
rom_tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
rom_tl_o.d_sink No No No OUTPUT
rom_tl_o.d_source[4:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
rom_tl_o.d_source[5] No No No OUTPUT
rom_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
rom_tl_o.d_size[0] No No No OUTPUT
rom_tl_o.d_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
rom_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
rom_tl_o.d_opcode[0] No No No OUTPUT
rom_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
rom_tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
regs_tl_i.d_ready Yes Yes T2,T3,T31 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.data_intg[6:0] Yes Yes T46,T94,T95 Yes T46,T94,T95 INPUT
regs_tl_i.a_user.cmd_intg[6:0] Yes Yes T138,T46,T94 Yes T138,T46,T94 INPUT
regs_tl_i.a_user.instr_type[0] Yes Yes *T138,*T46,*T94 Yes T138,T46,T94 INPUT
regs_tl_i.a_user.instr_type[2:1] No No No INPUT
regs_tl_i.a_user.instr_type[3] Yes Yes T138,T46,T94 Yes T138,T46,T94 INPUT
regs_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_data[31:0] Yes Yes T46,T94,T95 Yes T46,T94,T95 INPUT
regs_tl_i.a_mask[3:0] Yes Yes T138,T46,T94 Yes T138,T46,T94 INPUT
regs_tl_i.a_address[1:0] No No No INPUT
regs_tl_i.a_address[6:2] Yes Yes T138,T46,T139 Yes T138,T46,T139 INPUT
regs_tl_i.a_address[16:7] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[20:17] Yes Yes T138,T46,T94 Yes T138,T46,T94 INPUT
regs_tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[24] Yes Yes *T138,*T46,*T94 Yes T138,T46,T94 INPUT
regs_tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[30] Yes Yes *T138,*T46,*T94 Yes T138,T46,T94 INPUT
regs_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_source[1:0] Yes Yes *T46,*T138,*T94 Yes T46,T138,T94 INPUT
regs_tl_i.a_source[5:2] No No No INPUT
regs_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_size[0] No No No INPUT
regs_tl_i.a_size[1] Yes Yes T138,T46,T94 Yes T138,T46,T94 INPUT
regs_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_opcode[1:0] No No No INPUT
regs_tl_i.a_opcode[2] Yes Yes T138,T46,T139 Yes T138,T46,T139 INPUT
regs_tl_i.a_valid Yes Yes T138,T46,T94 Yes T138,T46,T94 INPUT
regs_tl_o.a_ready Yes Yes T138,T46,T94 Yes T138,T46,T94 OUTPUT
regs_tl_o.d_error No No No OUTPUT
regs_tl_o.d_user.data_intg[6:0] Yes Yes T138,T139,T140 Yes T138,T139,T140 OUTPUT
regs_tl_o.d_user.rsp_intg[1:0] Yes Yes T46,*T94,*T95 Yes T46,T94,T95 OUTPUT
regs_tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
regs_tl_o.d_user.rsp_intg[5:4] Yes Yes T46,T141,T142 Yes T138,T46,T94 OUTPUT
regs_tl_o.d_user.rsp_intg[6] No No No OUTPUT
regs_tl_o.d_data[31:0] Yes Yes T138,T46,T139 Yes T138,T46,T94 OUTPUT
regs_tl_o.d_sink No No No OUTPUT
regs_tl_o.d_source[1:0] Yes Yes *T46,*T138,*T139 Yes T46,T138,T94 OUTPUT
regs_tl_o.d_source[5:2] No No No OUTPUT
regs_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_size[0] No No No OUTPUT
regs_tl_o.d_size[1] Yes Yes T46,T141,T142 Yes T138,T46,T94 OUTPUT
regs_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_opcode[0] Yes Yes *T46,*T141,*T142 Yes T138,T46,T139 OUTPUT
regs_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_valid Yes Yes T138,T46,T94 Yes T138,T46,T94 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T46,T94,T106 Yes T46,T94,T106 INPUT
alert_rx_i[0].ping_n Yes Yes T106,T107,T175 Yes T106,T107,T175 INPUT
alert_rx_i[0].ping_p Yes Yes T106,T107,T175 Yes T106,T107,T175 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T46,T94,T106 Yes T46,T94,T106 OUTPUT
pwrmgr_data_o.good[3:0] Yes Yes T1,T2,T3 Yes T2,T3,T31 OUTPUT
pwrmgr_data_o.done[3:0] Yes Yes T1,T2,T3 Yes T2,T3,T31 OUTPUT
keymgr_data_o.valid Yes Yes T2,T3,T31 Yes T1,T2,T3 OUTPUT
keymgr_data_o.data[255:0] Yes Yes T2,T3,T31 Yes T1,T2,T3 OUTPUT
kmac_data_i.error No No Yes T6,T202,T204 INPUT
kmac_data_i.digest_share1[383:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
kmac_data_i.digest_share0[383:0] Yes Yes T4,T137,T210 Yes T4,T137,T210 INPUT
kmac_data_i.done Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
kmac_data_i.ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
kmac_data_o.last Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
kmac_data_o.strb[7:0] Excluded Excluded Excluded OUTPUT [UNR] rom_ctrl -> KMAC app intf: Tied off data and strobe bits.
kmac_data_o.data[38:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
kmac_data_o.data[63:39] Excluded Excluded Excluded OUTPUT [UNR] rom_ctrl -> KMAC app intf: Tied off data and strobe bits.
kmac_data_o.valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%