Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	96.55	100.00	93.33			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T131,T46,T271
0	1	Covered	T131,T271,T272
1	0	Covered	T46

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T131,T46,T271
1	Covered	T131,T46,T271

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T131,T46,T271
1	Covered	T131,T46,T271

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T131,T271,T272
1	1	Covered	T131,T46,T271

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T131,T46,T271
1	0	Covered	T131,T46,T271
1	1	Covered	T131,T271,T272

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T131,T46,T271

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T131,T46,T271
0	Covered	T131,T46,T271

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T131,T46,T271
0	Covered	T131,T46,T271

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	813156750	795918238	0	0
CheckNGreaterZero_A	1816	1816	0	0
GntImpliesReady_A	813156750	5450	0	0
GntImpliesValid_A	813156750	5450	0	0
GrantKnown_A	813156750	795918238	0	0
IdxKnown_A	813156750	795918238	0	0
IndexIsCorrect_A	813156750	5450	0	0
NoReadyValidNoGrant_A	813156750	0	0	0
Priority_A	813156750	5450	0	0
ReadyAndValidImplyGrant_A	813156750	5450	0	0
ReqAndReadyImplyGrant_A	813156750	5450	0	0
ReqImpliesValid_A	813156750	5450	0	0
ValidKnown_A	813156750	795918238	0	0
gen_data_port_assertion.DataFlow_A	813156750	5450	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	813156750	795918238	0	0
T1	264158	264034	0	0
T2	577078	576766	0	0
T3	455964	455738	0	0
T31	489598	489350	0	0
T63	929800	929568	0	0
T65	308694	308578	0	0
T66	287580	287464	0	0
T67	687080	686970	0	0
T99	543006	542758	0	0
T108	421104	420980	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1816	1816	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T31	2	2	0	0
T63	2	2	0	0
T65	2	2	0	0
T66	2	2	0	0
T67	2	2	0	0
T99	2	2	0	0
T108	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	813156750	5450	0	0
T131	214482	1820	0	0
T154	439588	0	0	0
T178	319728	0	0	0
T179	317300	0	0	0
T182	536520	0	0	0
T236	401924	0	0	0
T265	508636	0	0	0
T271	0	1810	0	0
T272	0	1820	0	0
T275	1401872	0	0	0
T299	400548	0	0	0
T312	717644	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	813156750	5450	0	0
T131	214482	1820	0	0
T154	439588	0	0	0
T178	319728	0	0	0
T179	317300	0	0	0
T182	536520	0	0	0
T236	401924	0	0	0
T265	508636	0	0	0
T271	0	1810	0	0
T272	0	1820	0	0
T275	1401872	0	0	0
T299	400548	0	0	0
T312	717644	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	813156750	795918238	0	0
T1	264158	264034	0	0
T2	577078	576766	0	0
T3	455964	455738	0	0
T31	489598	489350	0	0
T63	929800	929568	0	0
T65	308694	308578	0	0
T66	287580	287464	0	0
T67	687080	686970	0	0
T99	543006	542758	0	0
T108	421104	420980	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	813156750	795918238	0	0
T1	264158	264034	0	0
T2	577078	576766	0	0
T3	455964	455738	0	0
T31	489598	489350	0	0
T63	929800	929568	0	0
T65	308694	308578	0	0
T66	287580	287464	0	0
T67	687080	686970	0	0
T99	543006	542758	0	0
T108	421104	420980	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	813156750	5450	0	0
T131	214482	1820	0	0
T154	439588	0	0	0
T178	319728	0	0	0
T179	317300	0	0	0
T182	536520	0	0	0
T236	401924	0	0	0
T265	508636	0	0	0
T271	0	1810	0	0
T272	0	1820	0	0
T275	1401872	0	0	0
T299	400548	0	0	0
T312	717644	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	813156750	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	813156750	5450	0	0
T131	214482	1820	0	0
T154	439588	0	0	0
T178	319728	0	0	0
T179	317300	0	0	0
T182	536520	0	0	0
T236	401924	0	0	0
T265	508636	0	0	0
T271	0	1810	0	0
T272	0	1820	0	0
T275	1401872	0	0	0
T299	400548	0	0	0
T312	717644	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	813156750	5450	0	0
T131	214482	1820	0	0
T154	439588	0	0	0
T178	319728	0	0	0
T179	317300	0	0	0
T182	536520	0	0	0
T236	401924	0	0	0
T265	508636	0	0	0
T271	0	1810	0	0
T272	0	1820	0	0
T275	1401872	0	0	0
T299	400548	0	0	0
T312	717644	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	813156750	5450	0	0
T131	214482	1820	0	0
T154	439588	0	0	0
T178	319728	0	0	0
T179	317300	0	0	0
T182	536520	0	0	0
T236	401924	0	0	0
T265	508636	0	0	0
T271	0	1810	0	0
T272	0	1820	0	0
T275	1401872	0	0	0
T299	400548	0	0	0
T312	717644	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	813156750	5450	0	0
T131	214482	1820	0	0
T154	439588	0	0	0
T178	319728	0	0	0
T179	317300	0	0	0
T182	536520	0	0	0
T236	401924	0	0	0
T265	508636	0	0	0
T271	0	1810	0	0
T272	0	1820	0	0
T275	1401872	0	0	0
T299	400548	0	0	0
T312	717644	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	813156750	795918238	0	0
T1	264158	264034	0	0
T2	577078	576766	0	0
T3	455964	455738	0	0
T31	489598	489350	0	0
T63	929800	929568	0	0
T65	308694	308578	0	0
T66	287580	287464	0	0
T67	687080	686970	0	0
T99	543006	542758	0	0
T108	421104	420980	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	813156750	5450	0	0
T131	214482	1820	0	0
T154	439588	0	0	0
T178	319728	0	0	0
T179	317300	0	0	0
T182	536520	0	0	0
T236	401924	0	0	0
T265	508636	0	0	0
T271	0	1810	0	0
T272	0	1820	0	0
T275	1401872	0	0	0
T299	400548	0	0	0
T312	717644	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T131,T271,T272
0	1	Covered	T131,T271,T272
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T131,T271,T272
1	Covered	T131,T271,T272

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T131,T271,T272
1	Covered	T131,T271,T272

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T131,T271,T272
1	1	Covered	T131,T271,T272

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T131,T271,T272
1	0	Covered	T131,T271,T272
1	1	Covered	T131,T271,T272

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T131,T271,T272

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T131,T271,T272
0	Covered	T131,T271,T272

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T131,T271,T272
0	Covered	T131,T271,T272

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	406578375	397959119	0	0
CheckNGreaterZero_A	908	908	0	0
GntImpliesReady_A	406578375	4412	0	0
GntImpliesValid_A	406578375	4412	0	0
GrantKnown_A	406578375	397959119	0	0
IdxKnown_A	406578375	397959119	0	0
IndexIsCorrect_A	406578375	4412	0	0
NoReadyValidNoGrant_A	406578375	0	0	0
Priority_A	406578375	4412	0	0
ReadyAndValidImplyGrant_A	406578375	4412	0	0
ReqAndReadyImplyGrant_A	406578375	4412	0	0
ReqImpliesValid_A	406578375	4412	0	0
ValidKnown_A	406578375	397959119	0	0
gen_data_port_assertion.DataFlow_A	406578375	4412	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	397959119	0	0
T1	132079	132017	0	0
T2	288539	288383	0	0
T3	227982	227869	0	0
T31	244799	244675	0	0
T63	464900	464784	0	0
T65	154347	154289	0	0
T66	143790	143732	0	0
T67	343540	343485	0	0
T99	271503	271379	0	0
T108	210552	210490	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	908	908	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T31	1	1	0	0
T63	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0
T67	1	1	0	0
T99	1	1	0	0
T108	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	4412	0	0
T131	107241	1474	0	0
T154	219794	0	0	0
T178	159864	0	0	0
T179	158650	0	0	0
T182	268260	0	0	0
T236	200962	0	0	0
T265	254318	0	0	0
T271	0	1464	0	0
T272	0	1474	0	0
T275	700936	0	0	0
T299	200274	0	0	0
T312	358822	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	4412	0	0
T131	107241	1474	0	0
T154	219794	0	0	0
T178	159864	0	0	0
T179	158650	0	0	0
T182	268260	0	0	0
T236	200962	0	0	0
T265	254318	0	0	0
T271	0	1464	0	0
T272	0	1474	0	0
T275	700936	0	0	0
T299	200274	0	0	0
T312	358822	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	397959119	0	0
T1	132079	132017	0	0
T2	288539	288383	0	0
T3	227982	227869	0	0
T31	244799	244675	0	0
T63	464900	464784	0	0
T65	154347	154289	0	0
T66	143790	143732	0	0
T67	343540	343485	0	0
T99	271503	271379	0	0
T108	210552	210490	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	397959119	0	0
T1	132079	132017	0	0
T2	288539	288383	0	0
T3	227982	227869	0	0
T31	244799	244675	0	0
T63	464900	464784	0	0
T65	154347	154289	0	0
T66	143790	143732	0	0
T67	343540	343485	0	0
T99	271503	271379	0	0
T108	210552	210490	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	4412	0	0
T131	107241	1474	0	0
T154	219794	0	0	0
T178	159864	0	0	0
T179	158650	0	0	0
T182	268260	0	0	0
T236	200962	0	0	0
T265	254318	0	0	0
T271	0	1464	0	0
T272	0	1474	0	0
T275	700936	0	0	0
T299	200274	0	0	0
T312	358822	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	4412	0	0
T131	107241	1474	0	0
T154	219794	0	0	0
T178	159864	0	0	0
T179	158650	0	0	0
T182	268260	0	0	0
T236	200962	0	0	0
T265	254318	0	0	0
T271	0	1464	0	0
T272	0	1474	0	0
T275	700936	0	0	0
T299	200274	0	0	0
T312	358822	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	4412	0	0
T131	107241	1474	0	0
T154	219794	0	0	0
T178	159864	0	0	0
T179	158650	0	0	0
T182	268260	0	0	0
T236	200962	0	0	0
T265	254318	0	0	0
T271	0	1464	0	0
T272	0	1474	0	0
T275	700936	0	0	0
T299	200274	0	0	0
T312	358822	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	4412	0	0
T131	107241	1474	0	0
T154	219794	0	0	0
T178	159864	0	0	0
T179	158650	0	0	0
T182	268260	0	0	0
T236	200962	0	0	0
T265	254318	0	0	0
T271	0	1464	0	0
T272	0	1474	0	0
T275	700936	0	0	0
T299	200274	0	0	0
T312	358822	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	4412	0	0
T131	107241	1474	0	0
T154	219794	0	0	0
T178	159864	0	0	0
T179	158650	0	0	0
T182	268260	0	0	0
T236	200962	0	0	0
T265	254318	0	0	0
T271	0	1464	0	0
T272	0	1474	0	0
T275	700936	0	0	0
T299	200274	0	0	0
T312	358822	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	397959119	0	0
T1	132079	132017	0	0
T2	288539	288383	0	0
T3	227982	227869	0	0
T31	244799	244675	0	0
T63	464900	464784	0	0
T65	154347	154289	0	0
T66	143790	143732	0	0
T67	343540	343485	0	0
T99	271503	271379	0	0
T108	210552	210490	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	4412	0	0
T131	107241	1474	0	0
T154	219794	0	0	0
T178	159864	0	0	0
T179	158650	0	0	0
T182	268260	0	0	0
T236	200962	0	0	0
T265	254318	0	0	0
T271	0	1464	0	0
T272	0	1474	0	0
T275	700936	0	0	0
T299	200274	0	0	0
T312	358822	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T131,T46,T271
0	1	Covered	T131,T271,T272
1	0	Covered	T46

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T131,T46,T271
1	Covered	T131,T46,T271

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T131,T46,T271
1	Covered	T131,T46,T271

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T131,T271,T272
1	1	Covered	T131,T46,T271

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T131,T46,T271
1	0	Covered	T131,T46,T271
1	1	Covered	T131,T271,T272

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T131,T46,T271

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T131,T46,T271
0	Covered	T131,T46,T271

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T131,T46,T271
0	Covered	T131,T46,T271

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	406578375	397959119	0	0
CheckNGreaterZero_A	908	908	0	0
GntImpliesReady_A	406578375	1038	0	0
GntImpliesValid_A	406578375	1038	0	0
GrantKnown_A	406578375	397959119	0	0
IdxKnown_A	406578375	397959119	0	0
IndexIsCorrect_A	406578375	1038	0	0
NoReadyValidNoGrant_A	406578375	0	0	0
Priority_A	406578375	1038	0	0
ReadyAndValidImplyGrant_A	406578375	1038	0	0
ReqAndReadyImplyGrant_A	406578375	1038	0	0
ReqImpliesValid_A	406578375	1038	0	0
ValidKnown_A	406578375	397959119	0	0
gen_data_port_assertion.DataFlow_A	406578375	1038	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	397959119	0	0
T1	132079	132017	0	0
T2	288539	288383	0	0
T3	227982	227869	0	0
T31	244799	244675	0	0
T63	464900	464784	0	0
T65	154347	154289	0	0
T66	143790	143732	0	0
T67	343540	343485	0	0
T99	271503	271379	0	0
T108	210552	210490	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	908	908	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T31	1	1	0	0
T63	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0
T67	1	1	0	0
T99	1	1	0	0
T108	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	1038	0	0
T131	107241	346	0	0
T154	219794	0	0	0
T178	159864	0	0	0
T179	158650	0	0	0
T182	268260	0	0	0
T236	200962	0	0	0
T265	254318	0	0	0
T271	0	346	0	0
T272	0	346	0	0
T275	700936	0	0	0
T299	200274	0	0	0
T312	358822	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	1038	0	0
T131	107241	346	0	0
T154	219794	0	0	0
T178	159864	0	0	0
T179	158650	0	0	0
T182	268260	0	0	0
T236	200962	0	0	0
T265	254318	0	0	0
T271	0	346	0	0
T272	0	346	0	0
T275	700936	0	0	0
T299	200274	0	0	0
T312	358822	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	397959119	0	0
T1	132079	132017	0	0
T2	288539	288383	0	0
T3	227982	227869	0	0
T31	244799	244675	0	0
T63	464900	464784	0	0
T65	154347	154289	0	0
T66	143790	143732	0	0
T67	343540	343485	0	0
T99	271503	271379	0	0
T108	210552	210490	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	397959119	0	0
T1	132079	132017	0	0
T2	288539	288383	0	0
T3	227982	227869	0	0
T31	244799	244675	0	0
T63	464900	464784	0	0
T65	154347	154289	0	0
T66	143790	143732	0	0
T67	343540	343485	0	0
T99	271503	271379	0	0
T108	210552	210490	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	1038	0	0
T131	107241	346	0	0
T154	219794	0	0	0
T178	159864	0	0	0
T179	158650	0	0	0
T182	268260	0	0	0
T236	200962	0	0	0
T265	254318	0	0	0
T271	0	346	0	0
T272	0	346	0	0
T275	700936	0	0	0
T299	200274	0	0	0
T312	358822	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	1038	0	0
T131	107241	346	0	0
T154	219794	0	0	0
T178	159864	0	0	0
T179	158650	0	0	0
T182	268260	0	0	0
T236	200962	0	0	0
T265	254318	0	0	0
T271	0	346	0	0
T272	0	346	0	0
T275	700936	0	0	0
T299	200274	0	0	0
T312	358822	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	1038	0	0
T131	107241	346	0	0
T154	219794	0	0	0
T178	159864	0	0	0
T179	158650	0	0	0
T182	268260	0	0	0
T236	200962	0	0	0
T265	254318	0	0	0
T271	0	346	0	0
T272	0	346	0	0
T275	700936	0	0	0
T299	200274	0	0	0
T312	358822	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	1038	0	0
T131	107241	346	0	0
T154	219794	0	0	0
T178	159864	0	0	0
T179	158650	0	0	0
T182	268260	0	0	0
T236	200962	0	0	0
T265	254318	0	0	0
T271	0	346	0	0
T272	0	346	0	0
T275	700936	0	0	0
T299	200274	0	0	0
T312	358822	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	1038	0	0
T131	107241	346	0	0
T154	219794	0	0	0
T178	159864	0	0	0
T179	158650	0	0	0
T182	268260	0	0	0
T236	200962	0	0	0
T265	254318	0	0	0
T271	0	346	0	0
T272	0	346	0	0
T275	700936	0	0	0
T299	200274	0	0	0
T312	358822	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	397959119	0	0
T1	132079	132017	0	0
T2	288539	288383	0	0
T3	227982	227869	0	0
T31	244799	244675	0	0
T63	464900	464784	0	0
T65	154347	154289	0	0
T66	143790	143732	0	0
T67	343540	343485	0	0
T99	271503	271379	0	0
T108	210552	210490	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406578375	1038	0	0
T131	107241	346	0	0
T154	219794	0	0	0
T178	159864	0	0	0
T179	158650	0	0	0
T182	268260	0	0	0
T236	200962	0	0	0
T265	254318	0	0	0
T271	0	346	0	0
T272	0	346	0	0
T275	700936	0	0	0
T299	200274	0	0	0
T312	358822	0	0	0