Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.22 92.38 82.42 90.36 94.36 97.38 84.43


Total test records in report: 908
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T327 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.487718485 Apr 25 03:46:16 PM PDT 24 Apr 25 03:57:29 PM PDT 24 4326058792 ps
T58 /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.873058124 Apr 25 03:28:48 PM PDT 24 Apr 25 07:14:04 PM PDT 24 77734492711 ps
T377 /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.3590674722 Apr 25 03:54:58 PM PDT 24 Apr 25 04:01:47 PM PDT 24 3402628862 ps
T550 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.165719081 Apr 25 03:37:18 PM PDT 24 Apr 25 03:47:30 PM PDT 24 4702543720 ps
T551 /workspace/coverage/default/1.chip_sw_example_flash.3762466815 Apr 25 03:31:21 PM PDT 24 Apr 25 03:34:27 PM PDT 24 2403600528 ps
T552 /workspace/coverage/default/0.chip_sw_example_flash.1909208310 Apr 25 03:24:21 PM PDT 24 Apr 25 03:28:37 PM PDT 24 2466378404 ps
T84 /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.2997898106 Apr 25 03:49:57 PM PDT 24 Apr 25 04:03:34 PM PDT 24 5859694088 ps
T150 /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.3930422662 Apr 25 03:23:27 PM PDT 24 Apr 25 03:54:43 PM PDT 24 12181160680 ps
T91 /workspace/coverage/default/4.chip_tap_straps_testunlock0.924646039 Apr 25 03:48:44 PM PDT 24 Apr 25 03:51:58 PM PDT 24 2771848248 ps
T318 /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.2996170307 Apr 25 03:34:33 PM PDT 24 Apr 25 03:42:24 PM PDT 24 4899898088 ps
T553 /workspace/coverage/default/1.rom_keymgr_functest.1273633970 Apr 25 03:41:40 PM PDT 24 Apr 25 03:51:19 PM PDT 24 4234695368 ps
T355 /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.1119280954 Apr 25 03:53:14 PM PDT 24 Apr 25 04:23:12 PM PDT 24 8957847560 ps
T197 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.801397473 Apr 25 03:29:51 PM PDT 24 Apr 25 03:43:02 PM PDT 24 10856631512 ps
T554 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.3956780932 Apr 25 03:30:31 PM PDT 24 Apr 25 03:37:58 PM PDT 24 4593723344 ps
T136 /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.238396047 Apr 25 03:26:03 PM PDT 24 Apr 25 03:33:31 PM PDT 24 3639189656 ps
T21 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.388909410 Apr 25 03:31:42 PM PDT 24 Apr 25 04:00:56 PM PDT 24 23106507444 ps
T555 /workspace/coverage/default/3.chip_tap_straps_prod.2977578919 Apr 25 03:51:28 PM PDT 24 Apr 25 04:06:03 PM PDT 24 9468152741 ps
T254 /workspace/coverage/default/2.chip_sw_plic_sw_irq.487081887 Apr 25 03:46:08 PM PDT 24 Apr 25 03:50:26 PM PDT 24 2990791460 ps
T383 /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1716665439 Apr 25 03:50:32 PM PDT 24 Apr 25 03:58:22 PM PDT 24 3960905852 ps
T23 /workspace/coverage/default/2.chip_jtag_csr_rw.711577430 Apr 25 03:38:14 PM PDT 24 Apr 25 04:00:40 PM PDT 24 11350353865 ps
T556 /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.3030568682 Apr 25 03:31:19 PM PDT 24 Apr 25 03:41:15 PM PDT 24 5442677240 ps
T294 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2396161426 Apr 25 03:25:06 PM PDT 24 Apr 25 03:34:14 PM PDT 24 4116427180 ps
T60 /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.626288150 Apr 25 03:43:49 PM PDT 24 Apr 25 03:47:03 PM PDT 24 2771238441 ps
T450 /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.2351836471 Apr 25 03:58:49 PM PDT 24 Apr 25 04:05:32 PM PDT 24 3669980080 ps
T198 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.3770699177 Apr 25 03:23:48 PM PDT 24 Apr 25 05:02:21 PM PDT 24 48721962504 ps
T140 /workspace/coverage/default/2.chip_sw_kmac_app_rom.1319193434 Apr 25 03:44:32 PM PDT 24 Apr 25 03:48:21 PM PDT 24 2530134338 ps
T414 /workspace/coverage/default/84.chip_sw_all_escalation_resets.117730466 Apr 25 04:04:54 PM PDT 24 Apr 25 04:14:29 PM PDT 24 5779693000 ps
T228 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.1862725771 Apr 25 03:29:19 PM PDT 24 Apr 25 05:00:43 PM PDT 24 50874299224 ps
T284 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.4147853844 Apr 25 03:31:25 PM PDT 24 Apr 25 03:33:04 PM PDT 24 2043273409 ps
T465 /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2385328690 Apr 25 03:51:04 PM PDT 24 Apr 25 03:56:57 PM PDT 24 3592229652 ps
T295 /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.3986822418 Apr 25 03:25:28 PM PDT 24 Apr 25 03:32:16 PM PDT 24 3541611376 ps
T557 /workspace/coverage/default/1.chip_sw_edn_sw_mode.1906303753 Apr 25 03:32:54 PM PDT 24 Apr 25 04:02:15 PM PDT 24 8383192794 ps
T558 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4142457049 Apr 25 03:24:40 PM PDT 24 Apr 25 03:32:43 PM PDT 24 5263220952 ps
T559 /workspace/coverage/default/0.chip_sw_kmac_idle.3808646860 Apr 25 03:24:12 PM PDT 24 Apr 25 03:28:29 PM PDT 24 2265119640 ps
T360 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.1064308247 Apr 25 03:28:05 PM PDT 24 Apr 25 03:38:24 PM PDT 24 4336221381 ps
T176 /workspace/coverage/default/1.chip_plic_all_irqs_0.4082783122 Apr 25 03:36:56 PM PDT 24 Apr 25 03:58:51 PM PDT 24 6505550470 ps
T560 /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.3373351296 Apr 25 03:42:14 PM PDT 24 Apr 25 03:47:22 PM PDT 24 4330252952 ps
T328 /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2548838118 Apr 25 03:42:21 PM PDT 24 Apr 25 07:34:19 PM PDT 24 255849534100 ps
T561 /workspace/coverage/default/2.chip_sw_kmac_idle.4020248838 Apr 25 03:44:35 PM PDT 24 Apr 25 03:49:04 PM PDT 24 2492182096 ps
T273 /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.2900770443 Apr 25 03:28:19 PM PDT 24 Apr 25 03:31:59 PM PDT 24 2825363960 ps
T390 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.1337663516 Apr 25 03:43:12 PM PDT 24 Apr 25 04:48:09 PM PDT 24 14335188064 ps
T562 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.168110384 Apr 25 03:30:31 PM PDT 24 Apr 25 03:49:15 PM PDT 24 9049985673 ps
T563 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.4047777969 Apr 25 03:40:42 PM PDT 24 Apr 25 04:01:33 PM PDT 24 6802281196 ps
T61 /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.2853640172 Apr 25 03:42:45 PM PDT 24 Apr 25 03:52:18 PM PDT 24 9446976528 ps
T110 /workspace/coverage/default/14.chip_sw_all_escalation_resets.641927857 Apr 25 03:52:16 PM PDT 24 Apr 25 04:03:21 PM PDT 24 6191952926 ps
T62 /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.1551587298 Apr 25 03:34:42 PM PDT 24 Apr 25 03:37:53 PM PDT 24 2538492171 ps
T347 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.2168680102 Apr 25 03:41:38 PM PDT 24 Apr 25 03:53:48 PM PDT 24 4186996736 ps
T223 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.819534633 Apr 25 03:40:35 PM PDT 24 Apr 25 03:54:01 PM PDT 24 5277497960 ps
T564 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1118548815 Apr 25 03:26:06 PM PDT 24 Apr 25 03:35:19 PM PDT 24 3960852620 ps
T565 /workspace/coverage/default/2.chip_sw_csrng_kat_test.3860760382 Apr 25 03:45:57 PM PDT 24 Apr 25 03:48:36 PM PDT 24 2632731948 ps
T274 /workspace/coverage/default/1.chip_sw_rv_timer_irq.2107986868 Apr 25 03:32:34 PM PDT 24 Apr 25 03:37:35 PM PDT 24 3123982128 ps
T566 /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.3541207731 Apr 25 03:24:43 PM PDT 24 Apr 25 03:31:40 PM PDT 24 5543410850 ps
T226 /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3205938429 Apr 25 03:57:46 PM PDT 24 Apr 25 04:04:52 PM PDT 24 4059703092 ps
T567 /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.135364163 Apr 25 03:50:51 PM PDT 24 Apr 25 03:59:16 PM PDT 24 6695895408 ps
T568 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2650027717 Apr 25 03:36:14 PM PDT 24 Apr 25 03:47:01 PM PDT 24 4446752950 ps
T569 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.2637630788 Apr 25 03:48:34 PM PDT 24 Apr 25 03:52:13 PM PDT 24 2523422117 ps
T398 /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.1463977989 Apr 25 03:40:13 PM PDT 24 Apr 25 03:46:33 PM PDT 24 4610495580 ps
T570 /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.2100295527 Apr 25 03:39:27 PM PDT 24 Apr 25 03:48:32 PM PDT 24 4884564056 ps
T242 /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.2278730558 Apr 25 03:56:04 PM PDT 24 Apr 25 04:02:56 PM PDT 24 3806303672 ps
T92 /workspace/coverage/default/3.chip_tap_straps_testunlock0.2453715731 Apr 25 03:51:20 PM PDT 24 Apr 25 03:57:00 PM PDT 24 4736292666 ps
T329 /workspace/coverage/default/1.chip_tap_straps_rma.3357986997 Apr 25 03:35:58 PM PDT 24 Apr 25 03:39:06 PM PDT 24 2347895430 ps
T330 /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.2387970298 Apr 25 03:25:01 PM PDT 24 Apr 25 03:37:07 PM PDT 24 7016728443 ps
T331 /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.3933088141 Apr 25 03:55:36 PM PDT 24 Apr 25 04:03:30 PM PDT 24 3910104638 ps
T183 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.2183913580 Apr 25 03:25:38 PM PDT 24 Apr 25 03:59:19 PM PDT 24 8899668040 ps
T332 /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.1971848787 Apr 25 03:24:23 PM PDT 24 Apr 25 03:32:24 PM PDT 24 6902137944 ps
T123 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.4032938793 Apr 25 03:36:36 PM PDT 24 Apr 25 03:42:02 PM PDT 24 7402247588 ps
T229 /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.3487890356 Apr 25 03:24:46 PM PDT 24 Apr 25 04:58:15 PM PDT 24 48570829800 ps
T319 /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.949250729 Apr 25 03:27:24 PM PDT 24 Apr 25 03:37:30 PM PDT 24 4716102810 ps
T370 /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.3394218812 Apr 25 03:23:49 PM PDT 24 Apr 25 03:37:41 PM PDT 24 4450821700 ps
T571 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.4153895926 Apr 25 03:37:34 PM PDT 24 Apr 25 03:47:56 PM PDT 24 4312743710 ps
T572 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.704868200 Apr 25 03:43:15 PM PDT 24 Apr 25 03:54:25 PM PDT 24 4466652102 ps
T59 /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.4194262740 Apr 25 03:29:17 PM PDT 24 Apr 25 06:27:20 PM PDT 24 59638629076 ps
T365 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3594728941 Apr 25 03:42:10 PM PDT 24 Apr 25 04:15:05 PM PDT 24 22150813850 ps
T320 /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.3001552477 Apr 25 03:55:19 PM PDT 24 Apr 25 04:04:53 PM PDT 24 3594534520 ps
T224 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.2645118611 Apr 25 03:28:18 PM PDT 24 Apr 25 03:40:04 PM PDT 24 5116310160 ps
T573 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2967281619 Apr 25 03:40:22 PM PDT 24 Apr 25 04:05:37 PM PDT 24 12834305775 ps
T574 /workspace/coverage/default/2.chip_sw_uart_smoketest.3301638003 Apr 25 03:48:19 PM PDT 24 Apr 25 03:52:38 PM PDT 24 2997977188 ps
T575 /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.3034319160 Apr 25 03:43:11 PM PDT 24 Apr 25 03:56:50 PM PDT 24 7166958760 ps
T217 /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.4261394448 Apr 25 03:31:54 PM PDT 24 Apr 25 04:17:54 PM PDT 24 12095778736 ps
T463 /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.4199679901 Apr 25 03:55:05 PM PDT 24 Apr 25 04:03:12 PM PDT 24 4224770836 ps
T576 /workspace/coverage/default/0.chip_sw_uart_tx_rx.2252701656 Apr 25 03:23:57 PM PDT 24 Apr 25 03:32:52 PM PDT 24 4618123506 ps
T32 /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.4017769973 Apr 25 03:28:42 PM PDT 24 Apr 25 03:32:45 PM PDT 24 3232932018 ps
T577 /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.3626098168 Apr 25 03:39:43 PM PDT 24 Apr 25 03:46:16 PM PDT 24 3754228908 ps
T208 /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.708448698 Apr 25 03:39:08 PM PDT 24 Apr 25 03:42:30 PM PDT 24 2586333663 ps
T578 /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.2249023822 Apr 25 03:43:04 PM PDT 24 Apr 25 04:59:32 PM PDT 24 43352844269 ps
T279 /workspace/coverage/default/10.chip_sw_all_escalation_resets.2419801460 Apr 25 03:52:21 PM PDT 24 Apr 25 04:04:48 PM PDT 24 5352210128 ps
T213 /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.3300147338 Apr 25 03:25:52 PM PDT 24 Apr 25 03:30:38 PM PDT 24 2396427007 ps
T33 /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2268778909 Apr 25 03:24:32 PM PDT 24 Apr 25 03:29:58 PM PDT 24 3265695840 ps
T579 /workspace/coverage/default/2.chip_tap_straps_dev.3100945935 Apr 25 03:44:48 PM PDT 24 Apr 25 03:48:20 PM PDT 24 3275891365 ps
T107 /workspace/coverage/default/0.chip_sw_alert_handler_entropy.1517072800 Apr 25 03:24:18 PM PDT 24 Apr 25 03:29:32 PM PDT 24 3546073865 ps
T262 /workspace/coverage/default/1.chip_sw_inject_scramble_seed.280601223 Apr 25 03:28:11 PM PDT 24 Apr 25 06:52:44 PM PDT 24 65243531246 ps
T580 /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.3077991284 Apr 25 03:38:54 PM PDT 24 Apr 25 03:47:17 PM PDT 24 3655673668 ps
T581 /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.2316955589 Apr 25 03:51:32 PM PDT 24 Apr 25 03:58:34 PM PDT 24 5320045369 ps
T477 /workspace/coverage/default/27.chip_sw_all_escalation_resets.2136684959 Apr 25 03:55:09 PM PDT 24 Apr 25 04:03:55 PM PDT 24 4330495620 ps
T280 /workspace/coverage/default/72.chip_sw_all_escalation_resets.3457949859 Apr 25 03:57:08 PM PDT 24 Apr 25 04:07:09 PM PDT 24 4592270520 ps
T582 /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.2136028491 Apr 25 03:50:56 PM PDT 24 Apr 25 04:44:50 PM PDT 24 12428133136 ps
T583 /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.1912144461 Apr 25 03:53:11 PM PDT 24 Apr 25 04:18:15 PM PDT 24 8576268220 ps
T472 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.856386995 Apr 25 03:43:05 PM PDT 24 Apr 25 03:49:52 PM PDT 24 3561922028 ps
T227 /workspace/coverage/default/0.chip_sw_flash_init.184417493 Apr 25 03:24:04 PM PDT 24 Apr 25 03:59:38 PM PDT 24 24500729632 ps
T507 /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.3230116645 Apr 25 03:55:49 PM PDT 24 Apr 25 04:01:58 PM PDT 24 3375462702 ps
T584 /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.209389149 Apr 25 03:41:46 PM PDT 24 Apr 25 03:51:15 PM PDT 24 4921839488 ps
T585 /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.3510481674 Apr 25 03:52:01 PM PDT 24 Apr 25 04:38:06 PM PDT 24 13467876884 ps
T586 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.3317894758 Apr 25 03:50:03 PM PDT 24 Apr 25 03:59:54 PM PDT 24 4184516820 ps
T587 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.443834911 Apr 25 03:26:40 PM PDT 24 Apr 25 03:33:07 PM PDT 24 3988425712 ps
T255 /workspace/coverage/default/0.chip_sw_plic_sw_irq.1193807092 Apr 25 03:27:30 PM PDT 24 Apr 25 03:32:15 PM PDT 24 2943983720 ps
T443 /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.3333616745 Apr 25 03:52:43 PM PDT 24 Apr 25 03:59:03 PM PDT 24 3955205684 ps
T588 /workspace/coverage/default/4.chip_tap_straps_rma.3557027953 Apr 25 03:50:33 PM PDT 24 Apr 25 04:01:09 PM PDT 24 6009266041 ps
T589 /workspace/coverage/default/0.chip_sw_otbn_randomness.3586421393 Apr 25 03:23:07 PM PDT 24 Apr 25 03:37:11 PM PDT 24 6025435600 ps
T185 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.3075391445 Apr 25 03:44:21 PM PDT 24 Apr 25 04:58:31 PM PDT 24 19074718753 ps
T392 /workspace/coverage/default/2.chip_sw_edn_auto_mode.4183031262 Apr 25 03:44:56 PM PDT 24 Apr 25 03:56:18 PM PDT 24 3929841996 ps
T590 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.605288482 Apr 25 03:40:46 PM PDT 24 Apr 25 04:05:41 PM PDT 24 8142785769 ps
T258 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.133158004 Apr 25 03:32:29 PM PDT 24 Apr 25 03:37:08 PM PDT 24 3020150160 ps
T591 /workspace/coverage/default/87.chip_sw_all_escalation_resets.2873606021 Apr 25 03:59:53 PM PDT 24 Apr 25 04:12:14 PM PDT 24 5765466176 ps
T323 /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.4126543360 Apr 25 03:24:56 PM PDT 24 Apr 25 04:32:24 PM PDT 24 12413742840 ps
T592 /workspace/coverage/default/2.chip_sw_kmac_entropy.3600550503 Apr 25 03:43:26 PM PDT 24 Apr 25 03:47:12 PM PDT 24 2948832520 ps
T148 /workspace/coverage/default/1.chip_plic_all_irqs_10.1122380307 Apr 25 03:40:05 PM PDT 24 Apr 25 03:51:07 PM PDT 24 4194069098 ps
T415 /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.2412495854 Apr 25 03:56:58 PM PDT 24 Apr 25 04:03:23 PM PDT 24 3532048228 ps
T393 /workspace/coverage/default/1.chip_sw_edn_auto_mode.3445635358 Apr 25 03:35:44 PM PDT 24 Apr 25 03:52:17 PM PDT 24 4808997568 ps
T593 /workspace/coverage/default/2.chip_sw_aon_timer_irq.1949176582 Apr 25 03:43:16 PM PDT 24 Apr 25 03:51:58 PM PDT 24 3494010320 ps
T447 /workspace/coverage/default/37.chip_sw_all_escalation_resets.1055425672 Apr 25 03:54:08 PM PDT 24 Apr 25 04:08:03 PM PDT 24 5274566056 ps
T594 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1518254239 Apr 25 03:46:23 PM PDT 24 Apr 25 03:54:47 PM PDT 24 5029936142 ps
T595 /workspace/coverage/default/2.chip_sw_power_idle_load.1095799133 Apr 25 03:45:54 PM PDT 24 Apr 25 03:57:44 PM PDT 24 4538348790 ps
T596 /workspace/coverage/default/0.chip_sw_aes_masking_off.1123487258 Apr 25 03:23:12 PM PDT 24 Apr 25 03:27:55 PM PDT 24 3045790775 ps
T89 /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.186969252 Apr 25 03:35:51 PM PDT 24 Apr 25 03:45:12 PM PDT 24 3500145760 ps
T597 /workspace/coverage/default/0.chip_sw_csrng_smoketest.1271000539 Apr 25 03:27:35 PM PDT 24 Apr 25 03:31:30 PM PDT 24 2661905320 ps
T175 /workspace/coverage/default/1.chip_sw_alert_handler_entropy.986107864 Apr 25 03:33:54 PM PDT 24 Apr 25 03:40:26 PM PDT 24 3761104666 ps
T470 /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.4092986414 Apr 25 03:55:18 PM PDT 24 Apr 25 04:01:19 PM PDT 24 3058924580 ps
T598 /workspace/coverage/default/0.chip_tap_straps_prod.995403731 Apr 25 03:29:22 PM PDT 24 Apr 25 03:41:29 PM PDT 24 8292375750 ps
T599 /workspace/coverage/default/1.chip_sw_hmac_enc_idle.3100384747 Apr 25 03:34:02 PM PDT 24 Apr 25 03:37:20 PM PDT 24 2601741880 ps
T600 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3059722379 Apr 25 03:46:50 PM PDT 24 Apr 25 03:58:14 PM PDT 24 3661808188 ps
T601 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1469335571 Apr 25 03:27:02 PM PDT 24 Apr 25 03:34:11 PM PDT 24 4304931601 ps
T296 /workspace/coverage/default/2.chip_sw_data_integrity_escalation.2842550021 Apr 25 03:39:27 PM PDT 24 Apr 25 03:48:17 PM PDT 24 5312174458 ps
T35 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2878008868 Apr 25 03:43:37 PM PDT 24 Apr 25 03:52:12 PM PDT 24 5541448144 ps
T602 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.3429335301 Apr 25 03:34:00 PM PDT 24 Apr 25 04:13:06 PM PDT 24 9413229200 ps
T48 /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.4222735664 Apr 25 03:47:07 PM PDT 24 Apr 25 03:55:04 PM PDT 24 3879477650 ps
T423 /workspace/coverage/default/38.chip_sw_all_escalation_resets.2468688537 Apr 25 03:55:01 PM PDT 24 Apr 25 04:03:49 PM PDT 24 4989978160 ps
T504 /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1195675458 Apr 25 03:57:04 PM PDT 24 Apr 25 04:03:32 PM PDT 24 3339596800 ps
T26 /workspace/coverage/default/0.chip_sw_gpio.1399449260 Apr 25 03:24:00 PM PDT 24 Apr 25 03:31:56 PM PDT 24 3706892465 ps
T431 /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3052070169 Apr 25 03:58:35 PM PDT 24 Apr 25 04:05:10 PM PDT 24 3270357714 ps
T24 /workspace/coverage/default/0.chip_sw_usbdev_setuprx.1636844059 Apr 25 03:22:35 PM PDT 24 Apr 25 03:31:08 PM PDT 24 4452409200 ps
T603 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.2628499609 Apr 25 03:33:49 PM PDT 24 Apr 25 03:43:50 PM PDT 24 3978525412 ps
T191 /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.1240008314 Apr 25 03:31:20 PM PDT 24 Apr 25 03:36:13 PM PDT 24 2566466986 ps
T348 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1722639040 Apr 25 03:47:58 PM PDT 24 Apr 25 03:59:23 PM PDT 24 4378082782 ps
T604 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.559188344 Apr 25 03:23:12 PM PDT 24 Apr 25 03:59:40 PM PDT 24 19360596407 ps
T605 /workspace/coverage/default/1.chip_sw_csrng_kat_test.3052527295 Apr 25 03:33:18 PM PDT 24 Apr 25 03:37:01 PM PDT 24 3052441460 ps
T606 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.156606988 Apr 25 03:26:37 PM PDT 24 Apr 25 03:31:59 PM PDT 24 3705049560 ps
T607 /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.668703098 Apr 25 03:29:52 PM PDT 24 Apr 25 03:49:48 PM PDT 24 5038203508 ps
T359 /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.1830311426 Apr 25 03:27:51 PM PDT 24 Apr 25 03:32:38 PM PDT 24 2794682997 ps
T608 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.714776520 Apr 25 03:26:49 PM PDT 24 Apr 25 04:30:01 PM PDT 24 13166502668 ps
T268 /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2942852428 Apr 25 03:59:04 PM PDT 24 Apr 25 04:06:23 PM PDT 24 3707850156 ps
T304 /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.1383567997 Apr 25 03:55:44 PM PDT 24 Apr 25 04:02:34 PM PDT 24 4156492024 ps
T305 /workspace/coverage/default/0.chip_sw_otbn_smoketest.3529111798 Apr 25 03:28:02 PM PDT 24 Apr 25 03:55:37 PM PDT 24 8175076500 ps
T306 /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.302824061 Apr 25 03:31:08 PM PDT 24 Apr 25 03:41:54 PM PDT 24 6204258130 ps
T230 /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.132688492 Apr 25 03:46:13 PM PDT 24 Apr 25 04:24:11 PM PDT 24 19396949777 ps
T307 /workspace/coverage/default/91.chip_sw_all_escalation_resets.2262888012 Apr 25 03:58:59 PM PDT 24 Apr 25 04:08:56 PM PDT 24 6027857752 ps
T308 /workspace/coverage/default/0.chip_sw_alert_handler_escalation.3786048316 Apr 25 03:23:37 PM PDT 24 Apr 25 03:30:32 PM PDT 24 4706616954 ps
T309 /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.4140791929 Apr 25 03:56:49 PM PDT 24 Apr 25 04:04:16 PM PDT 24 4375541100 ps
T310 /workspace/coverage/default/2.chip_sw_rv_timer_irq.397729085 Apr 25 03:44:16 PM PDT 24 Apr 25 03:48:00 PM PDT 24 3190084760 ps
T269 /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.888562350 Apr 25 03:50:41 PM PDT 24 Apr 25 03:58:30 PM PDT 24 4119385512 ps
T609 /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.3434428100 Apr 25 03:30:00 PM PDT 24 Apr 25 03:36:46 PM PDT 24 3875042750 ps
T358 /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3824083957 Apr 25 03:33:11 PM PDT 24 Apr 25 03:40:44 PM PDT 24 18077564528 ps
T87 /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.1682855778 Apr 25 03:45:09 PM PDT 24 Apr 25 03:57:08 PM PDT 24 5807510240 ps
T478 /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.4080822972 Apr 25 03:57:54 PM PDT 24 Apr 25 04:05:17 PM PDT 24 3197009436 ps
T610 /workspace/coverage/default/2.chip_sw_example_rom.1272941723 Apr 25 03:40:30 PM PDT 24 Apr 25 03:42:47 PM PDT 24 2441184228 ps
T611 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.1265346639 Apr 25 03:33:00 PM PDT 24 Apr 25 04:44:08 PM PDT 24 19222346219 ps
T612 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.2756476256 Apr 25 03:23:12 PM PDT 24 Apr 25 03:26:27 PM PDT 24 3407520908 ps
T613 /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.2627871837 Apr 25 03:23:48 PM PDT 24 Apr 25 03:42:11 PM PDT 24 5351665936 ps
T614 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2669892960 Apr 25 03:39:09 PM PDT 24 Apr 25 04:01:12 PM PDT 24 7059201057 ps
T75 /workspace/coverage/default/0.chip_sw_usbdev_pincfg.2441130646 Apr 25 03:25:27 PM PDT 24 Apr 25 05:40:17 PM PDT 24 31485700890 ps
T351 /workspace/coverage/default/2.chip_sw_entropy_src_csrng.2780801537 Apr 25 03:44:34 PM PDT 24 Apr 25 04:08:11 PM PDT 24 7749304904 ps
T615 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3127039388 Apr 25 03:24:48 PM PDT 24 Apr 25 03:52:19 PM PDT 24 11370164113 ps
T384 /workspace/coverage/default/83.chip_sw_all_escalation_resets.1881311269 Apr 25 03:57:45 PM PDT 24 Apr 25 04:10:33 PM PDT 24 5891646172 ps
T457 /workspace/coverage/default/40.chip_sw_all_escalation_resets.3501689353 Apr 25 03:55:10 PM PDT 24 Apr 25 04:04:55 PM PDT 24 5446997688 ps
T616 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2094854580 Apr 25 03:30:59 PM PDT 24 Apr 25 03:36:18 PM PDT 24 4838509448 ps
T297 /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.1471003275 Apr 25 03:42:52 PM PDT 24 Apr 25 03:50:38 PM PDT 24 3456647170 ps
T617 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.314560275 Apr 25 03:45:44 PM PDT 24 Apr 25 03:53:53 PM PDT 24 3536433320 ps
T86 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1775506626 Apr 25 03:45:09 PM PDT 24 Apr 25 03:51:28 PM PDT 24 5009916214 ps
T263 /workspace/coverage/default/0.chip_sw_inject_scramble_seed.2053861059 Apr 25 03:24:27 PM PDT 24 Apr 25 06:45:22 PM PDT 24 63656000724 ps
T618 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2055146364 Apr 25 03:48:21 PM PDT 24 Apr 25 03:59:26 PM PDT 24 4449569720 ps
T619 /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1420843390 Apr 25 03:25:24 PM PDT 24 Apr 25 06:43:25 PM PDT 24 254450997248 ps
T620 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.1105713740 Apr 25 03:30:50 PM PDT 24 Apr 25 03:44:07 PM PDT 24 10462374808 ps
T259 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.1880316494 Apr 25 03:32:29 PM PDT 24 Apr 25 03:42:43 PM PDT 24 5031371447 ps
T621 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.3300066217 Apr 25 03:33:44 PM PDT 24 Apr 25 03:38:59 PM PDT 24 2348519712 ps
T622 /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.3951610709 Apr 25 03:24:33 PM PDT 24 Apr 25 03:28:22 PM PDT 24 2961519288 ps
T623 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2951429704 Apr 25 03:24:47 PM PDT 24 Apr 25 03:34:16 PM PDT 24 4312997496 ps
T624 /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.2265903556 Apr 25 03:22:56 PM PDT 24 Apr 25 07:05:02 PM PDT 24 78050480264 ps
T149 /workspace/coverage/default/2.chip_plic_all_irqs_10.1925485339 Apr 25 03:45:54 PM PDT 24 Apr 25 03:55:09 PM PDT 24 4329830678 ps
T445 /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.3745576913 Apr 25 04:02:33 PM PDT 24 Apr 25 04:10:48 PM PDT 24 3613336584 ps
T510 /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3075546970 Apr 25 03:56:55 PM PDT 24 Apr 25 04:02:06 PM PDT 24 3930391600 ps
T479 /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2727258403 Apr 25 03:53:19 PM PDT 24 Apr 25 04:00:28 PM PDT 24 3631439768 ps
T22 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.841844217 Apr 25 03:43:37 PM PDT 24 Apr 25 04:14:04 PM PDT 24 20893712600 ps
T625 /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.2466323968 Apr 25 03:44:13 PM PDT 24 Apr 25 03:49:21 PM PDT 24 2701049358 ps
T626 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.1073203491 Apr 25 03:35:30 PM PDT 24 Apr 25 03:46:50 PM PDT 24 5997536200 ps
T10 /workspace/coverage/default/1.chip_sw_spi_device_pass_through.4011029159 Apr 25 03:30:25 PM PDT 24 Apr 25 03:47:19 PM PDT 24 7432660710 ps
T627 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2213284055 Apr 25 03:37:27 PM PDT 24 Apr 25 03:47:27 PM PDT 24 4259361032 ps
T628 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1976762522 Apr 25 03:26:10 PM PDT 24 Apr 25 03:39:29 PM PDT 24 5140359496 ps
T629 /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.3976653387 Apr 25 03:49:08 PM PDT 24 Apr 25 03:55:22 PM PDT 24 7749260022 ps
T630 /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.2474064 Apr 25 03:54:58 PM PDT 24 Apr 25 04:01:31 PM PDT 24 4224403112 ps
T631 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.4031513574 Apr 25 03:43:13 PM PDT 24 Apr 25 03:46:52 PM PDT 24 2552986326 ps
T632 /workspace/coverage/default/1.chip_sw_aes_idle.2936640300 Apr 25 03:33:33 PM PDT 24 Apr 25 03:37:18 PM PDT 24 2632021422 ps
T633 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.3708147896 Apr 25 03:46:28 PM PDT 24 Apr 25 03:50:59 PM PDT 24 3456858257 ps
T199 /workspace/coverage/default/6.chip_sw_all_escalation_resets.1448796799 Apr 25 03:50:43 PM PDT 24 Apr 25 04:01:11 PM PDT 24 5972767966 ps
T634 /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.2871316791 Apr 25 03:28:17 PM PDT 24 Apr 25 03:34:12 PM PDT 24 3547208514 ps
T635 /workspace/coverage/default/1.chip_sw_aes_enc.3142334974 Apr 25 03:32:41 PM PDT 24 Apr 25 03:37:06 PM PDT 24 2656457560 ps
T39 /workspace/coverage/default/0.chip_sw_spi_device_tpm.675059001 Apr 25 03:24:34 PM PDT 24 Apr 25 03:31:10 PM PDT 24 3884146729 ps
T298 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.3029895520 Apr 25 03:25:53 PM PDT 24 Apr 25 03:36:02 PM PDT 24 7976113830 ps
T636 /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.4206684468 Apr 25 03:48:32 PM PDT 24 Apr 25 03:53:29 PM PDT 24 2313550222 ps
T637 /workspace/coverage/default/2.chip_sw_edn_sw_mode.3942914074 Apr 25 03:42:53 PM PDT 24 Apr 25 04:04:04 PM PDT 24 5521815732 ps
T494 /workspace/coverage/default/61.chip_sw_all_escalation_resets.1748291132 Apr 25 03:56:45 PM PDT 24 Apr 25 04:06:55 PM PDT 24 4743744954 ps
T233 /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.4091920021 Apr 25 03:42:28 PM PDT 24 Apr 25 05:09:46 PM PDT 24 50047497880 ps
T638 /workspace/coverage/default/2.chip_sw_otbn_smoketest.1131778233 Apr 25 03:48:50 PM PDT 24 Apr 25 04:32:19 PM PDT 24 10779374128 ps
T437 /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.3441411711 Apr 25 03:58:55 PM PDT 24 Apr 25 04:04:10 PM PDT 24 3249061502 ps
T639 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.3565622893 Apr 25 03:29:18 PM PDT 24 Apr 25 03:34:29 PM PDT 24 3906644180 ps
T640 /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.4137404193 Apr 25 03:25:15 PM PDT 24 Apr 25 03:33:48 PM PDT 24 5294229428 ps
T467 /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.1230044178 Apr 25 03:52:25 PM PDT 24 Apr 25 03:58:59 PM PDT 24 3443163736 ps
T492 /workspace/coverage/default/58.chip_sw_all_escalation_resets.4154025284 Apr 25 03:57:00 PM PDT 24 Apr 25 04:07:37 PM PDT 24 5460743092 ps
T641 /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.3389171277 Apr 25 03:49:24 PM PDT 24 Apr 25 03:53:32 PM PDT 24 3488350292 ps
T642 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.4216391319 Apr 25 03:26:27 PM PDT 24 Apr 25 03:37:09 PM PDT 24 4764212200 ps
T643 /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.3481294169 Apr 25 03:30:18 PM PDT 24 Apr 25 03:54:48 PM PDT 24 9534229313 ps
T644 /workspace/coverage/default/1.chip_sw_kmac_idle.2001122925 Apr 25 03:37:57 PM PDT 24 Apr 25 03:43:23 PM PDT 24 3068047990 ps
T448 /workspace/coverage/default/55.chip_sw_all_escalation_resets.3120213786 Apr 25 03:55:26 PM PDT 24 Apr 25 04:07:31 PM PDT 24 5508845876 ps
T645 /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.3392241197 Apr 25 03:39:41 PM PDT 24 Apr 25 04:09:34 PM PDT 24 8247665304 ps
T471 /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2153283558 Apr 25 03:59:06 PM PDT 24 Apr 25 04:04:42 PM PDT 24 3332263800 ps
T349 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.3198782779 Apr 25 03:29:15 PM PDT 24 Apr 25 03:39:52 PM PDT 24 3964389438 ps
T413 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.2403555501 Apr 25 03:41:43 PM PDT 24 Apr 25 04:26:48 PM PDT 24 20312753303 ps
T172 /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.2839324179 Apr 25 03:45:34 PM PDT 24 Apr 25 03:58:57 PM PDT 24 9013451252 ps
T646 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.2316598904 Apr 25 03:23:58 PM PDT 24 Apr 25 03:37:40 PM PDT 24 7554181468 ps
T647 /workspace/coverage/default/92.chip_sw_all_escalation_resets.3834912502 Apr 25 03:58:54 PM PDT 24 Apr 25 04:09:03 PM PDT 24 5523664920 ps
T648 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.1611998221 Apr 25 03:33:45 PM PDT 24 Apr 25 03:53:23 PM PDT 24 6840613454 ps
T53 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1105774220 Apr 25 03:24:40 PM PDT 24 Apr 25 03:51:27 PM PDT 24 20904166484 ps
T649 /workspace/coverage/default/0.chip_sw_aon_timer_irq.3448508743 Apr 25 03:23:29 PM PDT 24 Apr 25 03:29:12 PM PDT 24 3038420594 ps
T650 /workspace/coverage/default/52.chip_sw_all_escalation_resets.1819974023 Apr 25 03:55:25 PM PDT 24 Apr 25 04:08:56 PM PDT 24 5223354884 ps
T651 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2504244934 Apr 25 03:49:10 PM PDT 24 Apr 25 04:08:53 PM PDT 24 9152604342 ps
T418 /workspace/coverage/default/67.chip_sw_all_escalation_resets.3452612876 Apr 25 03:57:48 PM PDT 24 Apr 25 04:08:33 PM PDT 24 5544199050 ps
T652 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.250482249 Apr 25 03:28:10 PM PDT 24 Apr 25 03:33:36 PM PDT 24 2832857869 ps
T281 /workspace/coverage/default/5.chip_sw_all_escalation_resets.1185881002 Apr 25 03:51:43 PM PDT 24 Apr 25 04:00:18 PM PDT 24 4114944784 ps
T8 /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1535916768 Apr 25 03:27:22 PM PDT 24 Apr 25 03:31:48 PM PDT 24 2825943652 ps
T102 /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.1252401985 Apr 25 03:23:09 PM PDT 24 Apr 25 03:32:33 PM PDT 24 3423304952 ps
T49 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.897827366 Apr 25 03:23:40 PM PDT 24 Apr 25 03:28:04 PM PDT 24 2871069416 ps
T241 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.642664532 Apr 25 03:24:12 PM PDT 24 Apr 25 03:44:12 PM PDT 24 10818030952 ps
T166 /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.1584625294 Apr 25 03:43:22 PM PDT 24 Apr 25 03:52:03 PM PDT 24 4717841962 ps
T653 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.1499885604 Apr 25 03:25:14 PM PDT 24 Apr 25 03:29:20 PM PDT 24 2416155965 ps
T270 /workspace/coverage/default/79.chip_sw_all_escalation_resets.2013436389 Apr 25 04:00:25 PM PDT 24 Apr 25 04:09:37 PM PDT 24 4934538992 ps
T41 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.2018416271 Apr 25 03:30:50 PM PDT 24 Apr 25 08:04:40 PM PDT 24 79771878774 ps
T81 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.2232294232 Apr 25 03:27:31 PM PDT 24 Apr 25 04:28:01 PM PDT 24 16144266784 ps
T654 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.3556167680 Apr 25 03:50:01 PM PDT 24 Apr 25 03:58:17 PM PDT 24 4074733909 ps
T141 /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.3381396930 Apr 25 03:23:17 PM PDT 24 Apr 25 03:30:54 PM PDT 24 9400167953 ps
T193 /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.1007202586 Apr 25 03:24:00 PM PDT 24 Apr 25 03:28:02 PM PDT 24 3299279115 ps
T508 /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.1249126051 Apr 25 03:54:16 PM PDT 24 Apr 25 04:00:24 PM PDT 24 3650968184 ps
T655 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.3414660298 Apr 25 03:30:02 PM PDT 24 Apr 25 04:32:13 PM PDT 24 20544506419 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%