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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.22 92.38 82.42 90.36 94.36 97.38 84.43


Total test records in report: 908
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T656 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.3101552495 Apr 25 03:42:43 PM PDT 24 Apr 25 04:03:59 PM PDT 24 7214682598 ps
T493 /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.909938805 Apr 25 03:55:59 PM PDT 24 Apr 25 04:01:41 PM PDT 24 3429395100 ps
T356 /workspace/coverage/default/23.chip_sw_all_escalation_resets.810040006 Apr 25 03:54:08 PM PDT 24 Apr 25 04:04:21 PM PDT 24 4864955560 ps
T657 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.4247736026 Apr 25 03:24:05 PM PDT 24 Apr 25 03:35:22 PM PDT 24 11048817756 ps
T658 /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.339725433 Apr 25 03:50:48 PM PDT 24 Apr 25 04:04:07 PM PDT 24 9645312765 ps
T659 /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.2916615105 Apr 25 03:30:04 PM PDT 24 Apr 25 03:33:35 PM PDT 24 2594465504 ps
T502 /workspace/coverage/default/11.chip_sw_all_escalation_resets.2105581529 Apr 25 03:51:47 PM PDT 24 Apr 25 04:01:13 PM PDT 24 5135435058 ps
T660 /workspace/coverage/default/0.chip_sw_aes_entropy.691692188 Apr 25 03:23:32 PM PDT 24 Apr 25 03:27:21 PM PDT 24 2836503432 ps
T661 /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.3571444189 Apr 25 03:23:47 PM PDT 24 Apr 25 03:27:46 PM PDT 24 2765335752 ps
T662 /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.1356750699 Apr 25 03:25:46 PM PDT 24 Apr 25 03:33:49 PM PDT 24 4250311480 ps
T663 /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.4053394293 Apr 25 03:32:32 PM PDT 24 Apr 25 03:41:02 PM PDT 24 4433626390 ps
T336 /workspace/coverage/default/2.chip_sw_pattgen_ios.2043109992 Apr 25 03:39:30 PM PDT 24 Apr 25 03:44:32 PM PDT 24 3540984018 ps
T481 /workspace/coverage/default/31.chip_sw_all_escalation_resets.2735496793 Apr 25 03:53:42 PM PDT 24 Apr 25 04:02:29 PM PDT 24 4450275966 ps
T664 /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.1489786841 Apr 25 03:26:23 PM PDT 24 Apr 25 03:35:44 PM PDT 24 4395151472 ps
T665 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.910394431 Apr 25 03:50:47 PM PDT 24 Apr 25 04:01:37 PM PDT 24 4883043286 ps
T9 /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3560964867 Apr 25 03:41:29 PM PDT 24 Apr 25 03:45:27 PM PDT 24 2617449167 ps
T97 /workspace/coverage/default/0.chip_sw_sleep_pin_wake.488217387 Apr 25 03:23:56 PM PDT 24 Apr 25 03:31:07 PM PDT 24 6046910040 ps
T666 /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3313362962 Apr 25 03:44:28 PM PDT 24 Apr 25 03:55:32 PM PDT 24 18487209048 ps
T667 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.315494643 Apr 25 03:27:53 PM PDT 24 Apr 25 03:58:37 PM PDT 24 7325236286 ps
T234 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.357953732 Apr 25 03:42:10 PM PDT 24 Apr 25 05:21:19 PM PDT 24 46584818035 ps
T668 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.1681299116 Apr 25 03:42:27 PM PDT 24 Apr 25 03:53:48 PM PDT 24 4458953483 ps
T669 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1169710946 Apr 25 03:26:06 PM PDT 24 Apr 25 03:52:48 PM PDT 24 13980547868 ps
T670 /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.3612522163 Apr 25 03:24:11 PM PDT 24 Apr 25 03:32:28 PM PDT 24 4611758948 ps
T671 /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.141526922 Apr 25 03:42:44 PM PDT 24 Apr 25 03:46:16 PM PDT 24 2760246264 ps
T672 /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.1654674743 Apr 25 03:24:46 PM PDT 24 Apr 25 03:29:33 PM PDT 24 2531252166 ps
T142 /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.2841700532 Apr 25 03:44:50 PM PDT 24 Apr 25 03:56:13 PM PDT 24 8747869592 ps
T673 /workspace/coverage/default/0.chip_sw_gpio_smoketest.3845169188 Apr 25 03:29:49 PM PDT 24 Apr 25 03:33:17 PM PDT 24 2646081111 ps
T480 /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.3604915032 Apr 25 03:51:00 PM PDT 24 Apr 25 03:59:48 PM PDT 24 3623185444 ps
T674 /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.137036590 Apr 25 03:25:44 PM PDT 24 Apr 25 03:37:03 PM PDT 24 4131298240 ps
T675 /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.3533227260 Apr 25 03:51:07 PM PDT 24 Apr 25 03:57:30 PM PDT 24 4001545880 ps
T473 /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2871378923 Apr 25 03:59:19 PM PDT 24 Apr 25 04:06:36 PM PDT 24 4409320568 ps
T676 /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.2615147460 Apr 25 03:41:22 PM PDT 24 Apr 25 03:45:30 PM PDT 24 4695391032 ps
T677 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.1688135928 Apr 25 03:24:38 PM PDT 24 Apr 25 03:37:13 PM PDT 24 4254795864 ps
T483 /workspace/coverage/default/16.chip_sw_all_escalation_resets.2248346991 Apr 25 03:51:55 PM PDT 24 Apr 25 04:04:59 PM PDT 24 5403913480 ps
T366 /workspace/coverage/default/1.chip_sw_aon_timer_irq.2845019763 Apr 25 03:31:56 PM PDT 24 Apr 25 03:38:00 PM PDT 24 4361165616 ps
T371 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.2154679749 Apr 25 03:24:12 PM PDT 24 Apr 25 03:36:37 PM PDT 24 5193637548 ps
T678 /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.1008506616 Apr 25 03:44:58 PM PDT 24 Apr 25 03:54:07 PM PDT 24 5148938604 ps
T495 /workspace/coverage/default/57.chip_sw_all_escalation_resets.211920226 Apr 25 03:58:52 PM PDT 24 Apr 25 04:10:45 PM PDT 24 4337775512 ps
T406 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3400304415 Apr 25 03:42:02 PM PDT 24 Apr 25 03:43:56 PM PDT 24 1988358999 ps
T679 /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.1708533887 Apr 25 03:29:23 PM PDT 24 Apr 25 03:35:31 PM PDT 24 3004689712 ps
T680 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2957693667 Apr 25 03:37:47 PM PDT 24 Apr 25 03:47:32 PM PDT 24 5359766073 ps
T200 /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.172280039 Apr 25 03:24:53 PM PDT 24 Apr 25 03:32:47 PM PDT 24 4865222360 ps
T681 /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.1639939207 Apr 25 03:36:11 PM PDT 24 Apr 25 04:17:27 PM PDT 24 21964033134 ps
T682 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.2121215346 Apr 25 03:26:33 PM PDT 24 Apr 25 03:34:28 PM PDT 24 4595919150 ps
T683 /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1887709849 Apr 25 03:24:54 PM PDT 24 Apr 25 03:31:39 PM PDT 24 4006616576 ps
T684 /workspace/coverage/default/0.chip_sw_hmac_smoketest.643061838 Apr 25 03:28:11 PM PDT 24 Apr 25 03:33:22 PM PDT 24 2498738330 ps
T321 /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.3488281244 Apr 25 03:46:07 PM PDT 24 Apr 25 03:56:56 PM PDT 24 3936501288 ps
T685 /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.439272731 Apr 25 03:51:26 PM PDT 24 Apr 25 04:00:39 PM PDT 24 6981446169 ps
T686 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.942865528 Apr 25 03:26:55 PM PDT 24 Apr 25 03:39:06 PM PDT 24 8708482480 ps
T486 /workspace/coverage/default/51.chip_sw_all_escalation_resets.1965040448 Apr 25 04:01:57 PM PDT 24 Apr 25 04:14:00 PM PDT 24 5261275476 ps
T687 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3628244316 Apr 25 03:45:50 PM PDT 24 Apr 25 03:56:26 PM PDT 24 4859889543 ps
T688 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1870590103 Apr 25 03:30:19 PM PDT 24 Apr 25 03:59:25 PM PDT 24 14826206737 ps
T689 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.3796989521 Apr 25 03:24:25 PM PDT 24 Apr 25 03:43:48 PM PDT 24 8264761364 ps
T401 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.973812033 Apr 25 03:36:18 PM PDT 24 Apr 25 04:06:58 PM PDT 24 20843414200 ps
T690 /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.2968272578 Apr 25 03:35:18 PM PDT 24 Apr 25 03:44:57 PM PDT 24 5948302468 ps
T691 /workspace/coverage/default/0.chip_sw_uart_smoketest.3120018027 Apr 25 03:29:33 PM PDT 24 Apr 25 03:33:23 PM PDT 24 2356526344 ps
T482 /workspace/coverage/default/12.chip_sw_all_escalation_resets.695774629 Apr 25 03:51:35 PM PDT 24 Apr 25 04:05:06 PM PDT 24 5450424232 ps
T692 /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.2190764012 Apr 25 03:30:01 PM PDT 24 Apr 25 03:40:07 PM PDT 24 4287753288 ps
T451 /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.663869260 Apr 25 03:58:48 PM PDT 24 Apr 25 04:05:51 PM PDT 24 3895823600 ps
T693 /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.328422033 Apr 25 03:48:58 PM PDT 24 Apr 25 03:53:08 PM PDT 24 2619230536 ps
T694 /workspace/coverage/default/1.chip_sw_uart_smoketest.2742178350 Apr 25 03:40:00 PM PDT 24 Apr 25 03:45:10 PM PDT 24 3165456742 ps
T402 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1131351886 Apr 25 03:45:33 PM PDT 24 Apr 25 03:51:12 PM PDT 24 7017587938 ps
T425 /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2992507326 Apr 25 03:56:03 PM PDT 24 Apr 25 04:03:22 PM PDT 24 3338016300 ps
T695 /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.2453739671 Apr 25 03:26:17 PM PDT 24 Apr 25 03:33:34 PM PDT 24 4159389796 ps
T235 /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.3660307435 Apr 25 03:29:16 PM PDT 24 Apr 25 04:57:59 PM PDT 24 49255600856 ps
T696 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.3980027251 Apr 25 03:24:54 PM PDT 24 Apr 25 03:34:44 PM PDT 24 5004651142 ps
T697 /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.3326080061 Apr 25 03:44:41 PM PDT 24 Apr 25 03:54:32 PM PDT 24 4121585790 ps
T698 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1649748891 Apr 25 03:45:43 PM PDT 24 Apr 25 03:58:19 PM PDT 24 4506932628 ps
T699 /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.872864235 Apr 25 03:23:34 PM PDT 24 Apr 25 03:27:24 PM PDT 24 2596008104 ps
T700 /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.3657634942 Apr 25 03:52:33 PM PDT 24 Apr 25 03:58:58 PM PDT 24 5790432026 ps
T501 /workspace/coverage/default/43.chip_sw_all_escalation_resets.3089092126 Apr 25 03:55:19 PM PDT 24 Apr 25 04:09:41 PM PDT 24 5265903400 ps
T509 /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.4179886265 Apr 25 03:54:37 PM PDT 24 Apr 25 04:01:52 PM PDT 24 3568397354 ps
T701 /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.4103711449 Apr 25 03:53:47 PM PDT 24 Apr 25 04:00:04 PM PDT 24 6720850266 ps
T702 /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.3744045858 Apr 25 03:44:59 PM PDT 24 Apr 25 03:55:35 PM PDT 24 4827319100 ps
T491 /workspace/coverage/default/19.chip_sw_all_escalation_resets.3896407323 Apr 25 03:53:20 PM PDT 24 Apr 25 04:02:44 PM PDT 24 5533602896 ps
T703 /workspace/coverage/default/1.chip_sw_kmac_smoketest.1234813878 Apr 25 03:40:06 PM PDT 24 Apr 25 03:44:23 PM PDT 24 2394089050 ps
T704 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.3055734852 Apr 25 03:32:37 PM PDT 24 Apr 25 03:48:23 PM PDT 24 8033149780 ps
T311 /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.55656084 Apr 25 03:46:06 PM PDT 24 Apr 25 03:50:10 PM PDT 24 2586359940 ps
T705 /workspace/coverage/default/0.chip_sw_usbdev_vbus.1600897060 Apr 25 03:24:01 PM PDT 24 Apr 25 03:29:06 PM PDT 24 2542471632 ps
T204 /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.2997160045 Apr 25 03:25:07 PM PDT 24 Apr 25 03:27:29 PM PDT 24 3462642050 ps
T706 /workspace/coverage/default/1.chip_sival_flash_info_access.3642819050 Apr 25 03:29:54 PM PDT 24 Apr 25 03:34:47 PM PDT 24 3194394634 ps
T707 /workspace/coverage/default/2.chip_sw_inject_scramble_seed.452544850 Apr 25 03:40:52 PM PDT 24 Apr 25 07:13:09 PM PDT 24 63710474481 ps
T708 /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.2113742405 Apr 25 03:30:09 PM PDT 24 Apr 25 03:34:18 PM PDT 24 2746026324 ps
T709 /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.2314240885 Apr 25 03:51:28 PM PDT 24 Apr 25 04:14:08 PM PDT 24 12120776770 ps
T710 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.2469947662 Apr 25 03:25:41 PM PDT 24 Apr 25 04:39:05 PM PDT 24 18627104387 ps
T186 /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.2832979802 Apr 25 03:40:08 PM PDT 24 Apr 25 06:40:49 PM PDT 24 58072257204 ps
T711 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.3316396552 Apr 25 03:29:46 PM PDT 24 Apr 25 03:41:13 PM PDT 24 3724199660 ps
T712 /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.3392133410 Apr 25 03:49:09 PM PDT 24 Apr 25 04:06:19 PM PDT 24 9650729192 ps
T505 /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.1135682338 Apr 25 03:58:43 PM PDT 24 Apr 25 04:05:46 PM PDT 24 2992773364 ps
T713 /workspace/coverage/default/0.chip_sw_rv_timer_irq.3763650832 Apr 25 03:24:37 PM PDT 24 Apr 25 03:28:31 PM PDT 24 2315815400 ps
T714 /workspace/coverage/default/0.chip_tap_straps_testunlock0.654051541 Apr 25 03:26:17 PM PDT 24 Apr 25 03:33:09 PM PDT 24 5289677712 ps
T715 /workspace/coverage/default/3.chip_sw_data_integrity_escalation.3775476430 Apr 25 03:52:06 PM PDT 24 Apr 25 04:04:00 PM PDT 24 5578382920 ps
T466 /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.883032190 Apr 25 03:51:24 PM PDT 24 Apr 25 03:58:18 PM PDT 24 3125682088 ps
T716 /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.2387881108 Apr 25 03:24:24 PM PDT 24 Apr 25 03:52:21 PM PDT 24 11039554065 ps
T282 /workspace/coverage/default/7.chip_sw_all_escalation_resets.508761682 Apr 25 03:50:07 PM PDT 24 Apr 25 04:07:10 PM PDT 24 6077217786 ps
T717 /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.1057078893 Apr 25 03:41:57 PM PDT 24 Apr 25 03:49:35 PM PDT 24 3603989646 ps
T407 /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.1919010029 Apr 25 03:24:29 PM PDT 24 Apr 25 03:26:43 PM PDT 24 2177012719 ps
T718 /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.3793486056 Apr 25 03:41:04 PM PDT 24 Apr 25 07:12:38 PM PDT 24 77190731864 ps
T408 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.3911412755 Apr 25 03:41:22 PM PDT 24 Apr 25 03:43:02 PM PDT 24 2182866444 ps
T719 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3543092856 Apr 25 03:31:25 PM PDT 24 Apr 25 03:42:09 PM PDT 24 4561740374 ps
T720 /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.1108734867 Apr 25 03:23:13 PM PDT 24 Apr 25 03:30:50 PM PDT 24 4535723284 ps
T721 /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.2821136487 Apr 25 03:50:52 PM PDT 24 Apr 25 03:55:34 PM PDT 24 2169218070 ps
T722 /workspace/coverage/default/0.chip_sw_csrng_kat_test.1760848102 Apr 25 03:24:09 PM PDT 24 Apr 25 03:29:28 PM PDT 24 2865657960 ps
T723 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.1256058131 Apr 25 03:25:47 PM PDT 24 Apr 25 03:29:50 PM PDT 24 3442047889 ps
T724 /workspace/coverage/default/1.chip_sw_hmac_smoketest.2394685656 Apr 25 03:42:12 PM PDT 24 Apr 25 03:47:24 PM PDT 24 3045793990 ps
T474 /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.928220118 Apr 25 03:55:38 PM PDT 24 Apr 25 04:03:12 PM PDT 24 4430222720 ps
T725 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.914896238 Apr 25 03:30:31 PM PDT 24 Apr 25 04:00:17 PM PDT 24 7365661376 ps
T374 /workspace/coverage/default/18.chip_sw_all_escalation_resets.71439584 Apr 25 03:52:38 PM PDT 24 Apr 25 04:04:19 PM PDT 24 4664138048 ps
T726 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.765876435 Apr 25 03:26:30 PM PDT 24 Apr 25 03:36:06 PM PDT 24 6242996692 ps
T727 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.2415866994 Apr 25 03:42:56 PM PDT 24 Apr 25 03:56:07 PM PDT 24 6638134288 ps
T728 /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.1003095 Apr 25 03:23:58 PM PDT 24 Apr 25 04:05:19 PM PDT 24 29252995469 ps
T729 /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.1644310356 Apr 25 03:47:53 PM PDT 24 Apr 25 03:53:14 PM PDT 24 2653718254 ps
T375 /workspace/coverage/default/73.chip_sw_all_escalation_resets.1265812134 Apr 25 03:59:13 PM PDT 24 Apr 25 04:12:18 PM PDT 24 5840746416 ps
T730 /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.534959611 Apr 25 03:25:22 PM PDT 24 Apr 25 03:45:08 PM PDT 24 12233037818 ps
T731 /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.766196815 Apr 25 03:45:13 PM PDT 24 Apr 25 03:52:44 PM PDT 24 3636536154 ps
T732 /workspace/coverage/default/2.chip_sw_edn_kat.3723568833 Apr 25 03:45:29 PM PDT 24 Apr 25 03:54:37 PM PDT 24 3936913040 ps
T733 /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3242540329 Apr 25 03:50:20 PM PDT 24 Apr 25 04:43:18 PM PDT 24 12520292068 ps
T252 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.308515144 Apr 25 03:41:53 PM PDT 24 Apr 25 03:45:47 PM PDT 24 3295162878 ps
T734 /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.2780918800 Apr 25 03:24:06 PM PDT 24 Apr 25 03:33:33 PM PDT 24 3812483512 ps
T735 /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.3184816570 Apr 25 03:29:38 PM PDT 24 Apr 25 03:33:04 PM PDT 24 2522670154 ps
T433 /workspace/coverage/default/81.chip_sw_all_escalation_resets.378992672 Apr 25 03:57:56 PM PDT 24 Apr 25 04:09:31 PM PDT 24 6093208042 ps
T458 /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.1952883225 Apr 25 03:54:14 PM PDT 24 Apr 25 04:02:15 PM PDT 24 4306020218 ps
T736 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.2059990334 Apr 25 03:36:02 PM PDT 24 Apr 25 04:02:08 PM PDT 24 6049445596 ps
T737 /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.638444079 Apr 25 03:52:21 PM PDT 24 Apr 25 04:05:53 PM PDT 24 4870199656 ps
T132 /workspace/coverage/default/0.chip_jtag_mem_access.40842085 Apr 25 03:17:09 PM PDT 24 Apr 25 03:37:26 PM PDT 24 13863583713 ps
T738 /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.1471051889 Apr 25 03:23:48 PM PDT 24 Apr 25 06:27:27 PM PDT 24 58319288853 ps
T739 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1518837587 Apr 25 03:44:12 PM PDT 24 Apr 25 04:28:05 PM PDT 24 34008652005 ps
T740 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2302487408 Apr 25 03:24:45 PM PDT 24 Apr 25 04:34:38 PM PDT 24 17220522320 ps
T367 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.314247842 Apr 25 03:28:00 PM PDT 24 Apr 25 03:38:01 PM PDT 24 4140151112 ps
T741 /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.3173873371 Apr 25 03:48:20 PM PDT 24 Apr 25 03:54:18 PM PDT 24 2770074664 ps
T449 /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.3086778911 Apr 25 03:52:32 PM PDT 24 Apr 25 04:01:03 PM PDT 24 4192121608 ps
T742 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.142238650 Apr 25 03:42:33 PM PDT 24 Apr 25 03:59:50 PM PDT 24 10077853797 ps
T743 /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.3322378300 Apr 25 03:55:10 PM PDT 24 Apr 25 04:01:40 PM PDT 24 3632190014 ps
T503 /workspace/coverage/default/71.chip_sw_all_escalation_resets.1530721427 Apr 25 03:58:23 PM PDT 24 Apr 25 04:12:04 PM PDT 24 6178037848 ps
T421 /workspace/coverage/default/89.chip_sw_all_escalation_resets.2273988304 Apr 25 04:00:23 PM PDT 24 Apr 25 04:08:15 PM PDT 24 5884660236 ps
T744 /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.4247010049 Apr 25 03:30:17 PM PDT 24 Apr 25 03:36:06 PM PDT 24 3405103894 ps
T455 /workspace/coverage/default/28.chip_sw_all_escalation_resets.720592534 Apr 25 03:57:02 PM PDT 24 Apr 25 04:08:26 PM PDT 24 4848099228 ps
T745 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.1513149769 Apr 25 03:25:22 PM PDT 24 Apr 25 03:31:31 PM PDT 24 6267089708 ps
T746 /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.1042237383 Apr 25 03:49:53 PM PDT 24 Apr 25 03:58:44 PM PDT 24 6480550394 ps
T747 /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.3364728655 Apr 25 03:51:49 PM PDT 24 Apr 25 04:02:44 PM PDT 24 7160976274 ps
T322 /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.4083388940 Apr 25 03:34:35 PM PDT 24 Apr 25 03:45:55 PM PDT 24 5938065380 ps
T416 /workspace/coverage/default/99.chip_sw_all_escalation_resets.1932497638 Apr 25 03:59:48 PM PDT 24 Apr 25 04:10:08 PM PDT 24 4882703144 ps
T748 /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.1453498282 Apr 25 03:29:08 PM PDT 24 Apr 25 03:36:47 PM PDT 24 4661420020 ps
T461 /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.4196678167 Apr 25 03:59:17 PM PDT 24 Apr 25 04:04:27 PM PDT 24 3297684268 ps
T749 /workspace/coverage/default/5.chip_sw_data_integrity_escalation.1715003013 Apr 25 03:50:41 PM PDT 24 Apr 25 04:05:43 PM PDT 24 5701425820 ps
T424 /workspace/coverage/default/25.chip_sw_all_escalation_resets.586999766 Apr 25 03:54:27 PM PDT 24 Apr 25 04:04:43 PM PDT 24 5857563230 ps
T750 /workspace/coverage/default/0.chip_sw_aes_enc.141877625 Apr 25 03:24:12 PM PDT 24 Apr 25 03:29:32 PM PDT 24 3078634300 ps
T751 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.2990651257 Apr 25 03:39:01 PM PDT 24 Apr 25 03:50:38 PM PDT 24 5325738426 ps
T752 /workspace/coverage/default/2.chip_sw_hmac_smoketest.1105270917 Apr 25 03:48:52 PM PDT 24 Apr 25 03:54:46 PM PDT 24 2445907148 ps
T434 /workspace/coverage/default/42.chip_sw_all_escalation_resets.3664196284 Apr 25 03:55:22 PM PDT 24 Apr 25 04:05:52 PM PDT 24 4985028144 ps
T753 /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1681777476 Apr 25 03:58:11 PM PDT 24 Apr 25 04:05:29 PM PDT 24 4479521240 ps
T754 /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.324798773 Apr 25 03:29:34 PM PDT 24 Apr 25 03:35:12 PM PDT 24 4216145280 ps
T755 /workspace/coverage/default/1.chip_sw_example_rom.2180710076 Apr 25 03:26:54 PM PDT 24 Apr 25 03:28:49 PM PDT 24 2844938400 ps
T444 /workspace/coverage/default/95.chip_sw_all_escalation_resets.1812768227 Apr 25 03:59:39 PM PDT 24 Apr 25 04:13:29 PM PDT 24 5257628088 ps
T485 /workspace/coverage/default/4.chip_sw_all_escalation_resets.4057682460 Apr 25 03:48:44 PM PDT 24 Apr 25 04:01:46 PM PDT 24 6613629832 ps
T756 /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.3032086101 Apr 25 03:43:50 PM PDT 24 Apr 25 03:51:28 PM PDT 24 4657111332 ps
T511 /workspace/coverage/default/78.chip_sw_all_escalation_resets.1511140029 Apr 25 03:57:46 PM PDT 24 Apr 25 04:06:43 PM PDT 24 5413546436 ps
T757 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3746877485 Apr 25 03:41:55 PM PDT 24 Apr 25 04:09:39 PM PDT 24 12807618308 ps
T758 /workspace/coverage/default/2.chip_sw_otbn_randomness.1267447728 Apr 25 03:42:12 PM PDT 24 Apr 25 04:00:06 PM PDT 24 5379271648 ps
T376 /workspace/coverage/default/3.chip_sw_all_escalation_resets.1639764698 Apr 25 03:50:00 PM PDT 24 Apr 25 04:03:22 PM PDT 24 5825405682 ps
T11 /workspace/coverage/default/2.chip_sw_spi_device_pass_through.2706022065 Apr 25 03:40:21 PM PDT 24 Apr 25 03:53:39 PM PDT 24 6277910471 ps
T759 /workspace/coverage/default/3.chip_tap_straps_rma.1413185957 Apr 25 03:49:56 PM PDT 24 Apr 25 03:55:18 PM PDT 24 4248676318 ps
T506 /workspace/coverage/default/8.chip_sw_all_escalation_resets.1230883156 Apr 25 03:50:27 PM PDT 24 Apr 25 04:01:15 PM PDT 24 5380214500 ps
T760 /workspace/coverage/default/45.chip_sw_all_escalation_resets.2090715244 Apr 25 03:55:22 PM PDT 24 Apr 25 04:09:42 PM PDT 24 5034251884 ps
T761 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.3907208816 Apr 25 03:23:33 PM PDT 24 Apr 25 03:34:08 PM PDT 24 4084715972 ps
T762 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.490945219 Apr 25 03:36:41 PM PDT 24 Apr 25 03:45:34 PM PDT 24 3177681932 ps
T763 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.3063398965 Apr 25 03:33:31 PM PDT 24 Apr 25 03:54:25 PM PDT 24 5952355043 ps
T764 /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.1782431633 Apr 25 03:24:18 PM PDT 24 Apr 25 03:46:17 PM PDT 24 7815408070 ps
T765 /workspace/coverage/default/2.chip_sw_hmac_enc_idle.2448330576 Apr 25 03:43:29 PM PDT 24 Apr 25 03:47:33 PM PDT 24 2256433258 ps
T766 /workspace/coverage/default/1.chip_sw_uart_tx_rx.945378462 Apr 25 03:28:14 PM PDT 24 Apr 25 03:36:32 PM PDT 24 3381588948 ps
T767 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.159530245 Apr 25 03:41:23 PM PDT 24 Apr 25 03:58:12 PM PDT 24 5835166287 ps
T768 /workspace/coverage/default/2.rom_keymgr_functest.1184732506 Apr 25 03:47:46 PM PDT 24 Apr 25 03:58:09 PM PDT 24 5035094000 ps
T301 /workspace/coverage/default/41.chip_sw_all_escalation_resets.2136436147 Apr 25 03:55:00 PM PDT 24 Apr 25 04:07:30 PM PDT 24 6205863960 ps
T769 /workspace/coverage/default/1.chip_sw_example_concurrency.4176982623 Apr 25 03:28:43 PM PDT 24 Apr 25 03:32:52 PM PDT 24 2925013104 ps
T243 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.2957832724 Apr 25 03:32:53 PM PDT 24 Apr 25 03:38:43 PM PDT 24 3625975816 ps
T770 /workspace/coverage/default/4.chip_sw_data_integrity_escalation.3920334639 Apr 25 03:49:40 PM PDT 24 Apr 25 04:00:36 PM PDT 24 6257697272 ps
T488 /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1006154774 Apr 25 03:58:00 PM PDT 24 Apr 25 04:06:11 PM PDT 24 3582495722 ps
T771 /workspace/coverage/default/0.chip_sw_edn_sw_mode.3003700193 Apr 25 03:25:30 PM PDT 24 Apr 25 03:56:24 PM PDT 24 8913907804 ps
T772 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.3391989037 Apr 25 03:37:11 PM PDT 24 Apr 25 03:41:34 PM PDT 24 2894806614 ps
T773 /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.631007862 Apr 25 03:33:49 PM PDT 24 Apr 25 03:42:22 PM PDT 24 8480307563 ps
T774 /workspace/coverage/default/48.chip_sw_all_escalation_resets.3785214216 Apr 25 03:56:57 PM PDT 24 Apr 25 04:06:02 PM PDT 24 4276153070 ps
T775 /workspace/coverage/default/1.chip_sw_gpio_smoketest.392176191 Apr 25 03:41:33 PM PDT 24 Apr 25 03:46:09 PM PDT 24 3614380496 ps
T776 /workspace/coverage/default/29.chip_sw_all_escalation_resets.712817725 Apr 25 03:53:54 PM PDT 24 Apr 25 04:03:37 PM PDT 24 5108777996 ps
T103 /workspace/coverage/default/0.chip_sw_usbdev_pullup.3142773904 Apr 25 03:22:22 PM PDT 24 Apr 25 03:26:35 PM PDT 24 3044420292 ps
T456 /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1546882630 Apr 25 03:59:55 PM PDT 24 Apr 25 04:06:22 PM PDT 24 4179465008 ps
T777 /workspace/coverage/default/0.chip_sw_aes_smoketest.3018204076 Apr 25 03:29:41 PM PDT 24 Apr 25 03:33:21 PM PDT 24 2735918264 ps
T778 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.2385974120 Apr 25 03:47:37 PM PDT 24 Apr 25 03:55:20 PM PDT 24 4493728736 ps
T779 /workspace/coverage/default/1.chip_sw_flash_ctrl_access.1624456380 Apr 25 03:28:42 PM PDT 24 Apr 25 03:47:11 PM PDT 24 5131520492 ps
T337 /workspace/coverage/default/0.chip_sw_pattgen_ios.324330388 Apr 25 03:24:05 PM PDT 24 Apr 25 03:28:21 PM PDT 24 2800821224 ps
T780 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.3261367244 Apr 25 03:23:53 PM PDT 24 Apr 25 03:28:26 PM PDT 24 2772797044 ps
T781 /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.1255968631 Apr 25 03:42:30 PM PDT 24 Apr 25 04:00:37 PM PDT 24 5077557530 ps
T782 /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.2845139452 Apr 25 03:41:45 PM PDT 24 Apr 25 03:47:05 PM PDT 24 2266220480 ps
T783 /workspace/coverage/default/1.chip_sw_otbn_smoketest.713232686 Apr 25 03:39:48 PM PDT 24 Apr 25 04:16:04 PM PDT 24 10159935622 ps
T784 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.1002557177 Apr 25 03:23:20 PM PDT 24 Apr 25 03:33:35 PM PDT 24 3964783820 ps
T324 /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.558151929 Apr 25 03:35:42 PM PDT 24 Apr 25 04:30:53 PM PDT 24 12951708876 ps
T231 /workspace/coverage/default/1.chip_sw_flash_init.2549243197 Apr 25 03:28:47 PM PDT 24 Apr 25 04:03:54 PM PDT 24 22731307400 ps
T785 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3781577434 Apr 25 03:37:14 PM PDT 24 Apr 25 03:41:08 PM PDT 24 2465816207 ps
T786 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.252617606 Apr 25 03:44:36 PM PDT 24 Apr 25 03:59:09 PM PDT 24 5199719464 ps
T325 /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.1560618118 Apr 25 03:43:46 PM PDT 24 Apr 25 04:47:54 PM PDT 24 13848507360 ps
T787 /workspace/coverage/default/74.chip_sw_all_escalation_resets.2071259649 Apr 25 03:57:43 PM PDT 24 Apr 25 04:09:39 PM PDT 24 5348207788 ps
T361 /workspace/coverage/default/0.chip_sival_flash_info_access.2177536550 Apr 25 03:25:58 PM PDT 24 Apr 25 03:30:59 PM PDT 24 3448115390 ps
T788 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.3289213097 Apr 25 03:25:49 PM PDT 24 Apr 25 03:38:25 PM PDT 24 5264752856 ps
T439 /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3420200691 Apr 25 04:02:32 PM PDT 24 Apr 25 04:11:07 PM PDT 24 3470392952 ps
T489 /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.2603997822 Apr 25 03:55:55 PM PDT 24 Apr 25 04:01:09 PM PDT 24 3632466064 ps
T497 /workspace/coverage/default/90.chip_sw_all_escalation_resets.4018896609 Apr 25 03:59:12 PM PDT 24 Apr 25 04:08:09 PM PDT 24 5349472148 ps
T789 /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.679686453 Apr 25 03:51:14 PM PDT 24 Apr 25 04:21:50 PM PDT 24 8645159000 ps
T790 /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.1290242519 Apr 25 03:37:04 PM PDT 24 Apr 25 03:40:37 PM PDT 24 2429093696 ps
T791 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.2487031382 Apr 25 03:43:48 PM PDT 24 Apr 25 03:48:37 PM PDT 24 3117234269 ps
T792 /workspace/coverage/default/2.chip_sw_aes_enc.2967824069 Apr 25 03:42:27 PM PDT 24 Apr 25 03:48:23 PM PDT 24 3625749544 ps
T232 /workspace/coverage/default/2.chip_sw_flash_init.4119648289 Apr 25 03:41:40 PM PDT 24 Apr 25 04:26:19 PM PDT 24 25846066086 ps
T12 /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.957885400 Apr 25 03:40:41 PM PDT 24 Apr 25 03:48:39 PM PDT 24 4595256071 ps
T793 /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.5802808 Apr 25 03:31:10 PM PDT 24 Apr 25 03:50:56 PM PDT 24 7169871296 ps
T111 /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.3522710084 Apr 25 03:58:17 PM PDT 24 Apr 25 04:04:19 PM PDT 24 3808179876 ps
T794 /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.2122876980 Apr 25 03:38:52 PM PDT 24 Apr 25 03:41:50 PM PDT 24 2979359000 ps
T795 /workspace/coverage/default/0.chip_sw_clkmgr_jitter.1102566248 Apr 25 03:24:28 PM PDT 24 Apr 25 03:27:44 PM PDT 24 2678412861 ps
T484 /workspace/coverage/default/82.chip_sw_all_escalation_resets.587289436 Apr 25 03:57:46 PM PDT 24 Apr 25 04:05:04 PM PDT 24 4524281432 ps
T27 /workspace/coverage/default/1.chip_sw_gpio.2689560538 Apr 25 03:28:37 PM PDT 24 Apr 25 03:36:13 PM PDT 24 3808313060 ps
T796 /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.2512830704 Apr 25 03:32:31 PM PDT 24 Apr 25 03:42:13 PM PDT 24 6423606682 ps
T283 /workspace/coverage/default/36.chip_sw_all_escalation_resets.2165057961 Apr 25 03:55:15 PM PDT 24 Apr 25 04:05:50 PM PDT 24 6291348680 ps
T453 /workspace/coverage/default/76.chip_sw_all_escalation_resets.1873961815 Apr 25 04:00:04 PM PDT 24 Apr 25 04:09:48 PM PDT 24 4639718104 ps
T460 /workspace/coverage/default/17.chip_sw_all_escalation_resets.2881781473 Apr 25 03:53:34 PM PDT 24 Apr 25 04:03:16 PM PDT 24 5179675072 ps
T797 /workspace/coverage/default/0.chip_sw_power_idle_load.2252396244 Apr 25 03:25:28 PM PDT 24 Apr 25 03:36:38 PM PDT 24 3790854136 ps
T798 /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.2243046619 Apr 25 03:48:44 PM PDT 24 Apr 25 03:51:54 PM PDT 24 2345320664 ps
T799 /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.3498314104 Apr 25 03:53:46 PM PDT 24 Apr 25 03:59:48 PM PDT 24 3536742788 ps
T800 /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.4087013949 Apr 25 03:51:37 PM PDT 24 Apr 25 03:57:45 PM PDT 24 2956101158 ps
T801 /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.3284068931 Apr 25 03:37:33 PM PDT 24 Apr 25 04:10:27 PM PDT 24 20758383302 ps
T802 /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.3147969283 Apr 25 03:51:07 PM PDT 24 Apr 25 03:59:41 PM PDT 24 5346368253 ps
T446 /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.2772701687 Apr 25 03:49:58 PM PDT 24 Apr 25 03:56:38 PM PDT 24 3344228528 ps
T36 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1632628870 Apr 25 03:23:33 PM PDT 24 Apr 25 03:29:45 PM PDT 24 5804550582 ps
T803 /workspace/coverage/default/2.chip_sw_alert_handler_escalation.2150240988 Apr 25 03:42:28 PM PDT 24 Apr 25 03:51:10 PM PDT 24 5011968300 ps
T395 /workspace/coverage/default/2.chip_sw_edn_boot_mode.161617981 Apr 25 03:45:08 PM PDT 24 Apr 25 03:52:21 PM PDT 24 2986158296 ps
T373 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.764296859 Apr 25 03:38:00 PM PDT 24 Apr 25 03:49:14 PM PDT 24 4354301176 ps
T804 /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.3362246567 Apr 25 03:39:17 PM PDT 24 Apr 25 04:06:24 PM PDT 24 10861785032 ps
T805 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.3394694524 Apr 25 03:42:07 PM PDT 24 Apr 25 03:46:59 PM PDT 24 3636449475 ps
T806 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2533719936 Apr 25 03:28:19 PM PDT 24 Apr 25 03:36:21 PM PDT 24 3950753672 ps
T409 /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.1372294321 Apr 25 03:27:00 PM PDT 24 Apr 25 03:29:25 PM PDT 24 3672402487 ps
T807 /workspace/coverage/default/0.chip_sw_kmac_smoketest.2225173301 Apr 25 03:33:39 PM PDT 24 Apr 25 03:37:25 PM PDT 24 2712464552 ps
T808 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.3492875152 Apr 25 03:24:35 PM PDT 24 Apr 25 03:26:25 PM PDT 24 2268979846 ps
T440 /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.2524337575 Apr 25 03:52:18 PM PDT 24 Apr 25 03:58:38 PM PDT 24 4127240548 ps
T809 /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.1930270190 Apr 25 03:53:39 PM PDT 24 Apr 25 04:01:46 PM PDT 24 3485529484 ps
T810 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.3888270152 Apr 25 03:47:09 PM PDT 24 Apr 25 03:55:56 PM PDT 24 5696619582 ps
T146 /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.1749812680 Apr 25 03:30:29 PM PDT 24 Apr 25 03:39:43 PM PDT 24 4205593237 ps
T215 /workspace/coverage/default/2.chip_plic_all_irqs_20.3360541314 Apr 25 03:44:48 PM PDT 24 Apr 25 03:56:54 PM PDT 24 4545283002 ps
T42 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.2624447346 Apr 25 03:30:30 PM PDT 24 Apr 25 07:54:24 PM PDT 24 80828356244 ps
T811 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1321618056 Apr 25 03:31:28 PM PDT 24 Apr 25 04:04:27 PM PDT 24 17901490791 ps
T812 /workspace/coverage/default/1.chip_sw_flash_crash_alert.4221185161 Apr 25 03:37:43 PM PDT 24 Apr 25 03:47:54 PM PDT 24 4732973000 ps
T256 /workspace/coverage/default/1.chip_sw_plic_sw_irq.3671059867 Apr 25 03:40:05 PM PDT 24 Apr 25 03:45:00 PM PDT 24 3332058140 ps
T813 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.2181605730 Apr 25 03:49:26 PM PDT 24 Apr 25 03:58:07 PM PDT 24 3947733496 ps
T313 /workspace/coverage/default/1.chip_sw_power_sleep_load.3702332169 Apr 25 03:39:45 PM PDT 24 Apr 25 03:49:18 PM PDT 24 11095070374 ps
T37 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2048549927 Apr 25 03:33:04 PM PDT 24 Apr 25 03:40:19 PM PDT 24 5188755320 ps
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