Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3858796	1			T76	493		T77	2192		T78	2217
values[2]	760344	1			T76	187		T77	588		T78	198
values[3]	104628	1			T76	74		T77	1		T78	1
values[4]	55352	1			T76	3		T234	5		T471	381
values[5]	37733	1			T234	6		T471	276		T367	1
values[6]	28228	1			T234	6		T471	232		T386	42
values[7]	22919	1			T234	5		T471	128		T386	32
values[8]	19492	1			T234	6		T471	94		T386	17
values[9]	17364	1			T234	5		T471	61		T386	9
values[10]	15898	1			T234	5		T471	36		T386	3
values[11]	15086	1			T234	5		T471	29		T386	4
values[12]	14378	1			T234	5		T471	20		T386	6
values[13]	13655	1			T234	5		T471	21		T386	5
values[14]	13002	1			T234	5		T471	17		T386	8
values[15]	12825	1			T234	5		T471	29		T386	6
values[16]	12294	1			T234	6		T471	31		T386	5
values[17]	11856	1			T234	5		T471	49		T386	7
values[18]	11309	1			T234	5		T471	40		T386	12
values[19]	11078	1			T234	5		T471	55		T386	9
values[20]	10396	1			T234	5		T471	31		T386	4
values[21]	9998	1			T234	5		T471	26		T386	8
values[22]	9966	1			T234	5		T471	14		T386	3
values[23]	9493	1			T234	5		T471	16		T386	1
values[24]	8797	1			T234	5		T471	19		T386	1
values[25]	8931	1			T234	5		T471	11		T386	1
values[26]	8485	1			T234	5		T471	3		T386	1
values[27]	7970	1			T234	5		T471	4		T386	3
values[28]	7431	1			T234	5		T471	6		T386	9
values[29]	7278	1			T234	6		T471	4		T386	6
values[30]	6630	1			T234	5		T471	6		T386	7
values[31]	6258	1			T234	5		T471	6		T386	2
values[32]	6007	1			T234	5		T471	3		T386	2
values[33]	5581	1			T234	5		T471	4		T386	1
values[34]	5134	1			T234	5		T471	3		T386	1
values[35]	4768	1			T234	5		T471	6		T386	1
values[36]	4367	1			T234	5		T471	4		T386	2
values[37]	4108	1			T234	5		T471	7		T386	1
values[38]	3908	1			T234	5		T471	7		T386	1
values[39]	3757	1			T234	5		T471	7		T386	3
values[40]	3554	1			T234	5		T471	7		T386	3
values[41]	3354	1			T234	5		T471	4		T386	2
values[42]	3353	1			T234	5		T471	5		T386	1
values[43]	3380	1			T234	5		T471	5		T386	2
values[44]	3231	1			T234	5		T471	7		T386	2
values[45]	3160	1			T234	5		T471	5		T386	3
values[46]	3205	1			T234	5		T471	5		T386	1
values[47]	3159	1			T234	5		T471	18		T386	1
values[48]	2905	1			T234	6		T471	6		T386	1
values[49]	2966	1			T234	7		T471	10		T386	2
values[50]	2850	1			T234	6		T471	5		T386	1
values[51]	2831	1			T234	5		T471	7		T386	2
values[52]	2878	1			T234	5		T471	9		T386	2
values[53]	2740	1			T234	5		T471	3		T386	2
values[54]	2597	1			T234	5		T471	4		T386	1
values[55]	2545	1			T234	5		T471	7		T386	3
values[56]	2503	1			T234	5		T471	6		T386	2
values[57]	2479	1			T234	5		T471	9		T386	1
values[58]	2386	1			T234	5		T471	5		T386	2
values[59]	2378	1			T234	6		T471	9		T386	2
values[60]	2387	1			T234	5		T471	10		T386	2
values[61]	2644	1			T234	5		T471	11		T386	4
values[62]	4341	1			T234	5		T471	14		T386	8
values[63]	17576	1			T234	53		T471	70		T386	26
values[64]	221313	1			T234	795		T471	292		T386	76

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4911172	1			T76	608		T77	2558		T78	2035
values[2]	803928	1			T76	185		T77	648		T78	132
values[3]	73355	1			T76	56		T77	12		T78	1
values[4]	13465	1			T76	21		T234	13		T476	3
values[5]	5134	1			T76	7		T234	3		T471	1
values[6]	2972	1			T76	2		T234	1		T478	4
values[7]	2386	1			T234	1		T478	1		T367	4
values[8]	2148	1			T234	1		T478	1		T367	1
values[9]	1935	1			T234	1		T386	3		T492	2
values[10]	1687	1			T234	1		T386	3		T492	2
values[11]	1544	1			T234	1		T386	1		T492	2
values[12]	1345	1			T234	1		T386	1		T492	2
values[13]	1309	1			T234	1		T386	2		T492	3
values[14]	1272	1			T234	1		T386	1		T492	2
values[15]	1216	1			T234	2		T386	1		T492	2
values[16]	1138	1			T234	1		T386	3		T492	2
values[17]	1068	1			T234	1		T386	2		T492	2
values[18]	959	1			T234	1		T386	1		T492	2
values[19]	945	1			T234	1		T386	2		T492	2
values[20]	897	1			T234	1		T386	1		T492	2
values[21]	929	1			T234	1		T386	3		T492	2
values[22]	911	1			T234	1		T386	2		T492	2
values[23]	881	1			T234	1		T386	6		T492	2
values[24]	781	1			T234	1		T386	3		T492	2
values[25]	701	1			T234	1		T386	1		T492	2
values[26]	704	1			T234	1		T386	1		T492	2
values[27]	647	1			T234	1		T386	2		T492	2
values[28]	629	1			T234	1		T386	1		T492	2
values[29]	552	1			T234	1		T386	1		T492	2
values[30]	619	1			T234	1		T386	2		T492	2
values[31]	608	1			T234	1		T386	5		T492	2
values[32]	558	1			T234	1		T386	2		T492	2
values[33]	550	1			T234	1		T386	2		T492	2
values[34]	507	1			T234	1		T386	5		T492	2
values[35]	479	1			T234	1		T386	2		T492	2
values[36]	507	1			T234	1		T386	4		T492	2
values[37]	539	1			T234	1		T386	4		T492	2
values[38]	489	1			T234	1		T386	1		T492	2
values[39]	470	1			T234	1		T386	1		T492	2
values[40]	434	1			T234	1		T386	3		T492	2
values[41]	436	1			T234	1		T386	4		T492	2
values[42]	473	1			T234	1		T386	2		T492	2
values[43]	499	1			T234	1		T386	4		T492	2
values[44]	468	1			T234	1		T386	3		T492	2
values[45]	459	1			T234	1		T386	4		T492	2
values[46]	454	1			T234	1		T386	3		T492	2
values[47]	417	1			T234	1		T386	1		T492	3
values[48]	413	1			T234	1		T386	1		T492	2
values[49]	409	1			T234	1		T386	2		T492	2
values[50]	413	1			T234	1		T386	5		T492	2
values[51]	428	1			T234	1		T386	5		T492	2
values[52]	431	1			T234	1		T386	2		T492	2
values[53]	422	1			T234	1		T386	1		T492	2
values[54]	401	1			T234	1		T386	1		T492	2
values[55]	400	1			T234	1		T386	2		T492	2
values[56]	407	1			T234	1		T386	3		T492	2
values[57]	384	1			T234	1		T386	2		T492	2
values[58]	354	1			T234	1		T386	1		T492	2
values[59]	343	1			T234	1		T386	2		T492	2
values[60]	348	1			T234	1		T386	1		T492	2
values[61]	401	1			T234	1		T386	2		T492	2
values[62]	680	1			T234	1		T386	2		T492	2
values[63]	3139	1			T234	17		T386	32		T492	4
values[64]	27695	1			T234	130		T386	66		T492	418

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	631540	1			T76	6		T77	20		T78	16
values[2]	2783615	1			T76	74		T77	2231		T78	1917
values[3]	1138303	1			T76	537		T77	603		T78	170
values[4]	141021	1			T76	123		T233	3		T234	5
values[5]	73472	1			T76	8		T234	6		T471	490
values[6]	49241	1			T76	5		T234	5		T471	309
values[7]	35994	1			T234	5		T471	172		T484	3
values[8]	28026	1			T234	5		T471	130		T484	3
values[9]	24083	1			T234	5		T471	77		T386	29
values[10]	21456	1			T234	5		T471	47		T386	27
values[11]	19365	1			T234	5		T471	44		T386	49
values[12]	18052	1			T234	5		T471	61		T386	15
values[13]	16778	1			T234	5		T471	41		T386	12
values[14]	15940	1			T234	5		T471	38		T386	17
values[15]	15669	1			T234	5		T471	38		T386	13
values[16]	14710	1			T234	5		T471	23		T386	13
values[17]	14237	1			T234	5		T471	21		T386	19
values[18]	13354	1			T234	5		T471	27		T386	9
values[19]	12759	1			T234	5		T471	23		T386	8
values[20]	12117	1			T234	5		T471	18		T386	9
values[21]	11527	1			T234	5		T471	22		T386	7
values[22]	11311	1			T234	5		T471	17		T386	10
values[23]	11137	1			T234	5		T471	20		T386	7
values[24]	10709	1			T234	5		T471	15		T386	5
values[25]	9872	1			T234	6		T471	8		T386	7
values[26]	9558	1			T234	5		T471	5		T386	8
values[27]	9327	1			T234	5		T471	7		T386	11
values[28]	8781	1			T234	5		T471	7		T386	8
values[29]	8316	1			T234	5		T471	10		T386	5
values[30]	7697	1			T234	5		T471	11		T386	1
values[31]	6998	1			T234	5		T471	7		T386	1
values[32]	6492	1			T234	5		T471	6		T386	1
values[33]	6019	1			T234	5		T471	7		T386	2
values[34]	5620	1			T234	5		T471	5		T386	1
values[35]	5101	1			T234	5		T471	12		T386	1
values[36]	4689	1			T234	5		T471	22		T386	3
values[37]	4628	1			T234	5		T471	13		T386	5
values[38]	4285	1			T234	5		T471	10		T386	1
values[39]	4142	1			T234	5		T471	12		T386	1
values[40]	3806	1			T234	5		T471	8		T386	2
values[41]	3781	1			T234	7		T471	4		T386	6
values[42]	3635	1			T234	5		T471	19		T386	2
values[43]	3573	1			T234	5		T471	17		T386	1
values[44]	3545	1			T234	5		T471	8		T386	1
values[45]	3518	1			T234	5		T471	8		T386	1
values[46]	3481	1			T234	5		T471	7		T386	1
values[47]	3340	1			T234	5		T471	6		T386	7
values[48]	3353	1			T234	5		T471	6		T386	2
values[49]	3218	1			T234	5		T471	9		T386	1
values[50]	3234	1			T234	5		T471	8		T386	1
values[51]	3152	1			T234	5		T471	11		T386	2
values[52]	3030	1			T234	5		T471	11		T386	2
values[53]	2922	1			T234	5		T471	4		T386	1
values[54]	2956	1			T234	5		T471	3		T386	2
values[55]	2972	1			T234	5		T471	14		T386	1
values[56]	2910	1			T234	5		T471	4		T386	2
values[57]	2943	1			T234	6		T471	3		T386	5
values[58]	2857	1			T234	5		T471	4		T386	3
values[59]	2780	1			T234	5		T471	6		T386	1
values[60]	2695	1			T234	6		T471	3		T386	2
values[61]	2878	1			T234	5		T471	4		T386	1
values[62]	4178	1			T234	6		T471	10		T386	6
values[63]	17999	1			T234	80		T471	41		T386	29
values[64]	211271	1			T234	861		T471	146		T386	104