Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1871489	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

26147898

1

T1

3498

T2

19816

T3

9736

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	18066414	1			T1	865		T2	15618		T3	3290
values[0x0]	8596205	1			T1	2633		T2	4198		T3	6446
values[0x1]	1356768	1			T1	119		T2	4274		T3	403

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	632779	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

27386608

1

T1

3617

T2

24090

T3

10139

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12867002	1			T1	1809		T2	12045		T3	5070
valid_sources[0x01]	12866528	1			T1	1808		T2	12045		T3	5069
valid_sources[0x02]	36589	1			T52	2		T477	39		T142	78
valid_sources[0x03]	37251	1			T477	14		T142	65		T143	889
valid_sources[0x04]	37053	1			T80	5		T81	6		T142	74
valid_sources[0x05]	35919	1			T52	4		T477	85		T142	86
valid_sources[0x06]	37371	1			T477	13		T142	102		T143	795
valid_sources[0x07]	37312	1			T142	88		T143	732		T330	73
valid_sources[0x08]	36270	1			T52	5		T477	3		T142	78
valid_sources[0x09]	37188	1			T142	86		T143	755		T330	81
valid_sources[0x0a]	36980	1			T81	7		T142	90		T143	693
valid_sources[0x0b]	36452	1			T81	4		T142	74		T143	819
valid_sources[0x0c]	36229	1			T80	1		T52	9		T142	99
valid_sources[0x0d]	36786	1			T80	2		T142	74		T143	794
valid_sources[0x0e]	37253	1			T371	5		T142	92		T143	784
valid_sources[0x0f]	36913	1			T52	1		T371	3		T477	4
valid_sources[0x10]	35921	1			T81	1		T142	96		T143	755
valid_sources[0x11]	35843	1			T80	3		T142	75		T143	735
valid_sources[0x12]	37137	1			T80	1		T371	2		T142	85
valid_sources[0x13]	36546	1			T80	2		T52	2		T477	59
valid_sources[0x14]	37513	1			T371	1		T142	73		T143	839
valid_sources[0x15]	36870	1			T142	82		T143	773		T330	91
valid_sources[0x16]	37608	1			T142	85		T143	799		T330	79
valid_sources[0x17]	36536	1			T52	2		T142	94		T143	789
valid_sources[0x18]	36438	1			T142	88		T143	877		T330	82
valid_sources[0x19]	37007	1			T477	27		T142	66		T143	741
valid_sources[0x1a]	36922	1			T52	3		T142	89		T143	817
valid_sources[0x1b]	37804	1			T477	6		T142	71		T143	774
valid_sources[0x1c]	36338	1			T477	14		T142	77		T143	804
valid_sources[0x1d]	37190	1			T142	79		T143	842		T330	76
valid_sources[0x1e]	36453	1			T81	1		T63	39		T371	1
valid_sources[0x1f]	36342	1			T80	3		T52	2		T142	73
valid_sources[0x20]	37070	1			T371	2		T142	100		T143	830

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

17358967

1

T1

865

T2

15618

T3

3290

values[0x0]

all_enables

biggest_size

8549581

1

T1

2633

T2

4198

T3

6446

values[0x1]

all_enables

biggest_size

239350

1

T49

20

T80

21

T81

20

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2838199	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

449656

1

T76

89

T77

15

T78

335

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1114344	1			T76	242		T77	61		T78	829
values[0x0]	1059002	1			T76	227		T77	8		T78	817
values[0x1]	1114509	1			T76	288		T77	54		T78	770

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2197114	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1090741

1

T76

244

T77

41

T78

793

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51917	1			T76	11		T77	3		T78	22
valid_sources[0x01]	50464	1			T76	20		T77	2		T78	52
valid_sources[0x02]	51370	1			T77	4		T78	26		T233	3
valid_sources[0x03]	51093	1			T76	18		T77	1		T78	41
valid_sources[0x04]	50810	1			T76	12		T77	4		T78	39
valid_sources[0x05]	51757	1			T76	17		T77	4		T78	35
valid_sources[0x06]	51122	1			T77	1		T78	35		T233	2
valid_sources[0x07]	51882	1			T76	1		T78	31		T234	16
valid_sources[0x08]	51752	1			T76	1		T77	1		T78	35
valid_sources[0x09]	51035	1			T76	21		T77	2		T78	43
valid_sources[0x0a]	50334	1			T76	9		T77	1		T78	30
valid_sources[0x0b]	51266	1			T76	2		T78	41		T233	6
valid_sources[0x0c]	52614	1			T76	2		T77	2		T78	50
valid_sources[0x0d]	51845	1			T76	27		T77	2		T78	43
valid_sources[0x0e]	51839	1			T76	7		T77	3		T78	29
valid_sources[0x0f]	51687	1			T76	35		T77	1		T78	44
valid_sources[0x10]	50790	1			T76	16		T77	2		T78	26
valid_sources[0x11]	51958	1			T76	12		T77	5		T78	53
valid_sources[0x12]	52015	1			T76	17		T78	40		T233	5
valid_sources[0x13]	50938	1			T76	17		T77	1		T78	35
valid_sources[0x14]	50828	1			T76	5		T77	1		T78	36
valid_sources[0x15]	51775	1			T76	3		T78	47		T234	16
valid_sources[0x16]	51295	1			T76	14		T77	3		T78	36
valid_sources[0x17]	51492	1			T76	26		T78	31		T233	4
valid_sources[0x18]	51153	1			T76	18		T77	5		T78	42
valid_sources[0x19]	51608	1			T76	22		T78	49		T234	17
valid_sources[0x1a]	51276	1			T76	26		T77	1		T78	50
valid_sources[0x1b]	51644	1			T76	10		T77	2		T78	36
valid_sources[0x1c]	50561	1			T76	3		T77	2		T78	42
valid_sources[0x1d]	51241	1			T76	1		T77	3		T78	50
valid_sources[0x1e]	50403	1			T76	19		T77	3		T78	34
valid_sources[0x1f]	51395	1			T76	22		T77	1		T78	33
valid_sources[0x20]	51346	1			T76	12		T77	2		T78	58

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47341

1

T76

13

T77

6

T78

20

values[0x0]

all_enables

biggest_size

354777

1

T76

63

T77

4

T78

288

values[0x1]

all_enables

biggest_size

47538

1

T76

13

T77

5

T78

27

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3021924	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

491998

1

T76

140

T77

15

T78

318

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1204279	1			T76	292		T77	61		T78	729
values[0x0]	1106325	1			T76	287		T77	13		T78	693
values[0x1]	1203318	1			T76	300		T77	69		T78	746

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2320334	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1193588

1

T76

305

T77

56

T78

763

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	55850	1			T76	26		T77	1		T78	21
valid_sources[0x01]	54670	1			T76	10		T77	2		T78	75
valid_sources[0x02]	54824	1			T76	13		T77	5		T78	84
valid_sources[0x03]	55219	1			T76	11		T77	5		T78	86
valid_sources[0x04]	55161	1			T76	9		T78	41		T234	25
valid_sources[0x05]	55335	1			T76	17		T77	2		T78	63
valid_sources[0x06]	55578	1			T76	15		T77	1		T78	64
valid_sources[0x07]	55729	1			T76	6		T77	1		T78	19
valid_sources[0x08]	54058	1			T76	24		T77	1		T78	9
valid_sources[0x09]	54753	1			T76	15		T77	1		T78	36
valid_sources[0x0a]	55987	1			T76	22		T77	2		T78	72
valid_sources[0x0b]	54441	1			T76	12		T77	3		T78	24
valid_sources[0x0c]	54511	1			T76	17		T77	1		T233	2
valid_sources[0x0d]	54777	1			T76	13		T77	3		T234	18
valid_sources[0x0e]	54740	1			T76	15		T77	2		T78	69
valid_sources[0x0f]	54804	1			T76	18		T77	3		T78	53
valid_sources[0x10]	53744	1			T76	16		T77	5		T78	33
valid_sources[0x11]	55865	1			T76	15		T77	2		T78	73
valid_sources[0x12]	53972	1			T76	7		T77	3		T234	28
valid_sources[0x13]	55483	1			T76	21		T78	46		T234	20
valid_sources[0x14]	54235	1			T76	11		T77	4		T78	46
valid_sources[0x15]	55176	1			T76	9		T77	2		T78	23
valid_sources[0x16]	55822	1			T76	21		T78	17		T233	1
valid_sources[0x17]	54568	1			T76	13		T78	15		T234	15
valid_sources[0x18]	55497	1			T76	9		T77	4		T78	29
valid_sources[0x19]	54888	1			T76	5		T77	1		T78	95
valid_sources[0x1a]	55091	1			T76	12		T77	2		T78	6
valid_sources[0x1b]	55765	1			T76	9		T77	2		T234	17
valid_sources[0x1c]	54269	1			T76	10		T77	3		T78	5
valid_sources[0x1d]	53672	1			T76	15		T77	4		T78	16
valid_sources[0x1e]	54400	1			T76	21		T77	2		T78	34
valid_sources[0x1f]	55511	1			T76	5		T77	3		T78	11
valid_sources[0x20]	54243	1			T76	19		T77	1		T78	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

51910

1

T76

11

T77

3

T78

39

values[0x0]

all_enables

biggest_size

387953

1

T76

109

T77

5

T78

246

values[0x1]

all_enables

biggest_size

52135

1

T76

20

T77

7

T78

33

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2866711	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

451727

1

T76

119

T77

7

T78

277

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1124903	1			T76	239		T77	48		T78	686
values[0x0]	1068224	1			T76	271		T77	9		T78	673
values[0x1]	1125311	1			T76	243		T77	65		T78	744

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2218583	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1099855

1

T76

247

T77

47

T78

684

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52139	1			T76	15		T77	1		T78	43
valid_sources[0x01]	50969	1			T76	11		T77	2		T78	30
valid_sources[0x02]	51834	1			T76	13		T78	35		T234	20
valid_sources[0x03]	52809	1			T76	18		T78	39		T233	2
valid_sources[0x04]	51708	1			T76	11		T77	3		T78	32
valid_sources[0x05]	51692	1			T76	9		T77	4		T78	28
valid_sources[0x06]	51603	1			T76	10		T77	2		T78	17
valid_sources[0x07]	52664	1			T76	11		T77	4		T78	26
valid_sources[0x08]	52105	1			T76	13		T77	3		T78	31
valid_sources[0x09]	51314	1			T76	4		T77	2		T78	27
valid_sources[0x0a]	51553	1			T76	13		T77	3		T78	27
valid_sources[0x0b]	51990	1			T76	8		T77	3		T78	30
valid_sources[0x0c]	53068	1			T76	12		T77	5		T78	42
valid_sources[0x0d]	51978	1			T76	14		T77	2		T78	37
valid_sources[0x0e]	51490	1			T76	7		T77	2		T78	31
valid_sources[0x0f]	51582	1			T76	8		T77	3		T78	27
valid_sources[0x10]	52133	1			T76	17		T77	3		T78	38
valid_sources[0x11]	51857	1			T76	6		T77	1		T78	37
valid_sources[0x12]	51479	1			T76	16		T77	7		T78	26
valid_sources[0x13]	52183	1			T76	8		T77	3		T78	34
valid_sources[0x14]	51244	1			T76	14		T78	34		T234	19
valid_sources[0x15]	52794	1			T76	13		T77	3		T78	48
valid_sources[0x16]	51932	1			T76	4		T77	1		T78	36
valid_sources[0x17]	51743	1			T76	6		T77	6		T78	27
valid_sources[0x18]	51127	1			T76	12		T77	4		T78	32
valid_sources[0x19]	51385	1			T76	16		T77	1		T78	27
valid_sources[0x1a]	52062	1			T76	17		T78	33		T234	16
valid_sources[0x1b]	52256	1			T76	8		T77	3		T78	30
valid_sources[0x1c]	51520	1			T76	13		T77	1		T78	23
valid_sources[0x1d]	51858	1			T76	8		T78	18		T234	15
valid_sources[0x1e]	50641	1			T76	11		T77	1		T78	36
valid_sources[0x1f]	51183	1			T76	10		T78	20		T234	13
valid_sources[0x20]	52171	1			T76	12		T78	31		T234	17

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47509

1

T76

8

T77

2

T78

26

values[0x0]

all_enables

biggest_size

356671

1

T76

104

T77

2

T78

225

values[0x1]

all_enables

biggest_size

47547

1

T76

7

T77

3

T78

26