Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	387366561	39611815	0	0
DepthKnown_A	387366561	387268161	0	0
RvalidKnown_A	387366561	387268161	0	0
WreadyKnown_A	387366561	387268161	0	0
gen_passthru_fifo.paramCheckPass	902	902	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387366561	39611815	0	0
T1	64887	6458	0	0
T2	228578	23549	0	0
T3	338069	43457	0	0
T30	414871	51867	0	0
T31	228707	29478	0	0
T60	107484	12513	0	0
T64	520768	739234	0	0
T65	161886	25887	0	0
T89	279912	44250	0	0
T90	266189	22209	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387366561	387268161	0	0
T1	64887	64836	0	0
T2	228578	228527	0	0
T3	338069	337961	0	0
T30	414871	414699	0	0
T31	228707	228594	0	0
T60	107484	107429	0	0
T64	520768	520758	0	0
T65	161886	161828	0	0
T89	279912	279854	0	0
T90	266189	266138	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387366561	387268161	0	0
T1	64887	64836	0	0
T2	228578	228527	0	0
T3	338069	337961	0	0
T30	414871	414699	0	0
T31	228707	228594	0	0
T60	107484	107429	0	0
T64	520768	520758	0	0
T65	161886	161828	0	0
T89	279912	279854	0	0
T90	266189	266138	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387366561	387268161	0	0
T1	64887	64836	0	0
T2	228578	228527	0	0
T3	338069	337961	0	0
T30	414871	414699	0	0
T31	228707	228594	0	0
T60	107484	107429	0	0
T64	520768	520758	0	0
T65	161886	161828	0	0
T89	279912	279854	0	0
T90	266189	266138	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	902	902	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T60	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T89	1	1	0	0
T90	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	387366561	30200814	0	0
DepthKnown_A	387366561	387268161	0	0
RvalidKnown_A	387366561	387268161	0	0
WreadyKnown_A	387366561	387268161	0	0
gen_passthru_fifo.paramCheckPass	902	902	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387366561	30200814	0	0
T1	64887	4636	0	0
T2	228578	19664	0	0
T3	338069	37822	0	0
T30	414871	40214	0	0
T31	228707	19971	0	0
T60	107484	9469	0	0
T64	520768	733070	0	0
T65	161886	18522	0	0
T89	279912	38650	0	0
T90	266189	17636	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387366561	387268161	0	0
T1	64887	64836	0	0
T2	228578	228527	0	0
T3	338069	337961	0	0
T30	414871	414699	0	0
T31	228707	228594	0	0
T60	107484	107429	0	0
T64	520768	520758	0	0
T65	161886	161828	0	0
T89	279912	279854	0	0
T90	266189	266138	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387366561	387268161	0	0
T1	64887	64836	0	0
T2	228578	228527	0	0
T3	338069	337961	0	0
T30	414871	414699	0	0
T31	228707	228594	0	0
T60	107484	107429	0	0
T64	520768	520758	0	0
T65	161886	161828	0	0
T89	279912	279854	0	0
T90	266189	266138	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387366561	387268161	0	0
T1	64887	64836	0	0
T2	228578	228527	0	0
T3	338069	337961	0	0
T30	414871	414699	0	0
T31	228707	228594	0	0
T60	107484	107429	0	0
T64	520768	520758	0	0
T65	161886	161828	0	0
T89	279912	279854	0	0
T90	266189	266138	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	902	902	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T60	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T89	1	1	0	0
T90	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	387366561	26586204	0	0
DepthKnown_A	387366561	387268161	0	0
RvalidKnown_A	387366561	387268161	0	0
WreadyKnown_A	387366561	387268161	0	0
gen_passthru_fifo.paramCheckPass	902	902	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387366561	26586204	0	0
T1	64887	3732	0	0
T2	228578	24291	0	0
T3	338069	10536	0	0
T30	414871	20937	0	0
T31	228707	14422	0	0
T60	107484	7441	0	0
T64	520768	13237	0	0
T65	161886	9609	0	0
T89	279912	15774	0	0
T90	266189	10854	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387366561	387268161	0	0
T1	64887	64836	0	0
T2	228578	228527	0	0
T3	338069	337961	0	0
T30	414871	414699	0	0
T31	228707	228594	0	0
T60	107484	107429	0	0
T64	520768	520758	0	0
T65	161886	161828	0	0
T89	279912	279854	0	0
T90	266189	266138	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387366561	387268161	0	0
T1	64887	64836	0	0
T2	228578	228527	0	0
T3	338069	337961	0	0
T30	414871	414699	0	0
T31	228707	228594	0	0
T60	107484	107429	0	0
T64	520768	520758	0	0
T65	161886	161828	0	0
T89	279912	279854	0	0
T90	266189	266138	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387366561	387268161	0	0
T1	64887	64836	0	0
T2	228578	228527	0	0
T3	338069	337961	0	0
T30	414871	414699	0	0
T31	228707	228594	0	0
T60	107484	107429	0	0
T64	520768	520758	0	0
T65	161886	161828	0	0
T89	279912	279854	0	0
T90	266189	266138	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	902	902	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T60	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T89	1	1	0	0
T90	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	387366561	25769556	0	0
DepthKnown_A	387366561	387268161	0	0
RvalidKnown_A	387366561	387268161	0	0
WreadyKnown_A	387366561	387268161	0	0
gen_passthru_fifo.paramCheckPass	902	902	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387366561	25769556	0	0
T1	64887	3617	0	0
T2	228578	24090	0	0
T3	338069	10139	0	0
T30	414871	20249	0	0
T31	228707	14032	0	0
T60	107484	7228	0	0
T64	520768	12880	0	0
T65	161886	9332	0	0
T89	279912	15574	0	0
T90	266189	10126	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387366561	387268161	0	0
T1	64887	64836	0	0
T2	228578	228527	0	0
T3	338069	337961	0	0
T30	414871	414699	0	0
T31	228707	228594	0	0
T60	107484	107429	0	0
T64	520768	520758	0	0
T65	161886	161828	0	0
T89	279912	279854	0	0
T90	266189	266138	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387366561	387268161	0	0
T1	64887	64836	0	0
T2	228578	228527	0	0
T3	338069	337961	0	0
T30	414871	414699	0	0
T31	228707	228594	0	0
T60	107484	107429	0	0
T64	520768	520758	0	0
T65	161886	161828	0	0
T89	279912	279854	0	0
T90	266189	266138	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387366561	387268161	0	0
T1	64887	64836	0	0
T2	228578	228527	0	0
T3	338069	337961	0	0
T30	414871	414699	0	0
T31	228707	228594	0	0
T60	107484	107429	0	0
T64	520768	520758	0	0
T65	161886	161828	0	0
T89	279912	279854	0	0
T90	266189	266138	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	902	902	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T60	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T89	1	1	0	0
T90	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	467500571	92222	0	0
DepthKnown_A	467500571	467390996	0	0
RvalidKnown_A	467500571	467390996	0	0
WreadyKnown_A	467500571	467390996	0	0
gen_passthru_fifo.paramCheckPass	2792	2792	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467500571	92222	0	0
T1	64887	13	0	0
T2	228578	53	0	0
T3	338069	125	0	0
T30	414871	77	0	0
T31	228707	151	0	0
T60	107484	17	0	0
T64	520768	30	0	0
T65	161886	26	0	0
T89	279912	63	0	0
T90	266189	346	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467500571	467390996	0	0
T1	64887	64836	0	0
T2	228578	228527	0	0
T3	338069	337961	0	0
T30	414871	414699	0	0
T31	228707	228594	0	0
T60	107484	107429	0	0
T64	520768	520758	0	0
T65	161886	161828	0	0
T89	279912	279854	0	0
T90	266189	266138	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467500571	467390996	0	0
T1	64887	64836	0	0
T2	228578	228527	0	0
T3	338069	337961	0	0
T30	414871	414699	0	0
T31	228707	228594	0	0
T60	107484	107429	0	0
T64	520768	520758	0	0
T65	161886	161828	0	0
T89	279912	279854	0	0
T90	266189	266138	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467500571	467390996	0	0
T1	64887	64836	0	0
T2	228578	228527	0	0
T3	338069	337961	0	0
T30	414871	414699	0	0
T31	228707	228594	0	0
T60	107484	107429	0	0
T64	520768	520758	0	0
T65	161886	161828	0	0
T89	279912	279854	0	0
T90	266189	266138	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2792	2792	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T60	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T89	1	1	0	0
T90	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	467500571	95080	0	0
DepthKnown_A	467500571	467390996	0	0
RvalidKnown_A	467500571	467390996	0	0
WreadyKnown_A	467500571	467390996	0	0
gen_passthru_fifo.paramCheckPass	2792	2792	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467500571	95080	0	0
T1	64887	13	0	0
T2	228578	53	0	0
T3	338069	125	0	0
T30	414871	77	0	0
T31	228707	151	0	0
T60	107484	17	0	0
T64	520768	30	0	0
T65	161886	26	0	0
T89	279912	63	0	0
T90	266189	346	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467500571	467390996	0	0
T1	64887	64836	0	0
T2	228578	228527	0	0
T3	338069	337961	0	0
T30	414871	414699	0	0
T31	228707	228594	0	0
T60	107484	107429	0	0
T64	520768	520758	0	0
T65	161886	161828	0	0
T89	279912	279854	0	0
T90	266189	266138	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467500571	467390996	0	0
T1	64887	64836	0	0
T2	228578	228527	0	0
T3	338069	337961	0	0
T30	414871	414699	0	0
T31	228707	228594	0	0
T60	107484	107429	0	0
T64	520768	520758	0	0
T65	161886	161828	0	0
T89	279912	279854	0	0
T90	266189	266138	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467500571	467390996	0	0
T1	64887	64836	0	0
T2	228578	228527	0	0
T3	338069	337961	0	0
T30	414871	414699	0	0
T31	228707	228594	0	0
T60	107484	107429	0	0
T64	520768	520758	0	0
T65	161886	161828	0	0
T89	279912	279854	0	0
T90	266189	266138	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2792	2792	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T60	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T89	1	1	0	0
T90	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	467500571	48694	0	0
DepthKnown_A	467500571	467390996	0	0
RvalidKnown_A	467500571	467390996	0	0
WreadyKnown_A	467500571	467390996	0	0
gen_passthru_fifo.paramCheckPass	2792	2792	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467500571	48694	0	0
T1	64887	12	0	0
T2	228578	52	0	0
T3	338069	123	0	0
T30	414871	74	0	0
T31	228707	95	0	0
T60	107484	14	0	0
T64	520768	24	0	0
T65	161886	23	0	0
T89	279912	30	0	0
T90	266189	343	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467500571	467390996	0	0
T1	64887	64836	0	0
T2	228578	228527	0	0
T3	338069	337961	0	0
T30	414871	414699	0	0
T31	228707	228594	0	0
T60	107484	107429	0	0
T64	520768	520758	0	0
T65	161886	161828	0	0
T89	279912	279854	0	0
T90	266189	266138	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467500571	467390996	0	0
T1	64887	64836	0	0
T2	228578	228527	0	0
T3	338069	337961	0	0
T30	414871	414699	0	0
T31	228707	228594	0	0
T60	107484	107429	0	0
T64	520768	520758	0	0
T65	161886	161828	0	0
T89	279912	279854	0	0
T90	266189	266138	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467500571	467390996	0	0
T1	64887	64836	0	0
T2	228578	228527	0	0
T3	338069	337961	0	0
T30	414871	414699	0	0
T31	228707	228594	0	0
T60	107484	107429	0	0
T64	520768	520758	0	0
T65	161886	161828	0	0
T89	279912	279854	0	0
T90	266189	266138	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2792	2792	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T60	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T89	1	1	0	0
T90	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	467500571	48693	0	0
DepthKnown_A	467500571	467390996	0	0
RvalidKnown_A	467500571	467390996	0	0
WreadyKnown_A	467500571	467390996	0	0
gen_passthru_fifo.paramCheckPass	2792	2792	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467500571	48693	0	0
T1	64887	12	0	0
T2	228578	52	0	0
T3	338069	123	0	0
T30	414871	74	0	0
T31	228707	95	0	0
T60	107484	14	0	0
T64	520768	24	0	0
T65	161886	23	0	0
T89	279912	30	0	0
T90	266189	343	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467500571	467390996	0	0
T1	64887	64836	0	0
T2	228578	228527	0	0
T3	338069	337961	0	0
T30	414871	414699	0	0
T31	228707	228594	0	0
T60	107484	107429	0	0
T64	520768	520758	0	0
T65	161886	161828	0	0
T89	279912	279854	0	0
T90	266189	266138	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467500571	467390996	0	0
T1	64887	64836	0	0
T2	228578	228527	0	0
T3	338069	337961	0	0
T30	414871	414699	0	0
T31	228707	228594	0	0
T60	107484	107429	0	0
T64	520768	520758	0	0
T65	161886	161828	0	0
T89	279912	279854	0	0
T90	266189	266138	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467500571	467390996	0	0
T1	64887	64836	0	0
T2	228578	228527	0	0
T3	338069	337961	0	0
T30	414871	414699	0	0
T31	228707	228594	0	0
T60	107484	107429	0	0
T64	520768	520758	0	0
T65	161886	161828	0	0
T89	279912	279854	0	0
T90	266189	266138	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2792	2792	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T60	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T89	1	1	0	0
T90	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	467500571	43528	0	0
DepthKnown_A	467500571	467390996	0	0
RvalidKnown_A	467500571	467390996	0	0
WreadyKnown_A	467500571	467390996	0	0
gen_passthru_fifo.paramCheckPass	2792	2792	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467500571	43528	0	0
T1	64887	1	0	0
T2	228578	1	0	0
T3	338069	2	0	0
T30	414871	3	0	0
T31	228707	56	0	0
T60	107484	3	0	0
T64	520768	6	0	0
T65	161886	3	0	0
T89	279912	33	0	0
T90	266189	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467500571	467390996	0	0
T1	64887	64836	0	0
T2	228578	228527	0	0
T3	338069	337961	0	0
T30	414871	414699	0	0
T31	228707	228594	0	0
T60	107484	107429	0	0
T64	520768	520758	0	0
T65	161886	161828	0	0
T89	279912	279854	0	0
T90	266189	266138	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467500571	467390996	0	0
T1	64887	64836	0	0
T2	228578	228527	0	0
T3	338069	337961	0	0
T30	414871	414699	0	0
T31	228707	228594	0	0
T60	107484	107429	0	0
T64	520768	520758	0	0
T65	161886	161828	0	0
T89	279912	279854	0	0
T90	266189	266138	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467500571	467390996	0	0
T1	64887	64836	0	0
T2	228578	228527	0	0
T3	338069	337961	0	0
T30	414871	414699	0	0
T31	228707	228594	0	0
T60	107484	107429	0	0
T64	520768	520758	0	0
T65	161886	161828	0	0
T89	279912	279854	0	0
T90	266189	266138	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2792	2792	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T60	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T89	1	1	0	0
T90	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	467500571	46387	0	0
DepthKnown_A	467500571	467390996	0	0
RvalidKnown_A	467500571	467390996	0	0
WreadyKnown_A	467500571	467390996	0	0
gen_passthru_fifo.paramCheckPass	2792	2792	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467500571	46387	0	0
T1	64887	1	0	0
T2	228578	1	0	0
T3	338069	2	0	0
T30	414871	3	0	0
T31	228707	56	0	0
T60	107484	3	0	0
T64	520768	6	0	0
T65	161886	3	0	0
T89	279912	33	0	0
T90	266189	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467500571	467390996	0	0
T1	64887	64836	0	0
T2	228578	228527	0	0
T3	338069	337961	0	0
T30	414871	414699	0	0
T31	228707	228594	0	0
T60	107484	107429	0	0
T64	520768	520758	0	0
T65	161886	161828	0	0
T89	279912	279854	0	0
T90	266189	266138	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467500571	467390996	0	0
T1	64887	64836	0	0
T2	228578	228527	0	0
T3	338069	337961	0	0
T30	414871	414699	0	0
T31	228707	228594	0	0
T60	107484	107429	0	0
T64	520768	520758	0	0
T65	161886	161828	0	0
T89	279912	279854	0	0
T90	266189	266138	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467500571	467390996	0	0
T1	64887	64836	0	0
T2	228578	228527	0	0
T3	338069	337961	0	0
T30	414871	414699	0	0
T31	228707	228594	0	0
T60	107484	107429	0	0
T64	520768	520758	0	0
T65	161886	161828	0	0
T89	279912	279854	0	0
T90	266189	266138	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2792	2792	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T60	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T89	1	1	0	0
T90	1	1	0	0