Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T169,T49,T172
0	1	Covered	T169,T172,T52
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T169,T172,T273
1	Covered	T169,T49,T172

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T169,T172,T273
1	Covered	T169,T49,T172

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T169,T172,T52
1	1	Covered	T169,T172,T273

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T169,T49,T172
1	0	Covered	T169,T172,T273
1	1	Covered	T169,T172,T52

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T169,T172,T52

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T169,T49,T172
0	Covered	T169,T172,T273

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T169,T49,T172
0	Covered	T169,T172,T273

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	774733122	755740786	0	0
CheckNGreaterZero_A	1804	1804	0	0
GntImpliesReady_A	774733122	5443	0	0
GntImpliesValid_A	774733122	5443	0	0
GrantKnown_A	774733122	755740786	0	0
IdxKnown_A	774733122	755740786	0	0
IndexIsCorrect_A	774733122	5443	0	0
NoReadyValidNoGrant_A	774733122	0	0	0
Priority_A	774733122	5443	0	0
ReadyAndValidImplyGrant_A	774733122	5443	0	0
ReqAndReadyImplyGrant_A	774733122	5443	0	0
ReqImpliesValid_A	774733122	5443	0	0
ValidKnown_A	774733122	755740786	0	0
gen_data_port_assertion.DataFlow_A	774733122	5443	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774733122	755740786	0	0
T1	129774	129672	0	0
T2	457156	457054	0	0
T3	676138	675922	0	0
T30	829742	829398	0	0
T31	457414	457188	0	0
T60	214968	214858	0	0
T64	1041536	1041516	0	0
T65	323772	323656	0	0
T89	559824	559708	0	0
T90	532378	532276	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1804	1804	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T30	2	2	0	0
T31	2	2	0	0
T60	2	2	0	0
T64	2	2	0	0
T65	2	2	0	0
T89	2	2	0	0
T90	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774733122	5443	0	0
T41	1546116	0	0	0
T66	1097504	0	0	0
T72	200752	0	0	0
T82	978492	0	0	0
T141	1219056	0	0	0
T169	183968	1814	0	0
T172	0	1811	0	0
T178	135294	0	0	0
T197	302130	0	0	0
T228	462966	0	0	0
T273	0	1818	0	0
T275	323056	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774733122	5443	0	0
T41	1546116	0	0	0
T66	1097504	0	0	0
T72	200752	0	0	0
T82	978492	0	0	0
T141	1219056	0	0	0
T169	183968	1814	0	0
T172	0	1811	0	0
T178	135294	0	0	0
T197	302130	0	0	0
T228	462966	0	0	0
T273	0	1818	0	0
T275	323056	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774733122	755740786	0	0
T1	129774	129672	0	0
T2	457156	457054	0	0
T3	676138	675922	0	0
T30	829742	829398	0	0
T31	457414	457188	0	0
T60	214968	214858	0	0
T64	1041536	1041516	0	0
T65	323772	323656	0	0
T89	559824	559708	0	0
T90	532378	532276	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774733122	755740786	0	0
T1	129774	129672	0	0
T2	457156	457054	0	0
T3	676138	675922	0	0
T30	829742	829398	0	0
T31	457414	457188	0	0
T60	214968	214858	0	0
T64	1041536	1041516	0	0
T65	323772	323656	0	0
T89	559824	559708	0	0
T90	532378	532276	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774733122	5443	0	0
T41	1546116	0	0	0
T66	1097504	0	0	0
T72	200752	0	0	0
T82	978492	0	0	0
T141	1219056	0	0	0
T169	183968	1814	0	0
T172	0	1811	0	0
T178	135294	0	0	0
T197	302130	0	0	0
T228	462966	0	0	0
T273	0	1818	0	0
T275	323056	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774733122	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774733122	5443	0	0
T41	1546116	0	0	0
T66	1097504	0	0	0
T72	200752	0	0	0
T82	978492	0	0	0
T141	1219056	0	0	0
T169	183968	1814	0	0
T172	0	1811	0	0
T178	135294	0	0	0
T197	302130	0	0	0
T228	462966	0	0	0
T273	0	1818	0	0
T275	323056	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774733122	5443	0	0
T41	1546116	0	0	0
T66	1097504	0	0	0
T72	200752	0	0	0
T82	978492	0	0	0
T141	1219056	0	0	0
T169	183968	1814	0	0
T172	0	1811	0	0
T178	135294	0	0	0
T197	302130	0	0	0
T228	462966	0	0	0
T273	0	1818	0	0
T275	323056	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774733122	5443	0	0
T41	1546116	0	0	0
T66	1097504	0	0	0
T72	200752	0	0	0
T82	978492	0	0	0
T141	1219056	0	0	0
T169	183968	1814	0	0
T172	0	1811	0	0
T178	135294	0	0	0
T197	302130	0	0	0
T228	462966	0	0	0
T273	0	1818	0	0
T275	323056	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774733122	5443	0	0
T41	1546116	0	0	0
T66	1097504	0	0	0
T72	200752	0	0	0
T82	978492	0	0	0
T141	1219056	0	0	0
T169	183968	1814	0	0
T172	0	1811	0	0
T178	135294	0	0	0
T197	302130	0	0	0
T228	462966	0	0	0
T273	0	1818	0	0
T275	323056	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774733122	755740786	0	0
T1	129774	129672	0	0
T2	457156	457054	0	0
T3	676138	675922	0	0
T30	829742	829398	0	0
T31	457414	457188	0	0
T60	214968	214858	0	0
T64	1041536	1041516	0	0
T65	323772	323656	0	0
T89	559824	559708	0	0
T90	532378	532276	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774733122	5443	0	0
T41	1546116	0	0	0
T66	1097504	0	0	0
T72	200752	0	0	0
T82	978492	0	0	0
T141	1219056	0	0	0
T169	183968	1814	0	0
T172	0	1811	0	0
T178	135294	0	0	0
T197	302130	0	0	0
T228	462966	0	0	0
T273	0	1818	0	0
T275	323056	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T169,T49,T172
0	1	Covered	T169,T172,T273
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T169,T172,T273
1	Covered	T169,T49,T172

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T169,T172,T273
1	Covered	T169,T49,T172

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T169,T172,T273
1	1	Covered	T169,T172,T273

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T169,T49,T172
1	0	Covered	T169,T172,T273
1	1	Covered	T169,T172,T273

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T169,T172,T273

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T169,T49,T172
0	Covered	T169,T172,T273

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T169,T49,T172
0	Covered	T169,T172,T273

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	387366561	377870393	0	0
CheckNGreaterZero_A	902	902	0	0
GntImpliesReady_A	387366561	4405	0	0
GntImpliesValid_A	387366561	4405	0	0
GrantKnown_A	387366561	377870393	0	0
IdxKnown_A	387366561	377870393	0	0
IndexIsCorrect_A	387366561	4405	0	0
NoReadyValidNoGrant_A	387366561	0	0	0
Priority_A	387366561	4405	0	0
ReadyAndValidImplyGrant_A	387366561	4405	0	0
ReqAndReadyImplyGrant_A	387366561	4405	0	0
ReqImpliesValid_A	387366561	4405	0	0
ValidKnown_A	387366561	377870393	0	0
gen_data_port_assertion.DataFlow_A	387366561	4405	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387366561	377870393	0	0
T1	64887	64836	0	0
T2	228578	228527	0	0
T3	338069	337961	0	0
T30	414871	414699	0	0
T31	228707	228594	0	0
T60	107484	107429	0	0
T64	520768	520758	0	0
T65	161886	161828	0	0
T89	279912	279854	0	0
T90	266189	266138	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	902	902	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T60	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T89	1	1	0	0
T90	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387366561	4405	0	0
T41	773058	0	0	0
T66	548752	0	0	0
T72	100376	0	0	0
T82	489246	0	0	0
T141	609528	0	0	0
T169	91984	1468	0	0
T172	0	1465	0	0
T178	67647	0	0	0
T197	151065	0	0	0
T228	231483	0	0	0
T273	0	1472	0	0
T275	161528	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387366561	4405	0	0
T41	773058	0	0	0
T66	548752	0	0	0
T72	100376	0	0	0
T82	489246	0	0	0
T141	609528	0	0	0
T169	91984	1468	0	0
T172	0	1465	0	0
T178	67647	0	0	0
T197	151065	0	0	0
T228	231483	0	0	0
T273	0	1472	0	0
T275	161528	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387366561	377870393	0	0
T1	64887	64836	0	0
T2	228578	228527	0	0
T3	338069	337961	0	0
T30	414871	414699	0	0
T31	228707	228594	0	0
T60	107484	107429	0	0
T64	520768	520758	0	0
T65	161886	161828	0	0
T89	279912	279854	0	0
T90	266189	266138	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387366561	377870393	0	0
T1	64887	64836	0	0
T2	228578	228527	0	0
T3	338069	337961	0	0
T30	414871	414699	0	0
T31	228707	228594	0	0
T60	107484	107429	0	0
T64	520768	520758	0	0
T65	161886	161828	0	0
T89	279912	279854	0	0
T90	266189	266138	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387366561	4405	0	0
T41	773058	0	0	0
T66	548752	0	0	0
T72	100376	0	0	0
T82	489246	0	0	0
T141	609528	0	0	0
T169	91984	1468	0	0
T172	0	1465	0	0
T178	67647	0	0	0
T197	151065	0	0	0
T228	231483	0	0	0
T273	0	1472	0	0
T275	161528	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387366561	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387366561	4405	0	0
T41	773058	0	0	0
T66	548752	0	0	0
T72	100376	0	0	0
T82	489246	0	0	0
T141	609528	0	0	0
T169	91984	1468	0	0
T172	0	1465	0	0
T178	67647	0	0	0
T197	151065	0	0	0
T228	231483	0	0	0
T273	0	1472	0	0
T275	161528	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387366561	4405	0	0
T41	773058	0	0	0
T66	548752	0	0	0
T72	100376	0	0	0
T82	489246	0	0	0
T141	609528	0	0	0
T169	91984	1468	0	0
T172	0	1465	0	0
T178	67647	0	0	0
T197	151065	0	0	0
T228	231483	0	0	0
T273	0	1472	0	0
T275	161528	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387366561	4405	0	0
T41	773058	0	0	0
T66	548752	0	0	0
T72	100376	0	0	0
T82	489246	0	0	0
T141	609528	0	0	0
T169	91984	1468	0	0
T172	0	1465	0	0
T178	67647	0	0	0
T197	151065	0	0	0
T228	231483	0	0	0
T273	0	1472	0	0
T275	161528	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387366561	4405	0	0
T41	773058	0	0	0
T66	548752	0	0	0
T72	100376	0	0	0
T82	489246	0	0	0
T141	609528	0	0	0
T169	91984	1468	0	0
T172	0	1465	0	0
T178	67647	0	0	0
T197	151065	0	0	0
T228	231483	0	0	0
T273	0	1472	0	0
T275	161528	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387366561	377870393	0	0
T1	64887	64836	0	0
T2	228578	228527	0	0
T3	338069	337961	0	0
T30	414871	414699	0	0
T31	228707	228594	0	0
T60	107484	107429	0	0
T64	520768	520758	0	0
T65	161886	161828	0	0
T89	279912	279854	0	0
T90	266189	266138	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387366561	4405	0	0
T41	773058	0	0	0
T66	548752	0	0	0
T72	100376	0	0	0
T82	489246	0	0	0
T141	609528	0	0	0
T169	91984	1468	0	0
T172	0	1465	0	0
T178	67647	0	0	0
T197	151065	0	0	0
T228	231483	0	0	0
T273	0	1472	0	0
T275	161528	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T169,T49,T172
0	1	Covered	T169,T172,T52
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T169,T172,T273
1	Covered	T169,T49,T172

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T169,T172,T273
1	Covered	T169,T49,T172

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T169,T172,T52
1	1	Covered	T169,T172,T273

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T169,T49,T172
1	0	Covered	T169,T172,T273
1	1	Covered	T169,T172,T52

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T169,T172,T52

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T169,T49,T172
0	Covered	T169,T172,T273

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T169,T49,T172
0	Covered	T169,T172,T273

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	387366561	377870393	0	0
CheckNGreaterZero_A	902	902	0	0
GntImpliesReady_A	387366561	1038	0	0
GntImpliesValid_A	387366561	1038	0	0
GrantKnown_A	387366561	377870393	0	0
IdxKnown_A	387366561	377870393	0	0
IndexIsCorrect_A	387366561	1038	0	0
NoReadyValidNoGrant_A	387366561	0	0	0
Priority_A	387366561	1038	0	0
ReadyAndValidImplyGrant_A	387366561	1038	0	0
ReqAndReadyImplyGrant_A	387366561	1038	0	0
ReqImpliesValid_A	387366561	1038	0	0
ValidKnown_A	387366561	377870393	0	0
gen_data_port_assertion.DataFlow_A	387366561	1038	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387366561	377870393	0	0
T1	64887	64836	0	0
T2	228578	228527	0	0
T3	338069	337961	0	0
T30	414871	414699	0	0
T31	228707	228594	0	0
T60	107484	107429	0	0
T64	520768	520758	0	0
T65	161886	161828	0	0
T89	279912	279854	0	0
T90	266189	266138	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	902	902	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T60	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T89	1	1	0	0
T90	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387366561	1038	0	0
T41	773058	0	0	0
T66	548752	0	0	0
T72	100376	0	0	0
T82	489246	0	0	0
T141	609528	0	0	0
T169	91984	346	0	0
T172	0	346	0	0
T178	67647	0	0	0
T197	151065	0	0	0
T228	231483	0	0	0
T273	0	346	0	0
T275	161528	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387366561	1038	0	0
T41	773058	0	0	0
T66	548752	0	0	0
T72	100376	0	0	0
T82	489246	0	0	0
T141	609528	0	0	0
T169	91984	346	0	0
T172	0	346	0	0
T178	67647	0	0	0
T197	151065	0	0	0
T228	231483	0	0	0
T273	0	346	0	0
T275	161528	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387366561	377870393	0	0
T1	64887	64836	0	0
T2	228578	228527	0	0
T3	338069	337961	0	0
T30	414871	414699	0	0
T31	228707	228594	0	0
T60	107484	107429	0	0
T64	520768	520758	0	0
T65	161886	161828	0	0
T89	279912	279854	0	0
T90	266189	266138	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387366561	377870393	0	0
T1	64887	64836	0	0
T2	228578	228527	0	0
T3	338069	337961	0	0
T30	414871	414699	0	0
T31	228707	228594	0	0
T60	107484	107429	0	0
T64	520768	520758	0	0
T65	161886	161828	0	0
T89	279912	279854	0	0
T90	266189	266138	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387366561	1038	0	0
T41	773058	0	0	0
T66	548752	0	0	0
T72	100376	0	0	0
T82	489246	0	0	0
T141	609528	0	0	0
T169	91984	346	0	0
T172	0	346	0	0
T178	67647	0	0	0
T197	151065	0	0	0
T228	231483	0	0	0
T273	0	346	0	0
T275	161528	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387366561	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387366561	1038	0	0
T41	773058	0	0	0
T66	548752	0	0	0
T72	100376	0	0	0
T82	489246	0	0	0
T141	609528	0	0	0
T169	91984	346	0	0
T172	0	346	0	0
T178	67647	0	0	0
T197	151065	0	0	0
T228	231483	0	0	0
T273	0	346	0	0
T275	161528	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387366561	1038	0	0
T41	773058	0	0	0
T66	548752	0	0	0
T72	100376	0	0	0
T82	489246	0	0	0
T141	609528	0	0	0
T169	91984	346	0	0
T172	0	346	0	0
T178	67647	0	0	0
T197	151065	0	0	0
T228	231483	0	0	0
T273	0	346	0	0
T275	161528	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387366561	1038	0	0
T41	773058	0	0	0
T66	548752	0	0	0
T72	100376	0	0	0
T82	489246	0	0	0
T141	609528	0	0	0
T169	91984	346	0	0
T172	0	346	0	0
T178	67647	0	0	0
T197	151065	0	0	0
T228	231483	0	0	0
T273	0	346	0	0
T275	161528	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387366561	1038	0	0
T41	773058	0	0	0
T66	548752	0	0	0
T72	100376	0	0	0
T82	489246	0	0	0
T141	609528	0	0	0
T169	91984	346	0	0
T172	0	346	0	0
T178	67647	0	0	0
T197	151065	0	0	0
T228	231483	0	0	0
T273	0	346	0	0
T275	161528	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387366561	377870393	0	0
T1	64887	64836	0	0
T2	228578	228527	0	0
T3	338069	337961	0	0
T30	414871	414699	0	0
T31	228707	228594	0	0
T60	107484	107429	0	0
T64	520768	520758	0	0
T65	161886	161828	0	0
T89	279912	279854	0	0
T90	266189	266138	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387366561	1038	0	0
T41	773058	0	0	0
T66	548752	0	0	0
T72	100376	0	0	0
T82	489246	0	0	0
T141	609528	0	0	0
T169	91984	346	0	0
T172	0	346	0	0
T178	67647	0	0	0
T197	151065	0	0	0
T228	231483	0	0	0
T273	0	346	0	0
T275	161528	0	0	0