SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.83 | 99.34 | 100.00 | 100.00 | 100.00 | u_pinmux_strap_sampling |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 902 | 902 | 0 | 0 |
OutputsKnown_A | 97461789 | 96845723 | 0 | 0 |
gen_no_flops.OutputDelay_A | 97461789 | 96845723 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 902 | 902 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
T60 | 1 | 1 | 0 | 0 |
T64 | 1 | 1 | 0 | 0 |
T65 | 1 | 1 | 0 | 0 |
T89 | 1 | 1 | 0 | 0 |
T90 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 97461789 | 96845723 | 0 | 0 |
T1 | 19361 | 18734 | 0 | 0 |
T2 | 56109 | 55231 | 0 | 0 |
T3 | 83127 | 82546 | 0 | 0 |
T30 | 101195 | 100696 | 0 | 0 |
T31 | 56100 | 55630 | 0 | 0 |
T60 | 26542 | 26165 | 0 | 0 |
T64 | 125234 | 125171 | 0 | 0 |
T65 | 43755 | 43463 | 0 | 0 |
T89 | 68045 | 67550 | 0 | 0 |
T90 | 64621 | 64258 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 97461789 | 96845723 | 0 | 0 |
T1 | 19361 | 18734 | 0 | 0 |
T2 | 56109 | 55231 | 0 | 0 |
T3 | 83127 | 82546 | 0 | 0 |
T30 | 101195 | 100696 | 0 | 0 |
T31 | 56100 | 55630 | 0 | 0 |
T60 | 26542 | 26165 | 0 | 0 |
T64 | 125234 | 125171 | 0 | 0 |
T65 | 43755 | 43463 | 0 | 0 |
T89 | 68045 | 67550 | 0 | 0 |
T90 | 64621 | 64258 | 0 | 0 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 902 | 902 | 0 | 0 |
OutputsKnown_A | 97461789 | 96845723 | 0 | 0 |
gen_no_flops.OutputDelay_A | 97461789 | 96845723 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 902 | 902 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
T60 | 1 | 1 | 0 | 0 |
T64 | 1 | 1 | 0 | 0 |
T65 | 1 | 1 | 0 | 0 |
T89 | 1 | 1 | 0 | 0 |
T90 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 97461789 | 96845723 | 0 | 0 |
T1 | 19361 | 18734 | 0 | 0 |
T2 | 56109 | 55231 | 0 | 0 |
T3 | 83127 | 82546 | 0 | 0 |
T30 | 101195 | 100696 | 0 | 0 |
T31 | 56100 | 55630 | 0 | 0 |
T60 | 26542 | 26165 | 0 | 0 |
T64 | 125234 | 125171 | 0 | 0 |
T65 | 43755 | 43463 | 0 | 0 |
T89 | 68045 | 67550 | 0 | 0 |
T90 | 64621 | 64258 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 97461789 | 96845723 | 0 | 0 |
T1 | 19361 | 18734 | 0 | 0 |
T2 | 56109 | 55231 | 0 | 0 |
T3 | 83127 | 82546 | 0 | 0 |
T30 | 101195 | 100696 | 0 | 0 |
T31 | 56100 | 55630 | 0 | 0 |
T60 | 26542 | 26165 | 0 | 0 |
T64 | 125234 | 125171 | 0 | 0 |
T65 | 43755 | 43463 | 0 | 0 |
T89 | 68045 | 67550 | 0 | 0 |
T90 | 64621 | 64258 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |