Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : edn
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.42 99.42

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_edn1 99.30 99.30
tb.dut.top_earlgrey.u_edn0 99.34 99.34


Module Instance : tb.dut.top_earlgrey.u_edn1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.30 99.30


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.30 99.30


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.46 92.83 93.54 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_edn0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.34 99.34


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.34 99.34


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.46 92.83 93.54 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : edn
TotalCoveredPercent
Totals 78 74 94.87
Total Bits 1208 1201 99.42
Total Bits 0->1 604 602 99.67
Total Bits 1->0 604 599 99.17

Ports 78 74 94.87
Port Bits 1208 1201 99.42
Port Bits 0->1 604 602 99.67
Port Bits 1->0 604 599 99.17

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T64,T30 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T126,T106,T110 Yes T126,T106,T110 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T126,T106,T110 Yes T126,T106,T110 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[6:0] Yes Yes *T76,*T77,*T78 Yes T76,T77,T78 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20:16] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T76,*T77,*T78 Yes T76,T77,T78 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T76,T77,T78 Yes T76,T77,T78 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T76,T77,T78 Yes T76,T77,T78 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T76,T77,T78 Yes T76,T77,T78 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T126,T106,T110 Yes T126,T106,T110 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T3,T64,T30 Yes T1,T2,T3 OUTPUT
tl_o.d_data[31:0] Yes Yes T3,T64,T30 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Yes Yes T76,T77,T78 Yes T76,T77,T78 OUTPUT
tl_o.d_source[5:0] Yes Yes *T76,*T77,*T78 Yes T76,T77,T78 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T76,T77,T78 Yes T76,T77,T78 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T126,*T106,*T110 Yes T126,T106,T110 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_i[0].edn_req Yes Yes T30,T126,T148 Yes T30,T126,T148 INPUT
edn_i[1].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[2].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[3].edn_req Yes Yes T223,T224,T384 Yes T223,T224,T384 INPUT
edn_i[4].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[5].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[6].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[7].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T30,T126,T148 Yes T30,T126,T148 OUTPUT
edn_o[0].edn_fips Yes Yes T126,T127,T357 Yes T126,T110,T127 OUTPUT
edn_o[0].edn_ack Yes Yes T30,T126,T148 Yes T30,T126,T148 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[1].edn_fips No No Yes T110,T115,T146 OUTPUT
edn_o[1].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T1,T30,T31 Yes T1,T89,T30 OUTPUT
edn_o[2].edn_fips Yes Yes T106,T113,T114 Yes T106,T115,T113 OUTPUT
edn_o[2].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T223,T224,T384 Yes T223,T224,T384 OUTPUT
edn_o[3].edn_fips No No Yes T223,T224,T384 OUTPUT
edn_o[3].edn_ack Yes Yes T223,T224,T384 Yes T223,T224,T384 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T64,T30,T31 Yes T2,T60,T89 OUTPUT
edn_o[4].edn_fips No No Yes T639,T640,T641 OUTPUT
edn_o[4].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[5].edn_fips Yes Yes T357,T358 Yes T357,T223,T224 OUTPUT
edn_o[5].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[6].edn_fips Yes Yes T126,T127,T357 Yes T126,T110,T127 OUTPUT
edn_o[6].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[7].edn_bus[31:0] Yes Yes T3,T64,T30 Yes T1,T3,T64 OUTPUT
edn_o[7].edn_fips Yes Yes T126,T106,T127 Yes T126,T106,T127 OUTPUT
edn_o[7].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T3,T64,T30 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.genbits_fips Yes Yes T126,T106,T113 Yes T126,T106,T110 INPUT
csrng_cmd_i.genbits_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_rsp_sts[1:0] No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T127,T642,T357 Yes T127,T642,T357 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T64,T82,T61 Yes T64,T82,T61 INPUT
alert_rx_i[0].ping_n Yes Yes T64,T82,T85 Yes T64,T82,T85 INPUT
alert_rx_i[0].ping_p Yes Yes T64,T82,T85 Yes T64,T82,T85 INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T68,T643,T82 Yes T68,T643,T82 INPUT
alert_rx_i[1].ping_n Yes Yes T82,T85,T87 Yes T82,T85,T87 INPUT
alert_rx_i[1].ping_p Yes Yes T82,T85,T87 Yes T82,T85,T87 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T64,T82,T61 Yes T64,T82,T61 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T68,T643,T82 Yes T68,T643,T82 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T298,T288,T299 Yes T298,T288,T299 OUTPUT
intr_edn_fatal_err_o Yes Yes T288,T290,T297 Yes T288,T290,T297 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn1
TotalCoveredPercent
Totals 50 48 96.00
Total Bits 712 707 99.30
Total Bits 0->1 356 354 99.44
Total Bits 1->0 356 353 99.16

Ports 50 48 96.00
Port Bits 712 707 99.30
Port Bits 0->1 356 354 99.44
Port Bits 1->0 356 353 99.16

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T64,T30 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T3,T64,T30 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T126,T106,T110 Yes T126,T106,T110 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T126,T106,T110 Yes T126,T106,T110 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T126,T106,T110 Yes T126,T106,T110 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T126,T106,T110 Yes T126,T106,T110 INPUT
tl_i.a_mask[3:0] Yes Yes T126,T106,T110 Yes T126,T106,T110 INPUT
tl_i.a_address[6:0] Yes Yes *T76,*T77,*T78 Yes T76,T77,T78 INPUT
tl_i.a_address[18:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20:19] Yes Yes T126,T106,T110 Yes T126,T106,T110 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T126,*T106,*T110 Yes T126,T106,T110 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T126,*T106,*T110 Yes T126,T106,T110 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T76,*T77,*T78 Yes T76,T77,T78 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T76,T77,T78 Yes T76,T77,T78 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T76,T77,T78 Yes T76,T77,T78 INPUT
tl_i.a_valid Yes Yes T126,T106,T110 Yes T126,T106,T110 INPUT
tl_o.a_ready Yes Yes T126,T106,T110 Yes T126,T106,T110 OUTPUT
tl_o.d_error Yes Yes T76,T77,T78 Yes T76,T77,T78 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T126,T106,T110 Yes T126,T106,T110 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T126,T106,T110 Yes T126,T106,T110 OUTPUT
tl_o.d_data[31:0] Yes Yes T126,T106,T110 Yes T126,T106,T110 OUTPUT
tl_o.d_sink Yes Yes T76,T77,T78 Yes T76,T77,T78 OUTPUT
tl_o.d_source[5:0] Yes Yes *T76,*T77,*T78 Yes T76,T77,T78 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T76,T77,T78 Yes T76,T77,T78 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T126,*T106,*T110 Yes T126,T106,T110 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T126,T106,T110 Yes T126,T106,T110 OUTPUT
edn_i[0].edn_req Yes Yes T126,T110,T127 Yes T126,T110,T127 INPUT
edn_i[1].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[2].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[3].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[4].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[5].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[6].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[7].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_o[0].edn_bus[31:0] Yes Yes T126,T110,T127 Yes T126,T110,T127 OUTPUT
edn_o[0].edn_fips Yes Yes T126,T127,T357 Yes T126,T110,T127 OUTPUT
edn_o[0].edn_ack Yes Yes T126,T110,T127 Yes T126,T110,T127 OUTPUT
edn_o[1].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[1].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[1].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
csrng_cmd_o.genbits_ready Yes Yes T126,T106,T110 Yes T126,T106,T110 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T126,T106,T110 Yes T126,T106,T110 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T126,T106,T110 Yes T126,T106,T110 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T126,T110,T127 Yes T126,T110,T127 INPUT
csrng_cmd_i.genbits_fips No No Yes T126,T644,T645 INPUT
csrng_cmd_i.genbits_valid Yes Yes T126,T106,T110 Yes T126,T106,T110 INPUT
csrng_cmd_i.csrng_rsp_sts[1:0] No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T126,T106,T110 Yes T126,T106,T110 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T127,T357,T358 Yes T127,T357,T358 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T64,T82,T61 Yes T64,T82,T61 INPUT
alert_rx_i[0].ping_n Yes Yes T64,T82,T85 Yes T64,T82,T85 INPUT
alert_rx_i[0].ping_p Yes Yes T64,T82,T85 Yes T64,T82,T85 INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T68,T82,T61 Yes T68,T82,T61 INPUT
alert_rx_i[1].ping_n Yes Yes T82,T85,T87 Yes T82,T85,T87 INPUT
alert_rx_i[1].ping_p Yes Yes T82,T85,T87 Yes T82,T85,T87 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T64,T82,T61 Yes T64,T82,T61 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T68,T82,T61 Yes T68,T82,T61 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T298,T288,T299 Yes T298,T288,T299 OUTPUT
intr_edn_fatal_err_o Yes Yes T288,T290,T297 Yes T288,T290,T297 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn0
TotalCoveredPercent
Totals 78 73 93.59
Total Bits 1206 1198 99.34
Total Bits 0->1 603 601 99.67
Total Bits 1->0 603 597 99.00

Ports 78 73 93.59
Port Bits 1206 1198 99.34
Port Bits 0->1 603 601 99.67
Port Bits 1->0 603 597 99.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T64,T30 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T126,T106,T110 Yes T126,T106,T110 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T126,T106,T110 Yes T126,T106,T110 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[6:0] Yes Yes *T76,*T77,*T78 Yes T76,T77,T78 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[18:16] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[19] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T76,*T77,*T78 Yes T76,T77,T78 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T76,T77,T78 Yes T76,T77,T78 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T76,T77,T78 Yes T76,T77,T78 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T76,T77,T78 Yes T76,T77,T78 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T126,T106,T110 Yes T126,T106,T110 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T3,T64,T30 Yes T1,T2,T3 OUTPUT
tl_o.d_data[31:0] Yes Yes T3,T64,T30 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Yes Yes T76,T77,T78 Yes T76,T77,T78 OUTPUT
tl_o.d_source[5:0] Yes Yes *T76,*T77,*T78 Yes T76,T77,T78 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T76,T77,T78 Yes T76,T77,T78 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T126,*T106,*T110 Yes T126,T106,T110 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_i[0].edn_req Yes Yes T30,T148,T5 Yes T30,T148,T5 INPUT
edn_i[1].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[2].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[3].edn_req Yes Yes T223,T224,T384 Yes T223,T224,T384 INPUT
edn_i[4].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[5].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[6].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[7].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T30,T148,T5 Yes T30,T148,T5 OUTPUT
edn_o[0].edn_fips No No Yes T211,T223,T224 OUTPUT
edn_o[0].edn_ack Yes Yes T30,T148,T5 Yes T30,T148,T5 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[1].edn_fips No No Yes T110,T115,T146 OUTPUT
edn_o[1].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T1,T30,T31 Yes T1,T89,T30 OUTPUT
edn_o[2].edn_fips Yes Yes T106,T113,T114 Yes T106,T115,T113 OUTPUT
edn_o[2].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T223,T224,T384 Yes T223,T224,T384 OUTPUT
edn_o[3].edn_fips No No Yes T223,T224,T384 OUTPUT
edn_o[3].edn_ack Yes Yes T223,T224,T384 Yes T223,T224,T384 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T64,T30,T31 Yes T2,T60,T89 OUTPUT
edn_o[4].edn_fips No No Yes T639,T640,T641 OUTPUT
edn_o[4].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[5].edn_fips Yes Yes T357,T358 Yes T357,T223,T224 OUTPUT
edn_o[5].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[6].edn_fips Yes Yes T126,T127,T357 Yes T126,T110,T127 OUTPUT
edn_o[6].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[7].edn_bus[31:0] Yes Yes T3,T64,T30 Yes T1,T3,T64 OUTPUT
edn_o[7].edn_fips Yes Yes T126,T106,T127 Yes T126,T106,T127 OUTPUT
edn_o[7].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T3,T64,T30 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.genbits_fips Yes Yes T126,T106,T113 Yes T126,T106,T110 INPUT
csrng_cmd_i.genbits_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_rsp_sts[1:0] No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T127,T642,T357 Yes T127,T642,T357 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T82,T61,T642 Yes T82,T61,T642 INPUT
alert_rx_i[0].ping_n Yes Yes T82,T85,T87 Yes T82,T85,T87 INPUT
alert_rx_i[0].ping_p Yes Yes T82,T85,T87 Yes T82,T85,T87 INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T643,T82,T646 Yes T643,T82,T646 INPUT
alert_rx_i[1].ping_n Yes Yes T82,T85,T87 Yes T82,T85,T87 INPUT
alert_rx_i[1].ping_p Yes Yes T82,T85,T87 Yes T82,T85,T87 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T82,T61,T642 Yes T82,T61,T642 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T643,T82,T646 Yes T643,T82,T646 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T298,T288,T299 Yes T298,T288,T299 OUTPUT
intr_edn_fatal_err_o Yes Yes T288,T290,T297 Yes T288,T290,T297 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%