Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3715091	1			T70	728		T71	19		T72	90
values[2]	745666	1			T71	17		T72	47		T78	118
values[3]	97651	1			T71	17		T151	10		T77	69
values[4]	51986	1			T71	17		T151	20		T77	52
values[5]	35090	1			T71	18		T151	19		T77	24
values[6]	26200	1			T71	17		T151	17		T77	24
values[7]	21425	1			T71	17		T151	9		T77	26
values[8]	18522	1			T71	17		T151	13		T77	31
values[9]	16350	1			T71	17		T151	21		T77	11
values[10]	15596	1			T71	17		T151	22		T77	13
values[11]	14872	1			T71	18		T151	18		T77	13
values[12]	14226	1			T71	17		T151	13		T77	12
values[13]	13696	1			T71	17		T151	16		T77	4
values[14]	12949	1			T71	17		T151	17		T77	5
values[15]	12607	1			T71	17		T151	12		T77	9
values[16]	12203	1			T71	17		T151	21		T77	13
values[17]	11582	1			T71	17		T151	28		T77	26
values[18]	11254	1			T71	18		T151	13		T77	9
values[19]	10458	1			T71	17		T151	7		T77	6
values[20]	10266	1			T71	17		T151	6		T77	4
values[21]	10391	1			T71	17		T151	7		T77	8
values[22]	9760	1			T71	18		T151	4		T77	1
values[23]	9498	1			T71	17		T151	4		T77	6
values[24]	9400	1			T71	17		T151	13		T77	17
values[25]	9193	1			T71	18		T151	16		T77	25
values[26]	8849	1			T71	17		T151	21		T77	19
values[27]	8308	1			T71	17		T151	16		T77	7
values[28]	7666	1			T71	17		T151	16		T77	5
values[29]	7192	1			T71	17		T151	13		T77	3
values[30]	6668	1			T71	17		T151	11		T77	3
values[31]	6060	1			T71	17		T151	14		T77	1
values[32]	5757	1			T71	17		T151	14		T77	2
values[33]	5481	1			T71	17		T151	9		T498	7
values[34]	5200	1			T71	18		T151	5		T498	7
values[35]	4773	1			T71	17		T151	3		T498	7
values[36]	4560	1			T71	17		T151	5		T498	9
values[37]	4192	1			T71	18		T151	4		T498	7
values[38]	3895	1			T71	18		T151	2		T498	7
values[39]	3641	1			T71	17		T151	6		T498	8
values[40]	3648	1			T71	18		T151	4		T498	7
values[41]	3513	1			T71	18		T151	3		T498	7
values[42]	3479	1			T71	17		T151	3		T498	7
values[43]	3282	1			T71	18		T151	3		T498	7
values[44]	3182	1			T71	17		T151	8		T498	8
values[45]	3189	1			T71	18		T151	6		T498	7
values[46]	3125	1			T71	18		T151	3		T498	7
values[47]	3020	1			T71	17		T151	2		T498	7
values[48]	3030	1			T71	17		T151	1		T498	7
values[49]	2854	1			T71	18		T151	1		T498	7
values[50]	2873	1			T71	19		T151	1		T498	7
values[51]	2785	1			T71	17		T151	2		T498	7
values[52]	2789	1			T71	17		T151	2		T498	7
values[53]	2742	1			T71	17		T151	1		T498	7
values[54]	2656	1			T71	17		T151	3		T498	7
values[55]	2591	1			T71	18		T151	3		T498	7
values[56]	2557	1			T71	17		T498	8		T389	11
values[57]	2487	1			T71	17		T498	7		T389	11
values[58]	2469	1			T71	17		T498	7		T389	11
values[59]	2406	1			T71	18		T498	7		T389	11
values[60]	2411	1			T71	17		T498	7		T389	11
values[61]	2573	1			T71	17		T498	8		T389	11
values[62]	3948	1			T71	17		T498	7		T389	11
values[63]	15628	1			T71	159		T498	70		T389	156
values[64]	222164	1			T71	2929		T498	1165		T389	1972

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4773389	1			T70	710		T71	2980		T72	87
values[2]	782541	1			T71	866		T72	10		T78	93
values[3]	72020	1			T71	244		T78	1		T151	3
values[4]	13069	1			T71	77		T151	1		T77	5
values[5]	5164	1			T71	23		T498	14		T389	22
values[6]	2910	1			T71	6		T498	6		T389	6
values[7]	2177	1			T71	2		T498	1		T389	1
values[8]	1771	1			T498	1		T386	2		T503	3
values[9]	1605	1			T498	1		T386	1		T503	6
values[10]	1490	1			T498	1		T386	2		T503	5
values[11]	1356	1			T498	1		T386	4		T503	7
values[12]	1207	1			T498	1		T386	5		T503	3
values[13]	1156	1			T498	1		T386	3		T503	3
values[14]	1036	1			T498	1		T386	1		T503	2
values[15]	925	1			T498	1		T386	1		T503	2
values[16]	957	1			T498	1		T386	6		T503	2
values[17]	947	1			T498	1		T386	4		T503	2
values[18]	873	1			T498	1		T386	1		T503	2
values[19]	783	1			T498	1		T386	4		T503	1
values[20]	715	1			T498	1		T386	1		T510	2
values[21]	743	1			T498	1		T386	2		T510	2
values[22]	734	1			T498	1		T386	2		T510	2
values[23]	684	1			T498	1		T386	2		T510	2
values[24]	644	1			T498	1		T386	4		T510	2
values[25]	619	1			T498	1		T386	3		T510	2
values[26]	653	1			T498	1		T386	2		T510	2
values[27]	620	1			T498	1		T386	1		T510	2
values[28]	557	1			T498	1		T386	2		T510	2
values[29]	540	1			T498	1		T386	11		T510	1
values[30]	539	1			T498	1		T386	1		T510	1
values[31]	547	1			T498	1		T386	2		T510	2
values[32]	509	1			T498	1		T386	1		T510	3
values[33]	451	1			T498	1		T386	2		T510	2
values[34]	432	1			T498	1		T386	1		T510	2
values[35]	400	1			T498	1		T386	1		T510	2
values[36]	392	1			T498	1		T386	1		T510	2
values[37]	406	1			T498	1		T386	1		T510	2
values[38]	396	1			T498	1		T386	2		T510	2
values[39]	454	1			T498	1		T386	5		T510	2
values[40]	463	1			T498	1		T386	1		T510	2
values[41]	458	1			T498	1		T386	2		T510	2
values[42]	406	1			T498	1		T386	6		T510	2
values[43]	401	1			T498	1		T386	4		T510	2
values[44]	408	1			T498	1		T386	2		T510	2
values[45]	389	1			T498	1		T386	3		T510	2
values[46]	414	1			T498	1		T386	2		T510	2
values[47]	401	1			T498	1		T386	1		T510	2
values[48]	409	1			T498	1		T386	1		T510	1
values[49]	370	1			T498	1		T386	1		T510	1
values[50]	387	1			T498	1		T386	1		T510	2
values[51]	375	1			T498	1		T386	4		T510	2
values[52]	355	1			T498	1		T386	4		T510	2
values[53]	365	1			T498	1		T386	6		T510	2
values[54]	373	1			T498	1		T386	2		T510	2
values[55]	372	1			T498	1		T386	2		T510	2
values[56]	355	1			T498	1		T386	2		T510	2
values[57]	366	1			T498	1		T386	2		T510	2
values[58]	342	1			T498	1		T386	1		T510	2
values[59]	375	1			T498	1		T386	1		T510	3
values[60]	365	1			T498	1		T386	1		T510	2
values[61]	393	1			T498	1		T386	2		T510	2
values[62]	646	1			T498	1		T386	7		T510	2
values[63]	3474	1			T498	17		T386	31		T510	2
values[64]	27102	1			T498	152		T386	32		T510	1

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	597800	1			T70	677		T71	17		T72	2
values[2]	2677260	1			T71	17		T72	79		T78	359
values[3]	1113454	1			T71	17		T72	34		T78	89
values[4]	136959	1			T71	17		T72	1		T78	1
values[5]	70849	1			T71	17		T151	11		T77	12
values[6]	46400	1			T71	17		T151	12		T77	4
values[7]	34187	1			T71	17		T151	14		T77	4
values[8]	27705	1			T71	17		T151	17		T77	5
values[9]	23564	1			T71	17		T151	23		T77	10
values[10]	20703	1			T71	17		T151	11		T77	17
values[11]	18853	1			T71	17		T151	10		T77	10
values[12]	17221	1			T71	17		T151	17		T77	16
values[13]	16238	1			T71	17		T151	13		T77	21
values[14]	15462	1			T71	17		T151	11		T77	3
values[15]	14564	1			T71	18		T151	10		T77	6
values[16]	14069	1			T71	17		T151	16		T77	5
values[17]	13627	1			T71	17		T151	25		T77	5
values[18]	12943	1			T71	17		T151	11		T77	5
values[19]	12442	1			T71	17		T151	17		T77	2
values[20]	12556	1			T71	17		T151	22		T77	9
values[21]	12080	1			T71	17		T151	12		T77	18
values[22]	11315	1			T71	17		T151	7		T77	10
values[23]	10786	1			T71	17		T151	8		T77	10
values[24]	10561	1			T71	17		T151	15		T77	1
values[25]	10170	1			T71	17		T151	13		T77	2
values[26]	9562	1			T71	17		T151	14		T77	3
values[27]	9074	1			T71	17		T151	25		T77	3
values[28]	8466	1			T71	17		T151	11		T77	2
values[29]	7933	1			T71	17		T151	6		T77	8
values[30]	7423	1			T71	17		T151	4		T77	7
values[31]	6824	1			T71	17		T151	8		T77	3
values[32]	6184	1			T71	17		T151	8		T77	4
values[33]	5795	1			T71	17		T151	5		T77	2
values[34]	5298	1			T71	17		T151	13		T77	2
values[35]	4929	1			T71	18		T151	6		T77	15
values[36]	4573	1			T71	17		T151	7		T77	15
values[37]	4353	1			T71	17		T151	3		T77	6
values[38]	4066	1			T71	17		T151	2		T77	5
values[39]	3835	1			T71	18		T77	2		T498	7
values[40]	3626	1			T71	17		T77	1		T498	7
values[41]	3576	1			T71	17		T77	1		T498	7
values[42]	3512	1			T71	18		T77	2		T498	7
values[43]	3608	1			T71	18		T77	1		T498	8
values[44]	3386	1			T71	17		T77	2		T498	7
values[45]	3444	1			T71	18		T77	1		T498	7
values[46]	3357	1			T71	17		T77	11		T498	7
values[47]	3191	1			T71	17		T77	1		T498	7
values[48]	3088	1			T71	17		T77	1		T498	7
values[49]	3029	1			T71	17		T498	7		T389	11
values[50]	3014	1			T71	17		T498	7		T389	11
values[51]	3060	1			T71	17		T498	7		T389	11
values[52]	2895	1			T71	18		T498	7		T389	11
values[53]	2849	1			T71	18		T498	7		T389	11
values[54]	2829	1			T71	17		T498	7		T389	12
values[55]	2766	1			T71	17		T498	8		T389	11
values[56]	2685	1			T71	17		T498	8		T389	11
values[57]	2549	1			T71	17		T498	7		T389	12
values[58]	2642	1			T71	17		T498	7		T389	11
values[59]	2554	1			T71	17		T498	7		T389	12
values[60]	2545	1			T71	17		T498	7		T389	11
values[61]	2776	1			T71	17		T498	7		T389	11
values[62]	3822	1			T71	17		T498	7		T389	11
values[63]	17548	1			T71	18		T498	8		T389	202
values[64]	212664	1			T71	3079		T498	1286		T389	1748