Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2061318	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

23435521

1

T1

40722

T2

4300

T3

3658

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	16530090	1			T1	37070		T2	1303		T3	986
values[0x0]	7489416	1			T1	3652		T2	2997		T3	2672
values[0x1]	1477333	1			T1	106		T2	171		T3	147

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	705091	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

24791748

1

T1

40828

T2

4471

T3

3805

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11463657	1			T1	20414		T2	2236		T3	1903
valid_sources[0x01]	11463754	1			T1	20414		T2	2235		T3	1902
valid_sources[0x02]	41485	1			T49	1		T496	44		T344	546
valid_sources[0x03]	40581	1			T73	1		T496	21		T344	542
valid_sources[0x04]	43835	1			T74	1		T420	1		T496	54
valid_sources[0x05]	41366	1			T49	1		T496	48		T344	549
valid_sources[0x06]	41020	1			T74	1		T496	33		T344	504
valid_sources[0x07]	40513	1			T420	1		T242	1		T496	33
valid_sources[0x08]	41656	1			T74	1		T242	2		T49	1
valid_sources[0x09]	41213	1			T496	52		T344	570		T340	3137
valid_sources[0x0a]	41175	1			T73	2		T74	2		T420	1
valid_sources[0x0b]	41688	1			T74	1		T49	1		T496	32
valid_sources[0x0c]	42595	1			T420	1		T496	31		T344	534
valid_sources[0x0d]	40818	1			T73	3		T242	2		T49	2
valid_sources[0x0e]	41131	1			T74	1		T242	1		T496	41
valid_sources[0x0f]	40685	1			T496	26		T344	513		T340	3256
valid_sources[0x10]	40266	1			T73	2		T74	2		T420	1
valid_sources[0x11]	40173	1			T74	1		T49	3		T496	44
valid_sources[0x12]	40893	1			T496	30		T344	514		T340	3219
valid_sources[0x13]	41436	1			T420	1		T496	54		T344	497
valid_sources[0x14]	42040	1			T74	1		T420	2		T242	1
valid_sources[0x15]	42080	1			T73	1		T242	2		T49	1
valid_sources[0x16]	42020	1			T74	3		T242	1		T496	21
valid_sources[0x17]	41566	1			T49	2		T496	40		T344	526
valid_sources[0x18]	41082	1			T74	1		T49	1		T496	74
valid_sources[0x19]	41075	1			T74	1		T242	1		T49	1
valid_sources[0x1a]	41301	1			T420	1		T49	1		T496	37
valid_sources[0x1b]	42027	1			T74	2		T420	1		T242	1
valid_sources[0x1c]	41046	1			T73	1		T242	1		T496	53
valid_sources[0x1d]	42334	1			T242	1		T49	1		T496	23
valid_sources[0x1e]	41703	1			T73	1		T420	1		T49	1
valid_sources[0x1f]	40949	1			T242	1		T496	39		T344	549
valid_sources[0x20]	41614	1			T74	2		T496	33		T344	516

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

15724865

1

T1

37070

T2

1303

T3

986

values[0x0]

all_enables

biggest_size

7447013

1

T1

3652

T2

2997

T3

2672

values[0x1]

all_enables

biggest_size

263643

1

T73

17

T74

20

T75

13

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2835287	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

447388

1

T70

110

T71

550

T72

29

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1113408	1			T70	234		T71	1384		T72	43
values[0x0]	1059078	1			T70	250		T71	1369		T72	51
values[0x1]	1110189	1			T70	244		T71	1409		T72	43

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2195380	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1087295

1

T70

245

T71

1369

T72

47

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51394	1			T70	20		T71	63		T72	1
valid_sources[0x01]	50239	1			T71	69		T151	10		T77	79
valid_sources[0x02]	51279	1			T70	18		T71	66		T151	7
valid_sources[0x03]	53240	1			T71	74		T151	5		T76	1
valid_sources[0x04]	51587	1			T70	7		T71	62		T151	6
valid_sources[0x05]	50959	1			T70	20		T71	75		T78	3
valid_sources[0x06]	52071	1			T70	10		T71	76		T78	1
valid_sources[0x07]	50768	1			T70	6		T71	61		T72	3
valid_sources[0x08]	50524	1			T71	66		T151	11		T76	2
valid_sources[0x09]	50613	1			T70	9		T71	61		T72	19
valid_sources[0x0a]	51784	1			T70	15		T71	65		T72	7
valid_sources[0x0b]	51137	1			T70	13		T71	68		T151	14
valid_sources[0x0c]	51650	1			T71	61		T72	1		T151	28
valid_sources[0x0d]	50832	1			T71	71		T151	117		T76	2
valid_sources[0x0e]	52041	1			T70	6		T71	67		T151	12
valid_sources[0x0f]	50460	1			T70	6		T71	63		T72	1
valid_sources[0x10]	51281	1			T71	65		T72	1		T78	3
valid_sources[0x11]	50529	1			T71	74		T151	12		T76	2
valid_sources[0x12]	51893	1			T70	30		T71	56		T72	4
valid_sources[0x13]	51222	1			T70	27		T71	68		T72	6
valid_sources[0x14]	51701	1			T70	12		T71	66		T72	4
valid_sources[0x15]	51289	1			T71	61		T151	4		T76	6
valid_sources[0x16]	50750	1			T71	58		T151	16		T76	3
valid_sources[0x17]	51542	1			T71	52		T151	3		T77	140
valid_sources[0x18]	51465	1			T71	62		T72	2		T151	4
valid_sources[0x19]	51326	1			T71	59		T72	2		T151	5
valid_sources[0x1a]	50140	1			T70	44		T71	58		T78	1
valid_sources[0x1b]	52271	1			T70	19		T71	86		T78	1
valid_sources[0x1c]	51886	1			T70	22		T71	62		T72	29
valid_sources[0x1d]	50863	1			T70	9		T71	80		T72	8
valid_sources[0x1e]	51533	1			T70	27		T71	59		T78	1
valid_sources[0x1f]	51700	1			T70	18		T71	73		T72	2
valid_sources[0x20]	50600	1			T70	15		T71	62		T151	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47192

1

T70

7

T71

49

T72

2

values[0x0]

all_enables

biggest_size

353091

1

T70

84

T71

449

T72

20

values[0x1]

all_enables

biggest_size

47105

1

T70

19

T71

52

T72

7

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3029933	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

493521

1

T70

103

T71

604

T72

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1205177	1			T70	221		T71	1387		T72	33
values[0x0]	1111732	1			T70	238		T71	1395		T72	28
values[0x1]	1206545	1			T70	251		T71	1416		T72	36

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2324265	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1199189

1

T70

246

T71

1389

T72

37

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	55358	1			T70	13		T71	69		T151	6
valid_sources[0x01]	54545	1			T71	93		T151	4		T76	4
valid_sources[0x02]	55083	1			T70	14		T71	65		T72	4
valid_sources[0x03]	55151	1			T71	24		T151	10		T76	4
valid_sources[0x04]	55303	1			T70	14		T71	72		T151	9
valid_sources[0x05]	55358	1			T70	6		T71	82		T78	1
valid_sources[0x06]	55086	1			T70	8		T71	74		T72	2
valid_sources[0x07]	55064	1			T70	17		T71	40		T151	12
valid_sources[0x08]	54503	1			T71	99		T78	2		T151	17
valid_sources[0x09]	54083	1			T70	19		T71	75		T72	1
valid_sources[0x0a]	55725	1			T70	27		T71	65		T151	7
valid_sources[0x0b]	54755	1			T70	11		T71	79		T151	12
valid_sources[0x0c]	54982	1			T71	83		T78	1		T151	10
valid_sources[0x0d]	55011	1			T71	69		T151	12		T76	3
valid_sources[0x0e]	55182	1			T70	7		T71	36		T72	2
valid_sources[0x0f]	54725	1			T70	20		T71	80		T78	1
valid_sources[0x10]	55721	1			T71	72		T72	2		T151	8
valid_sources[0x11]	55031	1			T71	38		T72	6		T151	15
valid_sources[0x12]	55346	1			T70	28		T71	77		T72	6
valid_sources[0x13]	55333	1			T70	26		T71	70		T72	2
valid_sources[0x14]	53981	1			T70	7		T71	46		T72	4
valid_sources[0x15]	55194	1			T71	61		T72	6		T78	1
valid_sources[0x16]	55091	1			T71	58		T72	6		T151	17
valid_sources[0x17]	55070	1			T71	69		T72	2		T78	1
valid_sources[0x18]	54764	1			T71	90		T151	11		T76	3
valid_sources[0x19]	54164	1			T71	68		T151	5		T77	108
valid_sources[0x1a]	53855	1			T70	40		T71	70		T151	15
valid_sources[0x1b]	55338	1			T70	9		T71	54		T72	3
valid_sources[0x1c]	56704	1			T70	25		T71	88		T72	2
valid_sources[0x1d]	54239	1			T70	15		T71	58		T78	1
valid_sources[0x1e]	54420	1			T70	20		T71	56		T72	4
valid_sources[0x1f]	54805	1			T70	14		T71	54		T72	1
valid_sources[0x20]	54981	1			T70	17		T71	78		T72	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

51910

1

T70

8

T71

65

T72

1

values[0x0]

all_enables

biggest_size

390009

1

T70

85

T71

486

T72

9

values[0x1]

all_enables

biggest_size

51602

1

T70

10

T71

53

T72

4

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2857044	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

451343

1

T70

89

T71

576

T72

11

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1121136	1			T70	214		T71	1368		T72	42
values[0x0]	1067561	1			T70	223		T71	1415		T72	37
values[0x1]	1119690	1			T70	240		T71	1376		T72	37

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2211348	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1097039

1

T70

225

T71

1377

T72

33

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51654	1			T70	19		T71	66		T72	4
valid_sources[0x01]	51346	1			T71	66		T151	3		T76	3
valid_sources[0x02]	50915	1			T70	16		T71	58		T72	6
valid_sources[0x03]	52204	1			T71	72		T151	15		T76	1
valid_sources[0x04]	51115	1			T70	13		T71	72		T151	5
valid_sources[0x05]	51662	1			T70	16		T71	70		T151	6
valid_sources[0x06]	51559	1			T70	5		T71	62		T78	1
valid_sources[0x07]	51492	1			T70	12		T71	62		T151	14
valid_sources[0x08]	52168	1			T71	59		T72	3		T151	2
valid_sources[0x09]	51192	1			T70	7		T71	65		T72	2
valid_sources[0x0a]	52487	1			T70	23		T71	66		T72	4
valid_sources[0x0b]	52396	1			T70	14		T71	63		T151	27
valid_sources[0x0c]	52212	1			T71	70		T72	1		T151	11
valid_sources[0x0d]	51693	1			T71	73		T72	4		T151	8
valid_sources[0x0e]	52199	1			T70	18		T71	54		T72	4
valid_sources[0x0f]	51320	1			T70	10		T71	70		T72	3
valid_sources[0x10]	51643	1			T71	73		T151	4		T76	2
valid_sources[0x11]	51205	1			T71	60		T72	5		T78	2
valid_sources[0x12]	51662	1			T70	26		T71	63		T72	1
valid_sources[0x13]	51475	1			T70	28		T71	71		T72	2
valid_sources[0x14]	51808	1			T70	9		T71	65		T72	3
valid_sources[0x15]	52013	1			T71	61		T72	2		T151	8
valid_sources[0x16]	51888	1			T71	71		T72	7		T78	1
valid_sources[0x17]	51607	1			T71	62		T72	5		T78	1
valid_sources[0x18]	52660	1			T71	71		T72	4		T151	87
valid_sources[0x19]	51208	1			T71	62		T72	4		T151	1
valid_sources[0x1a]	51725	1			T70	37		T71	72		T72	2
valid_sources[0x1b]	50466	1			T70	12		T71	58		T78	4
valid_sources[0x1c]	52463	1			T70	15		T71	57		T72	6
valid_sources[0x1d]	51725	1			T70	20		T71	56		T72	1
valid_sources[0x1e]	52099	1			T70	32		T71	68		T151	6
valid_sources[0x1f]	52502	1			T70	19		T71	71		T72	1
valid_sources[0x20]	51898	1			T70	17		T71	64		T72	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47331

1

T70

7

T71

40

T151

10

values[0x0]

all_enables

biggest_size

356752

1

T70

73

T71

467

T72

9

values[0x1]

all_enables

biggest_size

47260

1

T70

9

T71

69

T72

2