Unified Coverage Report :: Module :: prim_alert_sender

Module : prim_alert_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender	75.00			75.00
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender	87.50			87.50
tb.dut.top_earlgrey.u_pinmux_aon.gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
tb.dut.top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender	100.00			100.00
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.55	95.29	89.29	100.00		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50			87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50			87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.55	95.29	89.29	100.00		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_alert_tx[0].u_prim_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.55	99.11	83.75	98.76		79.12	92.00	u_pinmux_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.96	99.82	100.00	100.00		100.00	90.00	u_rv_plic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.55	95.29	89.29	100.00		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.55	95.29	89.29	100.00		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T43,T156,T55	Yes	T43,T156,T55	INPUT
alert_req_i	Yes	Yes	T234,T118,T235	Yes	T193,T79,T234	INPUT
alert_ack_o	Yes	Yes	T193,T79,T234	Yes	T193,T79,T234	OUTPUT
alert_state_o	Yes	Yes	T234,T118,T86	Yes	T193,T79,T234	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T43,T79,T156	Yes	T43,T79,T156	INPUT
alert_rx_i.ping_n	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
alert_rx_i.ping_p	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T43,T79,T156	Yes	T43,T79,T156	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender

	Total	Covered	Percent
Totals	12	9	75.00
Total Bits	24	18	75.00
Total Bits 0->1	12	9	75.00
Total Bits 1->0	12	9	75.00

Ports	12	9	75.00
Port Bits	24	18	75.00
Port Bits 0->1	12	9	75.00
Port Bits 1->0	12	9	75.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	INPUT
alert_req_i	No	No		No		INPUT
alert_ack_o	No	No		No		OUTPUT
alert_state_o	No	No		No		OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T55,T56,T81	Yes	T55,T56,T81	INPUT
alert_rx_i.ping_n	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
alert_rx_i.ping_p	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T55,T56,T81	Yes	T55,T56,T81	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender

	Total	Covered	Percent
Totals	12	10	83.33
Total Bits	24	21	87.50
Total Bits 0->1	12	11	91.67
Total Bits 1->0	12	10	83.33

Ports	12	10	83.33
Port Bits	24	21	87.50
Port Bits 0->1	12	11	91.67
Port Bits 1->0	12	10	83.33

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	INPUT
alert_req_i	Yes	Yes	T356	Yes	T356	INPUT
alert_ack_o	No	No		No		OUTPUT
alert_state_o	No	No		Yes	T356	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T55,T56,T81	Yes	T55,T56,T81	INPUT
alert_rx_i.ping_n	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
alert_rx_i.ping_p	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T55,T56,T81	Yes	T55,T56,T81	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_alert_tx[0].u_prim_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	INPUT
alert_req_i	Yes	Yes	T86,T88,T89	Yes	T79,T80,T86	INPUT
alert_ack_o	Yes	Yes	T79,T80,T86	Yes	T79,T80,T86	OUTPUT
alert_state_o	Yes	Yes	T86,T88,T89	Yes	T79,T80,T86	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T79,T80,T55	Yes	T79,T80,T55	INPUT
alert_rx_i.ping_n	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
alert_rx_i.ping_p	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T79,T80,T55	Yes	T79,T80,T55	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	INPUT
alert_req_i	Yes	Yes	T377,T412,T413	Yes	T377,T412,T413	INPUT
alert_ack_o	Yes	Yes	T377,T412,T413	Yes	T377,T412,T413	OUTPUT
alert_state_o	Yes	Yes	T377,T412,T413	Yes	T377,T412,T413	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T55,T56,T81	Yes	T55,T56,T81	INPUT
alert_rx_i.ping_n	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
alert_rx_i.ping_p	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T55,T56,T81	Yes	T55,T56,T81	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T43,T156,T55	Yes	T43,T156,T55	INPUT
alert_req_i	Yes	Yes	T49	Yes	T49	INPUT
alert_ack_o	Yes	Yes	T49	Yes	T49	OUTPUT
alert_state_o	Yes	Yes	T49	Yes	T49	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T43,T156,T55	Yes	T43,T156,T55	INPUT
alert_rx_i.ping_n	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
alert_rx_i.ping_p	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T43,T156,T55	Yes	T43,T156,T55	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	INPUT
alert_req_i	Yes	Yes	T234,T118,T235	Yes	T193,T234,T118	INPUT
alert_ack_o	Yes	Yes	T193,T234,T118	Yes	T193,T234,T118	OUTPUT
alert_state_o	Yes	Yes	T234,T118,T236	Yes	T193,T234,T118	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T193,T234,T118	Yes	T193,T234,T118	INPUT
alert_rx_i.ping_n	Yes	Yes	T81,T82,T83	Yes	T82,T83,T252	INPUT
alert_rx_i.ping_p	Yes	Yes	T82,T83,T252	Yes	T81,T82,T83	INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T193,T234,T118	Yes	T193,T234,T118	OUTPUT